SN54LVTH16952, SN74LVTH16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS697G JULY 1997 REVISED APRIL 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
TM
Family
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The 'LVTH16952 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) V
CC
operation, but
with the capability to provide a TTL interface to a 5-V system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is stored
in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable
(CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data
on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
CC
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
SN54LVTH16952 . . . WD PACKAGE
SN74LVTH16952 . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1CLKAB
1CLKENAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CLKENAB
2CLKAB
2OEAB
1OEBA
1CLKBA
1CLKENBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CLKENBA
2CLKBA
2OEBA
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVTH16952, SN74LVTH16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS697G JULY 1997 REVISED APRIL 2000
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH16952 is characterized for operation over the full military temperature range of 55
C to 125
C.
The SN74LVTH16952 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
INPUTS
OUTPUT
CLKENAB
CLKAB
OEAB
A
B
H
X
L
X
B0
X
L
L
X
B0
L
L
L
L
L
L
H
H
X
X
H
X
Z
A-to-B data flow is shown; B-to-A data flow is similar, but
uses CLKENBA, CLKBA, and OEBA.
Level of B before the indicated steady-state input
conditions were established
SN54LVTH16952, SN74LVTH16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS697G JULY 1997 REVISED APRIL 2000
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
1OEBA
1CLKENBA
1OEAB
1CLKENAB
2OEBA
2CLKENBA
2OEAB
2CLKENAB
G8
26
27
2CLKAB
8C12
1A1
5
6D
1A2
6
1A3
8
1A4
9
1A5
10
1A6
12
1A7
13
1A8
14
1B1
52
5D
1B6
45
1B7
44
1B8
43
1B2
51
1B3
49
1B4
48
1B5
47
EN10
28
G7
31
30
2CLKBA
7C11
EN9
29
G2
3
2
1CLKAB
2C6
EN4
1
G1
54
55
1CLKBA
1C5
EN3
56
3
4
2A1
15
12D
2A2
16
2A3
17
2A4
19
2A5
20
2A6
21
2A7
23
2A8
24
2B1
42
11D
2B6
36
2B7
34
2B8
33
2B2
41
2B3
40
2B4
38
2B5
37
9
10
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54LVTH16952, SN74LVTH16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS697G JULY 1997 REVISED APRIL 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
One of Eight
Channels
1A1
One of Eight
Channels
To Seven Other Channels
1CLKAB
1CLKBA
1OEBA
1OEAB
1B1
1CLKENAB
1CLKENBA
To Seven Other Channels
2CLKAB
2CLKBA
2OEBA
2OEAB
2A1
2B1
2CLKENAB
2CLKENBA
3
2
56
5
26
27
29
15
C1
CE
1D
54
55
1
52
31
30
28
42
C1
CE
1D
C1
CE
1D
C1
CE
1D
SN54LVTH16952, SN74LVTH16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS697G JULY 1997 REVISED APRIL 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54LVTH16952 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH16952 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2): SN54LVTH16952
48 mA
. . . . . . . . . . . . . . . . . . . . .
SN74LVTH16952 64
mA
. . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGG package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
56
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH16952
SN74LVTH16952
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2.7
3.6
2.7
3.6
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t/
v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54LVTH16952, SN74LVTH16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS697G JULY 1997 REVISED APRIL 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVTH16952
SN74LVTH16952
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 2.7 V,
II = 18 mA
1.2
1.2
V
VCC = 2.7 V to 3.6 V,
IOH = 100
A
VCC0.2
VCC0.2
VOH
VCC = 2.7 V,
IOH = 8 mA
2.4
2.4
V
VOH
VCC = 3 V
IOH = 24 mA
2
V
VCC = 3 V
IOH = 32 mA
2
VCC = 2 7 V
IOL = 100
A
0.2
0.2
VCC = 2.7 V
IOL = 24 mA
0.5
0.5
VOL
IOL = 16 mA
0.4
0.4
V
VOL
VCC = 3 V
IOL = 32 mA
0.5
0.5
V
VCC = 3 V
IOL = 48 mA
0.55
IOL = 64 mA
0.55
Control
VCC = 3.6 V,
VI = VCC or GND
1
1
inputs
VCC = 0 or 3.6 V,
VI = 5.5 V
10
10
II
A
B
VI = 5.5 V
20
20
A
A or B
ports
VCC = 3.6 V
VI = VCC
1
1
orts
VI = 0
5
5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
100
A
VCC = 3 V
VI = 0.8 V
75
75
II(hold) A or B ports
VCC = 3 V
VI = 2 V
75
75
A
(
)
VCC = 3.6 V,
VI = 0 to 3.6 V
500
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
100
100
A
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don't care
100
100
A
VCC = 3.6 V,
Outputs high
0.19
0.19
ICC
VCC = 3.6 V,
IO = 0,
Outputs low
5
5
mA
VI = VCC or GND
Outputs disabled
0.19
0.19
ICC
VCC = 3 V to 3.6 V, One input at VCC 0.6 V,
Other inputs at VCC or GND
0.2
0.2
mA
Ci
VI = 3 V or 0
4
4
pF
Cio
VO = 3 V or 0
10
10
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
Unused pins at VCC or GND
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
SN54LVTH16952, SN74LVTH16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS697G JULY 1997 REVISED APRIL 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH16952
SN74LVTH16952
VCC = 3.3 V
0.3 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
150
150
150
150
MHz
tw
Pulse duration
CLK high or low
3.3
3.3
3.3
3.3
ns
t
Setup time
A or B before CLK
2.6
3.3
1.7
2.5
ns
tsu
Setup time
CLKEN before CLK
2.2
2.8
2
2.8
ns
th
Hold time
A or B after CLK
1
1
0.8
0
ns
th
Hold time
CLKEN after CLK
1.4
1.5
0.4
0
ns
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH16952
SN74LVTH16952
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
0.3 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
fmax
150
150
150
150
MHz
tPLH
CLKBA or
A or B
1.6
5.7
7.4
1.3
2.7
4
4.4
ns
tPHL
CLKBA or
CLKAB
A or B
1.7
6
7
1.3
2.7
4
4.4
ns
tPZH
OEBA or OEAB
A or B
0.9
5
7.3
1
2.3
4
4.9
ns
tPZL
OEBA or OEAB
A or B
1.1
5.2
5.9
1
2.4
4
4.9
ns
tPHZ
OEBA or OEAB
A or B
1.7
6.7
7.3
2.1
3.9
5.7
6.2
ns
tPLZ
OEBA or OEAB
A or B
1.1
5.8
6
2.1
3.5
5.1
5.3
ns
All typical values are at VCC = 3.3 V, TA = 25
C.
SN54LVTH16952, SN74LVTH16952
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS697G JULY 1997 REVISED APRIL 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
Data Input
Timing Input
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
2.7 V
0 V
Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOL + 0.3 V
VOH 0.3 V
0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
th
tsu
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
5962-9684901QXA
ACTIVE
CFP
WD
56
1
TBD
Call TI
Level-NC-NC-NC
74LVTH16952DGGRE4
ACTIVE
TSSOP
DGG
56
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
74LVTH16952DLRG4
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16952DGGR
ACTIVE
TSSOP
DGG
56
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74LVTH16952DL
ACTIVE
SSOP
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16952DLR
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54LVTH16952WD
ACTIVE
CFP
WD
56
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
Addendum-Page 1
MECHANICAL DATA
MCFP010B JANUARY 1995 REVISED NOVEMBER 1997
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
4040176 / D 10/97
48 LEADS SHOWN
48
48
25
56
0.610
(18,80)
0.710
(18,03)
0.740
0.640
0.390 (9,91)
0.370 (9,40)
0.870 (22,10)
1.130 (28,70)
1
A
0.120 (3,05)
0.075 (1,91)
LEADS**
24
NO. OF
A MIN
A MAX
(16,26)
(15,49)
0.025 (0,635)
0.009 (0,23)
0.004 (0,10)
0.370 (9,40)
0.250 (6,35)
0.370 (9,40)
0.250 (6,35)
0.014 (0,36)
0.008 (0,20)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO -146AA
GDFP1-F56 and JEDEC MO -146AB
MECHANICAL DATA
MSSO001C JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040048 / E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
48
28
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0
8
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040078 / F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0
8
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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