SN54AHCT573, SN74AHCT573 (Rev. N)
SN54AHCT573, SN74AHCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS243N OCTOBER 1995 REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
description/ordering information
The 'AHCT573 devices are octal transparent
D-type latches. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the
logic levels of the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
To ensure the high-impedance state during power
up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
Tube
SN74AHCT573N
SN74AHCT573N
SOIC
DW
Tube
SN74AHCT573DW
AHCT573
SOIC DW
Tape and reel
SN74AHCT573DWR
AHCT573
40
C to 85
C
SOP NS
Tape and reel
SN74AHCT573NSR
AHCT573
40
C to 85
C
SSOP DB
Tape and reel
SN74AHCT573DBR
HB573
TSSOP
PW
Tube
SN74AHCT573PW
HB573
TSSOP PW
Tape and reel
SN74AHCT573PWR
HB573
TVSOP DGV
Tape and reel
SN74AHCT573DGVR
HB573
CDIP J
Tube
SNJ54AHCT573J
SNJ54AHCT573J
55
C to 125
C
CFP W
Tube
SNJ54AHCT573W
SNJ54AHCT573W
LCCC FK
Tube
SNJ54AHCT573FK
SNJ54AHCT573FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54AHCT573 . . . J OR W PACKAGE
SN74AHCT573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54AHCT573 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q
1Q
8D
GND
LE
V
CC
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AHCT573, SN74AHCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS243N OCTOBER 1995 REVISED JULY 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
2
19
LE
1D
C1
1D
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
75 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DB package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
92
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
60
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54AHCT573, SN74AHCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS243N OCTOBER 1995 REVISED JULY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54AHCT573
SN74AHCT573
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
4.5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
8
8
mA
IOL
Low-level output current
8
8
mA
t/
v
Input transition rise or fall rate
20
20
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54AHCT573
SN74AHCT573
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
IOH = 50
m
A
4 5 V
4.4
4.5
4.4
4.4
V
VOH
IOH = 8 mA
4.5 V
3.94
3.8
3.8
V
VOL
IOL = 50
m
A
4 5 V
0.1
0.1
0.1
V
VOL
IOL = 8 mA
4.5 V
0.36
0.44
0.44
V
II
VI = 5.5 V or GND
0 V to 5.5 V
0.1
1*
1
m
A
IOZ
VO = VCC or GND
5.5 V
0.25
2.5
2.5
m
A
ICC
VI = 5.5 V or GND,
IO = 0
5.5 V
4
40
40
m
A
ICC
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
1.35
1.5
1.5
mA
Ci
VI = VCC or GND
5 V
2.5
10
10
pF
Co
VO = VCC or GND
5 V
3
pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, V
cc
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
SN54AHCT573
SN74AHCT573
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
5
5
5
ns
tsu
Setup time, data before LE
3.5
3.5
3.5
ns
th
Hold time, data after LE
1.5
1.5
1.5
ns
SN54AHCT573, SN74AHCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS243N OCTOBER 1995 REVISED JULY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54AHCT573
SN74AHCT573
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
D
Q
CL = 15 pF
4.2*
6*
1*
6.5*
1
6.5
ns
tPHL
D
Q
CL = 15 pF
5.1*
7*
1*
9*
1
9
ns
tPLH
LE
Q
CL = 15 pF
4.7*
6.5*
1*
7.5*
1
7.5
ns
tPHL
LE
Q
CL = 15 pF
5.6*
7.5*
1*
9*
1
9
ns
tPZH
OE
Q
CL = 15 pF
4.1*
6.5*
1*
7*
1
7
ns
tPZL
OE
Q
CL = 15 pF
5.5*
7.5*
1*
10*
1
10
ns
tPHZ
OE
Q
CL = 15 pF
5.5*
8*
1*
11*
1
11
ns
tPLZ
OE
Q
CL = 15 pF
5.4*
8*
1*
9.5*
1
9.5
ns
tPLH
D
Q
CL = 50 pF
5.2
7
1
7.5
1
7.5
ns
tPHL
D
Q
CL = 50 pF
6.1
8
1
10
1
10
ns
tPLH
LE
Q
CL = 50 pF
5.7
7.5
1
8.5
1
8.5
ns
tPHL
LE
Q
CL = 50 pF
6.6
8.5
1
10
1
10
ns
tPZH
OE
Q
CL = 50 pF
5.1
7.5
1
8
1
8
ns
tPZL
OE
Q
CL = 50 pF
6.5
8.5
1
11
1
11
ns
tPHZ
OE
Q
CL = 50 pF
6.7
9
1
12
1
12
ns
tPLZ
OE
Q
CL = 50 pF
6.4
9
1
10.5
1
10.5
ns
tsk(o)
CL = 50 pF
1.5**
1.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load,
f = 1 MHz
16
pF
SN54AHCT573, SN74AHCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS243N OCTOBER 1995 REVISED JULY 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
50% VCC
VOL
+ 0.3 V
50% VCC
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST
S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr
3 ns, tf
3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 k
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH
0.3 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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