SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255J DECEMBER 1995 REVISED JULY 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Operating Range 2-V to 5.5-V V
CC
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54AHC74 . . . J OR W PACKAGE
SN74AHC74 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q
V
2CLR
1Q
GND
NC
SN54AHC74 . . . FK PACKAGE
(TOP VIEW)
CC
NC No internal connection
SN74AHC74 . . . RGY PACKAGE
(TOP VIEW)
1
14
7
8
2
3
4
5
6
13
12
11
10
9
2CLR
2D
2CLK
2PRE
2Q
1D
1CLK
1PRE
1Q
1Q
1CLR
2Q
V
GND
CC
description/ordering information
The 'AHC74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN RGY
Tape and reel
SN74AHC74RGYR
HA74
PDIP N
Tube
SN74AHC74N
SN74AHC74N
SOIC D
Tube
SN74AHC74D
AHC74
SOIC D
Tape and reel
SN74AHC74DR
AHC74
40
C to 85
C
SOP NS
Tape and reel
SN74AHC74NSR
AHC74
SSOP DB
Tape and reel
SN74AHC74DBR
HA74
TSSOP
PW
Tube
SN74AHC74PW
HA74
TSSOP PW
Tape and reel
SN74AHC74PWR
HA74
TVSOP DGV
Tape and reel
SN74AHC74DGVR
HA74
CDIP J
Tube
SNJ54AHC74J
SNJ54AHC74J
55
C to 125
C
CFP W
Tube
SNJ54AHC74W
SNJ54AHC74W
LCCC FK
Tube
SNJ54AHC74FK
SNJ54AHC74FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255J DECEMBER 1995 REVISED JULY 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255J DECEMBER 1995 REVISED JULY 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DB package
96
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package
127
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package
113
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package
47
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
SN54AHC74
SN74AHC74
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2
5.5
2
5.5
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 3 V
2.1
2.1
V
VCC = 5.5 V
3.85
3.85
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 3 V
0.9
0.9
V
VCC = 5.5 V
1.65
1.65
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
50
50
m
A
IOH
High-level output current
VCC = 3.3 V
0.3 V
4
4
mA
VCC = 5 V
0.5 V
8
8
mA
VCC = 2 V
50
50
m
A
IOL
Low-level output current
VCC = 3.3 V
0.3 V
4
4
mA
VCC = 5 V
0.5 V
8
8
mA
t
/
v
Input transition rise or fall rate
VCC = 3.3 V
0.3 V
100
100
ns/V
t
/
v
Input transition rise or fall rate
VCC = 5 V
0.5 V
20
20
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255J DECEMBER 1995 REVISED JULY 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54AHC74
SN74AHC74
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
1.9
2
1.9
1.9
IOH = 50
m
A
3 V
2.9
3
2.9
2.9
VOH
4.5 V
4.4
4.5
4.4
4.4
V
IOH = 4 mA
3 V
2.58
2.48
2.48
IOH = 8 mA
4.5 V
3.94
3.8
3.8
2 V
0.1
0.1
0.1
IOL = 50
m
A
3 V
0.1
0.1
0.1
VOL
4.5 V
0.1
0.1
0.1
V
IOL = 4 mA
3 V
0.36
0.5
0.44
IOL = 8 mA
4.5 V
0.36
0.5
0.44
II
VI = 5.5 V or GND
0 V to 5.5 V
0.1
1*
1
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
2
20
20
m
A
Ci
VI = VCC or GND
5 V
2
10
10
pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
SN54AHC74
SN74AHC74
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
PRE or CLR low
6
7
7
ns
tw
Pulse duration
CLK
6
7
7
ns
t
Setup time before CLK
Data
6
7
7
ns
tsu
Setup time before CLK
PRE or CLR inactive
5
5
5
ns
th
Hold time, data after CLK
0.5
0.5
0.5
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
SN54AHC74
SN74AHC74
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
t
Pulse duration
PRE or CLR low
5
5
5
ns
tw
Pulse duration
CLK
5
5
5
ns
t
Setup time before CLK
Data
5
5
5
ns
tsu
Setup time before CLK
PRE or CLR inactive
3
3
3
ns
th
Hold time, data after CLK
0.5
0.5
0.5
ns
SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255J DECEMBER 1995 REVISED JULY 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54AHC74
SN74AHC74
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
f
CL = 15 pF
80*
125*
70*
70
MHz
fmax
CL = 50 pF
50
75
45
45
MHz
tPLH
PRE or CLR
Q or Q
CL = 15 pF
7.6*
12.3*
1*
14.5*
1
14.5
ns
tPHL
PRE or CLR
Q or Q
CL = 15 pF
7.6*
12.3*
1*
14.5*
1
14.5
ns
tPLH
CLK
Q
Q
CL = 15 pF
6.7*
11.9*
1*
14*
1
14
ns
tPHL
CLK
Q or Q
CL = 15 pF
6.7*
11.9*
1*
14*
1
14
ns
tPLH
PRE
CLR
Q
Q
CL = 50 pF
10.1
15.8
1
18
1
18
ns
tPHL
PRE or CLR
Q or Q
CL = 50 pF
10.1
15.8
1
18
1
18
ns
tPLH
CLK
Q or Q
CL = 50 pF
9.2
15.4
1
17.5
1
17.5
ns
tPHL
CLK
Q or Q
CL = 50 pF
9.2
15.4
1
17.5
1
17.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
TA = 25
C
SN54AHC74
SN74AHC74
UNIT
PARAMETER
(INPUT)
(OUTPUT)
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
f
CL = 15 pF
130*
170*
110*
110
MHz
fmax
CL = 50 pF
90
115
75
75
MHz
tPLH
PRE
CLR
Q
Q
CL = 15 pF
4.8*
7.7*
1*
9*
1
9
ns
tPHL
PRE or CLR
Q or Q
CL = 15 pF
4.8*
7.7*
1*
9*
1
9
ns
tPLH
CLK
Q or Q
CL = 15 pF
4.6*
7.3*
1*
8.5*
1
8.5
ns
tPHL
CLK
Q or Q
CL = 15 pF
4.6*
7.3*
1*
8.5*
1
8.5
ns
tPLH
PRE
CLR
Q
Q
CL = 50 pF
6.3
9.7
1
11
1
11
ns
tPHL
PRE or CLR
Q or Q
CL = 50 pF
6.3
9.7
1
11
1
11
ns
tPLH
CLK
Q or Q
CL = 50 pF
6.1
9.3
1
10.5
1
10.5
ns
tPHL
CLK
Q or Q
CL = 50 pF
6.1
9.3
1
10.5
1
10.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
CC
= 5 V, C
L
= 50 pF, T
A
= 25
C (see Note 5
)
PARAMETER
SN74AHC74
UNIT
PARAMETER
MIN
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4.7
V
VIH(D)
High-level dynamic input voltage
3.5
V
VIL(D)
Low-level dynamic input voltage
1.5
V
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load,
f = 1 MHz
32
pF
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