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FEATURES
SN54GTL16612 . . . WD PACKAGE
SN74GTL16612 . . . DGG OR DL PACKAGE
(TOP VIEW)
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OEAB
LEAB
A1
GND
A2
A3
V
CC
(3.3 V)
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
(3.3 V)
A16
A17
GND
A18
OEBA
LEBA
CEAB
CLKAB
B1
GND
B2
B3
V
CC
(5 V)
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
REF
B16
B17
GND
B18
CLKBA
CEBA
DESCRIPTION/ORDERING INFORMATION
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K JUNE 1994 REVISED JULY 2005
Members of Texas Instruments WidebusTM
Family
UBTTM Transceivers Combine D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, or
Clock-Enabled Modes
OECTM Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
Identical to '16601 Function
I
off
Supports Partial-Power-Down Mode
Operation
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors on
A Port
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 500 mA Per
JESD 17
The
'GTL16612
devices
are
18-bit
UBTTM
transceivers
that
provide
LVTTL-to-GTL/GTL+
and
GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for
transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The
devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at
GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced
input threshold levels, and OECTM circuitry.
The user has the flexibility of using these devices at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or the preferred
higher noise margin GTL+ (V
TT
= 1.5 V and V
REF
= 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V
REF
is the reference input voltage for the B port.
V
CC
(5 V) supplies the internal and GTL circuitry while V
CC
(3.3 V) supplies the LVTTL output buffers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 19942005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K JUNE 1994 REVISED JULY 2005
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable(LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs.
For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A
data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs
are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that
for A to B, but uses OEBA, LEBA, CLKBA, and CEBA.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Tube
SN74GTL16612DL
SSOP DL
GTL16612
40
C to 85
C
Tape and reel
SN74GTL16612DLR
TSSOP DGG
Tape and reel
SN74GTL16612DGGR
GTL16612
55
C to 125
C
CFP WD
Tube
SNJ54GTL16612WD
SNJ54GTL16612WD
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(1)
INPUTS
OUTPUT
MODE
B
CEAB
OEAB
LEAB
CLKAB
A
X
H
X
X
X
Z
Isolation
L
L
L
H
X
B
0
(2)
Latched storage of A data
L
L
L
L
X
B
0
(3)
X
L
H
X
L
L
Transparent
X
L
H
X
H
H
L
L
L
L
L
Clocked storage of A data
L
L
L
H
H
H
L
L
X
X
B
0
(3)
Clock inhibit
(1)
A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA.
(2)
Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low
(3)
Output level before the indicated steady-state input conditions were established
2
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1D
C1
CLK
1D
C1
CLK
B1
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
To 17 Other Channels
CE
CE
1
56
55
2
28
30
29
27
3
54
V
REF
35
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K JUNE 1994 REVISED JULY 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
3
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1) (2) (3) (4)
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K JUNE 1994 REVISED JULY 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
3.3 V
0.5
4.6
V
CC
Supply voltage range
V
5 V
0.5
7
A-port and control inputs
0.5
7
V
I
Input voltage range
(2)
V
B port and V
REF
0.5
4.6
A port
0.5
7
V
O
Voltage range applied to any output in the high or power-off state
(2)
V
B port
0.5
4.6
A port
128
I
O
Current into any output in the low state
mA
B port
80
I
O
Current into any A-port output in the high state
(3)
64
mA
Continuous current through each V
CC
or GND
100
mA
I
IK
Input clamp current
V
I
< 0
50
mA
I
OK
Output clamp current
V
O
< 0
50
mA
DGG package
64
JA
Package thermal impedance
(4)
C/W
DL package
56
T
stg
Storage temperature range
65
150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
This current flows only when the output is in the high state and V
O
> V
CC
.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
SN54GTL16612
SN74GTL16612
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
3.3 V
3.15
3.3
3.45
3.15
3.3
3.45
V
CC
Supply voltage
V
5 V
4.75
5
5.25
4.75
5
5.25
GTL
1.14
1.2
1.26
1.14
1.2
1.26
Termination
V
TT
V
voltage
GTL+
1.35
1.5
1.65
1.35
1.5
1.65
GTL
0.74
0.8
0.87
0.74
0.8
0.87
V
REF
Reference voltage
V
GTL+
0.87
1
1.1
0.87
1
1.1
B port
V
TT
V
TT
V
I
Input voltage
V
Except B port
5.5
5.5
B port
V
REF
+ 50 mV
V
REF
+ 50 mV
High-level
V
IH
V
input voltage
Except B port
2
2
B port
V
REF
50 mV
V
REF
50 mV
Low-level
V
IL
V
input voltage
Except B port
0.8
0.8
I
IK
Input clamp current
18
18
mA
High-level
I
OH
A port
32
32
mA
output current
A port
64
64
Low-level
I
OL
mA
output current
B port
40
40
T
A
Operating free-air temperature
55
125
40
85
C
(1)
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2)
Normal connection sequence is GND first, V
CC
= 5 V second, and V
CC
= 3.3 V, I/O, control inputs, V
TT
and V
REF
(any order) last.
(3)
V
TT
and R
TT
can be adjusted to accommodate backplane impedances if the dc recommended I
OL
ratings are not exceeded.
(4)
V
REF
can be adjusted to optimize noise margins, but normally is two-thirds V
TT
.
4
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Electrical Characteristics
SN54GTL16612, SN74GTL16612
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K JUNE 1994 REVISED JULY 2005
over recommended operating free-air temperature range (unless otherwise noted)
SN54GTL16612
SN74GTL16612
PARAMETER
TEST CONDITIONS
UNIT
MIN TYP
(1)
MAX
MIN TYP
(1)
MAX
V
CC
(3.3 V) = 3.15 V,
V
IK
I
I
= 18 mA
1.2
1.2
V
V
CC
(5 V) = 4.75 V
V
CC
(3.3 V) = 3.15 V to
V
CC
(3.3 V)
V
CC
(3.3 V)
3.45 V,
I
OH
= 100
A
0.2
0.2
V
CC
(5 V) = 4.75 V to 5.25 V
V
OH
A port
V
I
OH
= 8 mA
2.4
2.4
V
CC
(3.3 V) = 3.15 V,
V
CC
(5 V) = 4.75 V
I
OH
= 32 mA
2
2
I
OL
= 100
A
0.2
0.2
I
OL
= 16 mA
0.4
0.4
V
CC
(3.3 V) = 3.15 V,
A port
V
CC
(5 V) = 4.75 V
I
OL
= 32 mA
0.5
0.5
V
OL
V
I
OL
= 64 mA
0.6
0.55
V
CC
(3.3 V) = 3.15 V, V
CC
(5 V) = 4.75 V,
B port
0.5
0.4
I
OL
= 40 mA
Control
V
CC
(3.3 V) = 0 or 3.45 V,
V
I
= 5.5 V
10
10
inputs
V
CC
(5 V) = 0 or 5.25 V
V
I
= 5.5 V
1000
20
V
CC
(3.3 V) = 3.45 V,
A port
V
I
= V
CC
(3.3 V)
1
1
I
I
A
V
CC
(5 V) = 5.25 V
V
I
= 0
30
30
V
I
= V
CC
(3.3 V)
5
5
V
CC
(3.3 V) = 3.45 V,
B port
V
CC
(5 V) = 5.25 V
V
I
= 0
5
5
I
off
V
CC
= 0,
V
I
or V
O
= 0 to 4.5 V
1000
100
A
V
I
= 0.8 V
75
75
V
CC
(3.3 V) = 3.15 V,
V
I
= 2 V
75
75
I
I(hold)
A port
A
V
CC
(5 V) = 4.75 V
V
I
= 0 to V
CC
500
500
(3.3 V)
(2)
A port
V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V, V
O
= 3 V
1
1
I
OZH
A
B port
V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V, V
O
= 1.2 V
10
10
A port
V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V, V
O
= 0.5 V
1
1
I
OZL
A
B port
V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V, V
O
= 0.4 V
10
10
Outputs high
1
1
V
CC
(3.3 V) = 3.45 V,
I
CC
A or B
V
CC
(5 V) = 5.25 V, I
O
= 0,
Outputs low
5
5
mA
(3.3 V) port
V
I
= V
CC
(3.3 V) or GND
Outputs disabled
1
1
Outputs high
120
120
V
CC
(3.3 V) = 3.45 V,
I
CC
A or B
V
CC
(5 V) = 5.25 V, I
O
= 0,
Outputs low
120
120
mA
(5 V)
port
V
I
= V
CC
(3.3 V) or GND
Outputs disabled
120
120
V
CC
(3.3 V) = 3.45 V, V
CC
(5 V) = 5.25 V,
I
CC
(3)
A-port or control inputs at V
CC
(3.3 V) or GND,
1
1
mA
One input at 2.7 V
Control
C
i
V
I
= 3.15 V or 0
3.5
12
3.5
pF
inputs
A port
12
18
12
C
io
V
O
= 3.15 V or 0
pF
B port
10
5
(1)
All typical values are at V
CC
(3.3 V) = 3.3 V, V
CC
(5 V) = 5 V, T
A
= 25C.
(2)
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3)
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC
or GND.
5
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