SN54F74, SN74F74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS046A MARCH 1987 REVISED OCTOBER 1993
Copyright
1993, Texas Instruments Incorporated
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
These devices contain two independent positive-
edge-triggered D-type flip-flops. A low level at the
preset (PRE) or clear (CLR) inputs sets or resets
the outputs regardless of the levels of the other
inputs. When PRE and CLR are inactive (high),
data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the
D input may be changed without affecting the
levels at the outputs.
The SN54F74 is characterized for operation over
the full military temperature range of 55
C to
125
C. The SN74F74 is characterized for
operation from 0
C to 70
C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
The output levels are not guaranteed to meet the
minimum levels for VOH. Furthermore, this
configuration is nonstable; that is, it will not persist
when PRE or CLR returns to its inactive (high)
level.
SN54F74 . . . J PACKAGE
SN74F74 . . . D OR N PACKAGE
(TOP VIEW)
SN54F74 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q
V
2CLR
1Q
GND
NC
CC
NC No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54F74, SN74F74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS046A MARCH 1987 REVISED OCTOBER 1993
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
S
4
3
1CLK
1D
2
1D
R
1
1Q
5
6
C1
10
11
2CLK
12
2D
13
2Q
9
8
1PRE
2PRE
1CLR
2CLR
1Q
2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
1.2 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range
30 mA to 5 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state
0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state
40 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: SN54F74
55
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74F74
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
SN54F74, SN74F74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS046A MARCH 1987 REVISED OCTOBER 1993
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
SN54F74
SN74F74
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IIK
Input clamp current
18
18
mA
IOH
High-level output current
1
1
mA
IOL
Low-level output current
20
20
mA
TA
Operating free-air temperature
55
125
0
70
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54F74
SN74F74
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
VOH
VCC = 4.5 V,
IOH = 1 mA
2.5
3.4
2.5
3.4
V
VOH
VCC = 4.75 V,
IOH = 1 mA
2.7
V
VOL
VCC = 4.5 V,
IOL = 20 mA
0.3
0.5
0.3
0.5
V
II
VCC = 5.5 V,
VI = 7 V
0.1
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
Data, CLK
VCC = 5 5 V
VI = 0 5 V
0.6
0.6
mA
IIL
PRE or CLR
VCC = 5.5 V,
VI = 0.5 V
1.8
1.8
mA
IOS
VCC = 5.5 V,
VO = 0
60
150
60
150
mA
ICC
VCC = 5.5 V,
See Note 2
10.5
16
10.5
16
mA
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 2: ICC is measured with D, CLK, and PRE grounded then with D, CLK, and CLR grounded.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25
C
SN54F74
SN74F74
UNIT
F74
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
fclock
Clock frequency
0
100
0
80
0
100
MHz
t
Pulse duration
CLK high, PRE or CLR low
4
4
4
ns
tw
Pulse duration
CLK low
5
6
5
ns
Setup time data before CLK
High
2
3
2
tsu
Setup time, data before CLK
Low
3
4
3
ns
su
Setup time, inactive-state before CLK
PRE or CLR to CLK
2
3
2
th
Hold time data after CLK
High
1
2
1
ns
th
Hold time, data after CLK
Low
1
2
1
ns
Inactive-state setup time is also referred to as recovery time.
SN54F74, SN74F74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDFS046A MARCH 1987 REVISED OCTOBER 1993
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics (see Note 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
RL = 500
,
TA = 25
C
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
UNIT
(INPUT)
(OUTPUT)
F74
SN54F74
SN74F74
MIN
TYP
MAX
MIN
MAX
MIN
MAX
fmax
100
145
80
100
MHz
tPLH
CLK
Q or Q
3
4.9
6.8
3.8
8.5
3
7.8
ns
tPHL
CLK
Q or Q
3.6
5.8
8
4.4
10.5
3.6
9.2
ns
tPLH
PRE or CLR
Q or Q
2.4
4.2
6.1
3.2
8
2.4
7.1
ns
tPHL
PRE or CLR
Q or Q
2.7
6.6
9
3.5
11.5
2.7
10.5
ns
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 3: Load circuits and waveforms are shown in Section 1.
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
5962-9759201Q2A
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
5962-9759201QCA
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
5962-9759201QDA
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
JM38510/34101B2A
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
JM38510/34101BCA
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
JM38510/34101BDA
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
SN54F74J
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
SN74F74D
ACTIVE
SOIC
D
14
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74F74DR
ACTIVE
SOIC
D
14
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74F74N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74F74N3
OBSOLETE
PDIP
N
14
None
Call TI
Call TI
SN74F74NSR
ACTIVE
SO
NS
14
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SNJ54F74FK
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
SNJ54F74J
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
SNJ54F74W
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check
http://www.ti.com/productcontent
for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
Addendum-Page 1
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