SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3 STATE OUTPUTS
SCAS302J - JANUARY 1993 - REVISED AUGUST 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Operate From 1.65 V to 3.6 V
D
Inputs Accept Voltages to 5.5 V
D
Max t
pd
of 7.4 ns at 3.3 V
D
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25
C
D
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
CC
)
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN54LVC646A . . . JT OR W PACKAGE
SN74LVC646A . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
4
3
2 1 28
12 13 14 15 16
OE
B1
B2
NC
B3
B4
B5
A1
A2
A3
NC
A4
A5
A6
SN54LVC646A . . . FK PACKAGE
(TOP VIEW)
DIR
SAB
CLKAB
B8
B7
A8
GND
NC
NC
CLKBA
SBA
V
A7
B6
17 18
27 26
CC
NC - No internal connection
description/ordering information
The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V V
CC
operation, and the
SN74LVC646A octal bus transceiver and register is designed for 1.65-V to 3.6-V V
CC
operation.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC - DW
Tube of 25
SN74LVC646ADW
LVC646A
SOIC - DW
Reel of 2000
SN74LVC646ADWR
LVC646A
SOP - NS
Reel of 2000
SN74LVC646ANSR
LVC646A
-40
C to 85
C
SSOP - DB
Reel of 2000
SN74LVC646ADBR
LC646A
-40 C to 85 C
Tube of 60
SN74LVC646APW
TSSOP - PW
Reel of 2000
SN74LVC646APWR
LC646A
TSSOP - PW
Reel of 250
SN74LVC646APWT
LC646A
CDIP - JT
Tube of 15
SNJ54LVC646AJT
SNJ54LVC646AJT
-55
C to 125
C
CFP - W
Tube of 85
SNJ54LVC646AW
SNJ54LVC646AW
-55 C to 125 C
LCCC - FK
Tube of 42
SNJ54LVC646AFK
SNJ54LVC646AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3 STATE OUTPUTS
SCAS302J - JANUARY 1993 - REVISED AUGUST 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that are performed with the 'LVC646A devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port is stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one
register and B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1-A8
B1-B8
OPERATION OR FUNCTION
X
X
X
X
X
Input
Unspecified
Store A, B unspecified
X
X
X
X
X
Unspecified
Input
Store B, A unspecified
H
X
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
H or L
X
H
X
Input
Output
Stored A data to B bus
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3 STATE OUTPUTS
SCAS302J - JANUARY 1993 - REVISED AUGUST 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
X
2
SAB
X
22
SBA
L
21
L
3
DIR
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
22
SBA
X
21
X
3
DIR
X
1
CLKAB
23
CLKBA
X
2
SAB
X
22
SBA
X
21
L
3
DIR
L
1
CLKAB
X
23
CLKBA
H or L
2
SAB
X
22
SBA
H
X
H
X
X
X
X
X
X
X
L
H
H or L
X
H
X
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
BUS B
BUS A
OE
OE
OE
OE
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3 STATE OUTPUTS
SCAS302J - JANUARY 1993 - REVISED AUGUST 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
A1
B1
One of Eight Channels
SAB
CLKAB
SBA
CLKBA
DIR
OE
To Seven Other Channels
21
3
23
22
1
2
4
20
1D
C1
1D
C1
Pin numbers shown are for the DB, DW, JT, NS, PW, and W packages.
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3 STATE OUTPUTS
SCAS302J - JANUARY 1993 - REVISED AUGUST 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1)
-0.5 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DB package
63
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
46
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
65
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
88
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54LVC646A
SN74LVC646A
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
Operating
2
3.6
1.65
3.6
V
VCC
Supply voltage
Data retention only
1.5
1.5
V
VCC = 1.65 V to 1.95 V
0.65
VCC
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
2
2
V
VCC = 1.65 V to 1.95 V
0.35
VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
0.8
0.8
V
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
High or low state
0
VCC
0
VCC
V
VO
Output voltage
3-state
0
5.5
0
5.5
V
VCC = 1.65 V
-4
IOH
High-level output current
VCC = 2.3 V
-8
mA
IOH
High-level output current
VCC = 2.7 V
-12
-12
mA
VCC = 3 V
-24
-24
VCC = 1.65 V
4
IOL
Low-level output current
VCC = 2.3 V
8
mA
IOL
Low-level output current
VCC = 2.7 V
12
12
mA
VCC = 3 V
24
24
t/
v
Input transition rise or fall rate
10
10
ns/V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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