SN54CBT16212A, SN74CBT16212A
24 BIT FET BUS EXCHANGE SWITCHES
SCDS007T - NOVEMBER 1992 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
5-
Switch Connection Between Two Ports
D
TTL-Compatible Input Levels
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
description/ordering information
The 'CBT16212A devices provide 24 bits of
high-speed TTL-compatible bus switching or
exchanging. The low on-state resistance of the
switch allows connections to be made with
minimal propagation delay.
Each device operates as a 24-bit bus switch or a
12-bit bus exchanger that provides data
exchanging between the four signal ports via the
data-select (S0, S1, S2) terminals.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP - DL
Tube
SN74CBT16212ADL
CBT16212A
SSOP - DL
Tape and reel
SN74CBT16212ADLR
CBT16212A
-40
C to 85
C
TSSOP - DGG
Tape and reel
SN74CBT16212ADGGR
CBT16212A
-40
C to 85
C
TVSOP - DGV
Tape and reel
SN74CBT16212ADGVR
CY212A
VFBGA - GQL
Tape and reel
SN74CBT16212AGQLR
CY212A
VFBGA - ZQL (Pb-free)
Tape and reel
SN74CBT16212AZQLR
CY212A
-55
C to 125
C
CFP - WD
Tube
SNJ54CBT16212AWD
SNJ54CBT16212AWD
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
S0
1A1
1A2
2A1
2A2
3A1
3A2
GND
4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
V
CC
8A1
GND
8A2
9A1
9A2
10A1
10A2
11A1
11A2
12A1
12A2
S1
S2
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
SN54CBT16212A . . . WD PACKAGE
SN74CBT16212A . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Widebus is a trademark of Texas Instruments.
SN54CBT16212A, SN74CBT16212A
24 BIT FET BUS EXCHANGE SWITCHES
SCDS007T - NOVEMBER 1992 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
terminal assignments
1
2
3
4
5
6
A
1A2
1A1
S0
S1
S2
1B1
B
3A1
2A2
2A1
1B2
2B1
2B2
C
4A1
GND
3A2
3B1
GND
3B2
D
5A2
4A2
5A1
4B2
4B1
5B1
E
6A2
6A1
5B2
6B1
F
7A1
7A2
7B1
6B2
G
VCC
GND
8A1
8B1
GND
7B2
H
8A2
9A1
9A2
9B2
9B1
8B2
J
10A1
10A2
11A1
11B1
10B2
10B1
K
11A2
12A1
12A2
12B2
12B1
11B2
FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
FUNCTION
S2
S1
S0
A1
A2
FUNCTION
L
L
L
Z
Z
Disconnect
L
L
H
B1 port
Z
A1 port = B1 port
L
H
L
B2 port
Z
A1 port = B2 port
L
H
H
Z
B1 port
A2 port = B1 port
H
L
L
Z
B2 port
A2 port = B2 port
H
L
H
Z
Z
Disconnect
H
H
L
B1 port
B2 port
A1 port = B1 port
A2 port = B2 port
H
H
H
B2 port
B1 port
A1 port = B2 port
A2 port = B1 port
GQL OR ZQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
SN54CBT16212A, SN74CBT16212A
24 BIT FET BUS EXCHANGE SWITCHES
SCDS007T - NOVEMBER 1992 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
12B2
12B1
1B2
1B1
12A2
12A1
1A2
1A1
S0
S1
S2
2
3
27
28
1
56
55
54
53
30
29
Pin numbers shown are for the DGG, DGV, DL, and WD packages.
SN54CBT16212A, SN74CBT16212A
24 BIT FET BUS EXCHANGE SWITCHES
SCDS007T - NOVEMBER 1992 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DGG package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
48
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
56
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL/ZQL package
42
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54CBT16212A
SN74CBT16212A
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
4
5.5
4
5.5
V
VIH
High-level control input voltage
2
2
V
VIL
Low-level control input voltage
0.8
0.8
V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54CBT16212A
SN74CBT16212A
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 4.5 V,
II = -18 mA
-1.2
-1.2
V
II
VCC = 0,
VI = 5.5 V
10
10
A
II
VCC = 5.5 V,
VI = 5.5 V or GND
1
1
A
ICC
VCC = 5.5 V,
IO = 0, VI = VCC or GND
3.2
3
A
ICC
Control inputs
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
2.5
2.5
mA
Ci
Control inputs
VI = 3 V or 0
2.5
2.5
pF
Cio(off)
VO = 3 V or 0,
S0, S1, and S2 = GND
7.5
7.5
pF
VCC = 4 V,
TYP at VCC = 4 V
VI = 2.4 V,
II = 15 mA
14
20
14
20
ron
VI = 0
II = 64 mA
4
10
4
7
ron
VCC = 4.5 V
VI = 0
II = 30 mA
4
10
4
7
VCC = 4.5 V
VI = 2.4 V,
II = 15 mA
6
14
6
12
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25
C.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
SN54CBT16212A, SN74CBT16212A
24 BIT FET BUS EXCHANGE SWITCHES
SCDS007T - NOVEMBER 1992 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
SN54CBT16212A
SN74CBT16212A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4 V
VCC = 5 V
0.5 V
VCC = 4 V
VCC = 5 V
0.5 V
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tpd
A or B
B or A
0.8*
0.35
0.25
ns
tpd
S
A or B
14
1.5
13
10
1.5
9.1
ns
ten
S
A or B
15
1.5
13.7
10.4
1.5
9.7
ns
tdis
S
A or B
14.2
1.5
13.5
9.2
1.5
8.8
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500
500
tPLH
tPHL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH - 0.3 V
0 V
Input
3 V
3.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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