74AC11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS499A DECEMBER 1986 REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
D
500-mA Typical Latch-Up Immunity at
125
C
D
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
description
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)
or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR
are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the
outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is
not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may
be changed without affecting the levels at the outputs.
The 74AC11074 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
INPUTS
OUTPUT
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q0
Q0
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Copyright
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
D, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
1CLK
1D
1CLR
V
CC
2CLR
2D
2CLK
74AC11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS499A DECEMBER 1986 REVISED APRIL 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
S
1
14
2
1D
13
R
12
6
7
8
9
10
3
5
1PRE
1CLK
1D
2PRE
1CLR
2CLK
2D
2CLR
1Q
1Q
2Q
2Q
C1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
A
= 55
C (in still air) (see Note 2): D package
1.25 W
. . . . . . . . . . . . . . . . . .
N package
1.1 W
. . . . . . . . . . . . . . . . . . .
PW package
0.5 W
. . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
74AC11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS499A DECEMBER 1986 REVISED APRIL 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5 V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
t/
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
I
24
A
4.5 V
3.94
3.8
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
4
40
A
Ci
VI = VCC or GND
5 V
3.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
74AC11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS499A DECEMBER 1986 REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
100
0
100
MHz
t
Pulse duration
PRE or CLR low
4
4
ns
tw
Pulse duration
CLK low or high
5
5
ns
t
Set p time before CLK
Data high or low
5
5
ns
tsu
Setup time before CLK
PRE or CLR inactive
1
1
ns
th
Hold time after CLK
0
0
ns
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
125
0
125
MHz
t
Pulse duration
PRE or CLR low
4
4
ns
tw
Pulse duration
CLK low or CLK high
4
4
ns
t
Set p time before CLK
Data high or low
3.5
3.5
ns
tsu
Setup time before CLK
PRE or CLR inactive
1
1
ns
th
Hold time after CLK
0
0
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
100
125
100
MHz
tPLH
PRE or CLR
Q or Q
1.5
5.8
9.3
1.5
10
ns
tPHL
PRE or CLR
Q or Q
1.5
6.5
11.4
1.5
12.2
ns
tPLH
CLK
Q or Q
1.5
7.7
10.5
1.5
11.3
ns
tPHL
CLK
Q or Q
1.5
7.3
9.7
1.5
10.6
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
125
150
125
MHz
tPLH
PRE or CLR
Q or Q
1.5
4.2
6.6
1.5
7.1
ns
tPHL
PRE or CLR
Q or Q
1.5
4.7
8.2
1.5
9
ns
tPLH
CLK
Q or Q
1.5
5.4
7.5
1.5
8.2
ns
tPHL
CLK
Q or Q
1.5
5
6.9
1.5
7.5
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 1 MHz
30
pF
74AC11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS499A DECEMBER 1986 REVISED APRIL 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
50% VCC
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
VCC
0 V
50%
50%
tw
VOLTAGE WAVEFORMS
Input
LOAD CIRCUIT
From Output
Under Test
CL = 50 pF
(see Note A)
500
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
50% VCC
50% VCC
50% VCC
Figure 1. Load Circuit and Voltage Waveforms
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Copyright
1998, Texas Instruments Incorporated
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