74AC11162
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS381 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
1
Internal Look-Ahead Circuitry for Fast
Counting
Carry Output for N-Bit Cascading
Fully Synchronous Operation for Counting
Synchronously Programmable
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity at 125
C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This synchronous, presettable 4-bit decade counter features an internal carry look-ahead circuitry for
application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each other when so instructed by the count-enable
inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally
associated with asynchronous (ripple-clock) counters; however, counting spikes may occur on the ripple-carry
(RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the
clock-input waveform.
These counters are fully programmable in that they may be preset to any number between 0 and 9. As presetting
is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to
agree with the setup data after the next clock pulse regardless of the levels of the enable inputs.
If one of these decade counters is preset to a number between 10 and 15 or assumes such an invalid state when
power is applied, it progresses to the normal sequence within two counts as shown in the state diagram.
The clear function for the 74AC11162 is synchronous, and a low level at the clear (CLR) input drives all four of
the flip-flop outputs low after the next low-to-high transition of the clock regardless of the levels on the
count-enable (ENP and ENT) inputs. This synchronous clear allows the count length to be modified easily by
decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding
is connected to the clear input to synchronously clear the counter to 0000 (LLLL on the Q outputs).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RCO
Q
A
Q
B
GND
GND
GND
GND
Q
C
Q
D
LOAD
CLR
CLK
A
B
V
CC
V
CC
C
D
ENP
ENT
DW OR N PACKAGE
(TOP VIEW)
EPIC is a trademark of Texas Instruments Incorporated.
74AC11162
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS381 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2
description (continued)
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable (ENP and ENT) inputs and
a ripple-carry (RCO) output. Both ENP and ENT must be high to count, and ENT is fed foward to enable RCO.
RCO thus enabled produces a high-level pulse while the count is 9 (HLLH). This high-level overflow ripple-carry
pulse can be used to enable successive cascaded stages. Transitions at the ENP or ENT inputs are allowed
regardless of the level of the clock input.
These counters feature fully independent clock circuits. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
setup and hold times.
The 74AC11162 is characterized for operation from 40
C to 85
C.
logic symbol
state diagram
CLR
CTRDIV10
5CT = 0
20
M2
G3
11
ENT
C5/2,3,4+
1, 5D
18
A
17
B
14
C
13
D
RCO
1
3CT = 9
2
3
8
9
M1
10
G4
12
ENP
19
CLK
LOAD
QA
QB
QC
QD
1
2
4
8
0
15
14
13
12
1
2
3
4
5
6
7
8
9
10
11
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
74AC11162
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS381 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
logic diagram (positive logic)
LOAD
1
10
RCO
M1
G2
1,2T/1C3
G4
3D
4R
M1
G2
1,2T/1C3
G4
3D
4R
M1
G2
1,2T/1C3
G4
3D
4R
M1
G2
1,2T/1C3
G4
3D
4R
2
QA
3
QB
8
QC
9
QD
CLR
20
CLK
19
ENP
12
ENT
11
A
18
B
17
C
14
D
13
LD
CK
CK
R
LD
For the sake of simplicity, the routing of the complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals
are shown on the logic diagram of the D/T flip-flops.
74AC11162
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS381 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
logic symbol
M1
(Load) LD
G4
3D
(Data) D
Q (Output)
G2
(Toggle Enable) TE
(Clock) CK
4R
(Inverted Reset) R
1, 2T/1C3
logic diagram, each D/T flip-flop (positive logic)
LD
Q
TE
D
CK
R
LD
LD
CK
CK
CK
CK
TG
TG
TG
TG
The origins of the signals LD and CK are shown in the logic diagram of the overall device.
74AC11162
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS381 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
output sequence
Illustrated below is the following sequence:
1.
Clear outputs to zero
2.
Preset to BCD seven
3.
Count to eight, nine (RCO high), zero, one, two, and three
4.
Inhibit
LOAD
A
Sync
Clear
Preset
Count
Inhibit
7
8
9
0
1
2
3
B
C
D
CLK
ENP
ENT
QA
QB
QC
QD
RCO
CLR
Data
Inputs
Outputs
Counting is inhibited if either or both of ENT and ENP are low.
74AC11162
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS381 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
6
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND pins
125 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
MIN
NOM
MAX
UNIT
VCC
3
5
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 4.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 4.5 V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
V
VCC = 4.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
V
VCC = 4.5 V
24
dt/dv
Input transition rise or fall rate
0
10
ns/ V
TA
Operating free-air temperature
40
85
C
NOTE 2: Unused or floating inputs must be held high or low.
74AC11162
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS381 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
7
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
I
24
A
4.5 V
3.94
3.8
IOL = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
A
Ci
VI = VCC or GND
5 V
3.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements, V
CC
= 3.3 V
0.3 V (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
66
0
66
MHz
tw
Pulse duration
CLK low or high
7.5
7.5
ns
A, B, C, D
6
6
t
Setup time before CLK
LOAD
6
6
ns
tsu
Setup time before CLK
ENT, ENP
7.5
7.5
ns
CLR low or high
7.5
7.5
th
Hold time, all synchronous inputs after CLK
1
1
ns
timing requirements, V
CC
= 5 V
0.5 V (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
110
0
110
MHz
tw
Pulse duration
CLK low or high
4.5
4.5
ns
A, B, C, D
4
4
t
Setup time before CLK
LOAD
5
5
ns
tsu
Setup time before CLK
ENT, ENP
6
6
ns
CLR low or high
4.5
4.5
th
Hold time, all synchronous inputs after CLK
1
1
ns
74AC11162
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS381 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
8
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
66
66
MHz
tPLH
CLK
RCO
1.5
10.5
14.1
1.5
15.9
ns
tPHL
CLK
RCO
1.5
12.1
15.8
1.5
18
ns
tPLH
CLK (LOAD high)
Any Q
1.5
8.7
11.7
1.5
13.2
ns
tPHL
CLK (LOAD high)
Any Q
1.5
10.2
14.4
1.5
16
ns
tPLH
CLK (LOAD lo )
Any Q
1.5
8.7
11.2
1.5
12.6
ns
tPHL
CLK (LOAD low)
Any Q
1.5
10.4
14.1
1.5
16
ns
tPLH
ENT
RCO
1.5
5.8
7.6
1.5
8.5
ns
tPHL
ENT
RCO
1.5
6.9
9.9
1.5
11
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
110
110
MHz
tPLH
CLK
RCO
1.5
7.7
9.9
1.5
11.2
ns
tPHL
CLK
RCO
1.5
8.3
11.9
1.5
12.6
ns
tPLH
CLK (LOAD high)
Any Q
1.5
6.4
8.4
1.5
9.5
ns
tPHL
CLK (LOAD high)
Any Q
1.5
7.4
10.5
1.5
11.9
ns
tPLH
CLK (LOAD lo )
Any Q
1.5
6
7.9
1.5
9
ns
tPHL
CLK (LOAD low)
Any Q
1.5
7.2
10.1
1.5
11.5
ns
tPLH
ENT
RCO
1.5
4
5.5
1.5
6
ns
tPHL
ENT
RCO
1.5
5
7.4
1.5
8.8
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF, f = 1 MHz
54
pF
74AC11162
SYNCHRONOUS 4-BIT DECADE COUNTER
SCAS381 D3199, AUGUST 1988 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
9
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500
LOAD CIRCUIT
Input
(see Note B)
In-Phase
Output
Out-of-Phase
Output
tPLH
tPHL
tPHL
tPLH
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
50% VCC
0 V
0 V
0 V
High-Level
Input
Low-Level
Input
tw
PULSE DURATION
50%
VCC
0 V
0 V
th
tsu
SETUP AND HOLD TIMES
Data
Input
Timing Input
(see Note B)
50% VCC
50% VCC
50% VCC
50%
50%
VCC
VCC
50% VCC
50% VCC
50%
50%
VCC
VCC
50%
50%
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns. For testing
fmax and pulse duration: tr = 1 to 3 ns, tf = 1 to 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright
1998, Texas Instruments Incorporated
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