74AC11191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
1
Single Down/Up Count Control Line
Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
Fully Synchronous in Count Modes
Asynchronously Presettable with Load
Control
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at
125
C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
The 74AC11191 is a synchronous, 4-bit binary reversible up/down counter. Synchronous counting operation
is provided by clocking all flip-flops simultaneously so that the outputs change coincident with each other when
instructed by the steering logic. This mode of operation eliminates the output counting spikes normally
associated with asynchronous (ripple clock) counters.
The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the enable
input (CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of
the down/up (D/U)
input. When D/U is low, the counter counts up and when D/U is high, it counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that
will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter will be dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, the outputs may be preset to any number between 0 and 15
by placing a low on the load input and entering the desired data at the data inputs. The outputs will change to
agree with the data inputs independently of the level of the clock input. This feature allows the counter to be
used as a modulo-N divider by simply modifying the count length with the preset inputs.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum
count. The latter output produces a high-level output pulse with a duration approximately equal to one complete
cycle of the clock while the count is zero (all outputs low) counting down or maximum (15) counting up. The
ripple-clock output (RCO) produces a low-level output pulse under those same conditions but only while the
clock input is low. The counter can easily be cascaded by feeding the ripple clock output to the enable input
of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
The 74AC11191 is characterized for operation from 40
C to 85
C.
DW OR N PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RCO
Q
A
Q
B
GND
GND
GND
GND
Q
C
Q
D
MAX/MIN
D/U
CLK
A
B
V
CC
V
CC
C
D
CTEN
LOAD
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
74AC11191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2
logic symbol
B
12
20
18
13
14
17
11
19
CLK
C
D
A
G1
9
8
3
2
M2 [DOWN]
M3 [UP]
1,2/1,3+
G4
C5
6,1,4
3(CT=15)Z6
2(CT=0)Z6
CTRDIV16
RCO
MAX/MIN
10
1
5D
[1]
[2]
[4]
[8]
CTEN
LOAD
D/U
QA
QB
QC
QD
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
74AC11191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
logic diagram (positive logic)
18
12
11
19
20
S
R
RCO
CLK
MAX/MIN
A
17
14
13
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
B
C
D
10
1
2
3
8
9
CTEN
D/U
LOAD
QB
QC
QD
1D
C1
QA
74AC11191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
typical load, count, and inhibit sequences
Illustrated below is the following sequence:
1.
Load (preset) to binary thirteen
2.
Count up to fourteen, fifteen (maximum), zero, one, and two
3.
Inhibit
4.
Count down to one, zero (minimum), fifteen, fourteen, and thirteen.
A
B
C
D
CLOCK
D/U
MAX/MIN
QA
QD
QC
QB
Load
Count Up
Inhibit
Count Down
13
14
15
0
1
2
2
2
1
0
15
14
13
Data
Inputs
RCO
CTEN
LOAD
74AC11191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND pins
150 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
D
t/
D
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
85
C
74AC11191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
6
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
m
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
IOH = 24 mA
4.5 V
3.94
3.8
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
{
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
m
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
{
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND, IO = 0
5.5 V
8
80
m
A
Ci
VI = VCC or GND
5 V
4
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
50
0
50
MHz
t
Pulse duration
LOAD low
4.8
4.8
ns
tw
Pulse duration
CLK high or low
10
10
ns
Data before LOAD
4
4
t
Setup time
CTEN before CLK
12.5
12.5
ns
tsu
Setup time
D/U before CLK
13.5
13.5
ns
LOAD inactive before CLK
2.5
2.5
Data after LOAD
1
1
th
Hold time
CTEN after CLK
0
0
ns
D/U after CLK
0
0
74AC11191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
7
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
100
0
100
MHz
t
Pulse duration
LOAD low
4
4
ns
tw
Pulse duration
CLK high or low
7.2
7.2
ns
Data before LOAD
3
3
t
Setup time
CTEN before CLK
8
8
ns
tsu
Setup time
D/U before CLK
8.5
8.5
ns
LOAD inactive before CLK
2
2
Data after LOAD
1.5
1.5
th
Hold time
CTEN after CLK
0.5
0.5
ns
D/U after CLK
0
0
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
50
80
50
MHz
tPLH
LOAD
Any Q
3.7
10.7
13.4
3.7
14.9
ns
tPHL
LOAD
Any Q
3.6
9.3
12.3
3.6
14.1
ns
tPLH
LOAD
MAX/MIN
5
14.2
18.7
5
21.1
ns
tPHL
LOAD
MAX/MIN
4.6
12.6
17.5
4.6
19.6
ns
tPLH
LOAD
RCO
5.2
15.4
20.2
5.2
22.9
ns
tPHL
LOAD
RCO
6
15.7
21.6
6
24.7
ns
tPLH
A B C or D
Any Q
3.4
9.8
12.3
3.4
13.8
ns
tPHL
A, B, C, or D
Any Q
3.5
8.9
12.1
3.5
13.7
ns
tPLH
A B C or D
MAX/MIN
4.7
13.5
18.2
4.7
20.7
ns
tPHL
A, B, C, or D
MAX/MIN
4
11.8
17.1
4
19.3
ns
tPLH
A B C or D
RCO
5
14.7
19.9
5
22.5
ns
tPHL
A, B, C, or D
RCO
5.3
15.1
21.1
5.3
24.3
ns
tPLH
CLK
RCO
2.8
8.7
11.5
2.8
12.9
ns
tPHL
CLK
RCO
2.8
7.8
10.6
2.8
11.9
ns
tPLH
CLK
Any Q
2.2
7.5
9.8
2.2
11.1
ns
tPHL
CLK
Any Q
2.7
7.5
11
2.7
12.7
ns
tPLH
CLK
MAX/MIN
3.7
9.9
12.2
3.7
13.8
ns
tPHL
CLK
MAX/MIN
4.1
10.2
14.4
4.1
16
ns
tPLH
D/U
RCO
4.1
11.2
14.4
4.1
15.9
ns
tPHL
D/U
RCO
4.1
10.2
14.3
4.1
16.5
ns
tPLH
D/U
MAX/MIN
2.7
8.7
11.5
2.7
12.7
ns
tPHL
D/U
MAX/MIN
3.1
8.3
11.8
3.1
13.6
ns
tPLH
CTEN
RCO
2.5
7.2
9
2.5
10.3
ns
tPHL
CTEN
RCO
2.6
6.6
8.8
2.6
10
ns
74AC11191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
8
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
100
135
100
MHz
tPLH
LOAD
Any Q
3.1
6.7
9.4
3.1
10.6
ns
tPHL
LOAD
Any Q
3
6.4
9
3
10.2
ns
tPLH
LOAD
MAX/MIN
4.3
8.8
12.5
4.3
14.3
ns
tPHL
LOAD
MAX/MIN
4
8.4
12
4
13.7
ns
tPLH
LOAD
RCO
4.5
9.7
13.7
4.5
15.4
ns
tPHL
LOAD
RCO
5
10.1
14.4
5
16.3
ns
tPLH
A B C or D
Any Q
2.9
6.2
8.7
2.9
9.8
ns
tPHL
A, B, C, or D
Any Q
3
6.1
8.7
3
9.8
ns
tPLH
A B C or D
MAX/MIN
4.1
8.4
12.2
4.1
13.7
ns
tPHL
A, B, C, or D
MAX/MIN
3.5
8
11.8
3.5
13.4
ns
tPLH
A B C or D
RCO
4.3
9.2
13.5
4.3
15.1
ns
tPHL
A, B, C, or D
RCO
4.7
9.7
14
4.7
16
ns
tPLH
CLK
RCO
2.4
5.9
8.4
2.4
9.1
ns
tPHL
CLK
RCO
2.9
5.6
7.7
2.9
8.7
ns
tPLH
CLK
Any Q
1.9
5.2
7.6
1.9
8.4
ns
tPHL
CLK
Any Q
2.4
5.4
8
2.4
9.4
ns
tPLH
CLK
MAX/MIN
3
6.5
8.8
3
10.4
ns
tPHL
CLK
MAX/MIN
3.6
7.1
10.4
3.6
10.8
ns
tPLH
D/U
RCO
3.5
7.2
10.2
3.5
11.3
ns
tPHL
D/U
RCO
3.5
6.9
10
3.5
11.5
ns
tPLH
D/U
MAX/MIN
2.3
5.7
8.1
2.3
9.1
ns
tPHL
D/U
MAX/MIN
2.7
5.9
8.6
2.7
9.7
ns
tPLH
CTEN
RCO
2.1
4.9
6.8
2.1
7.7
ns
tPHL
CTEN
RCO
2.2
4.8
6.7
2.2
7.7
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd Power dissipation capacitance
CL = 50 pF, f = 1 MHz
66
pF
74AC11191
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
SCAS105A FEBRUARY 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
9
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500
LOAD CIRCUIT
Input
(see Note B)
In-Phase
Output
Out-of-Phase
Output
tPLH
tPHL
tPHL
tPLH
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
50% VCC
0 V
0 V
0 V
High-Level
Input
Low-Level
Input
tw
PULSE DURATION
50%
VCC
0 V
0 V
th
tsu
SETUP AND HOLD TIMES
Data
Input
Timing Input
(see Note B)
50% VCC
50% VCC
50% VCC
50%
50%
VCC
VCC
50%
50%
50%
50%
VCC
VCC
50%
50%
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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In order to minimize risks associated with the customer's applications, adequate design and operating
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Copyright
1998, Texas Instruments Incorporated
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