74AC11478
OCTAL DUAL-RANK D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS182 APRIL 1989 REVISED APRIL 1993
Copyright
1993, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Specifically Designed for Data
Synchronization Applications
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin V
CC
and GND Pin
Configurations Minimize High-Speed
Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS ) 1-
m Process
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
The 74AC11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization
applications in which the normal setup and hold time specifications are frequently violated.
Synchronization of two digital signals operating at different frequencies is a common system problem. This
problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution,
however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the
setup or hold time of a flip-flop is violated, the output response is uncertain. A flip-flop is metastable if its output
hangs up in the region between V
IL
and V
IH
. The metastable condition lasts until the flip-flop recovers into one
of its two stable states. With conventional flip-flops, this recovery time can be longer than the specified maximum
propagation delay.
The problem of metastability is typically solved by adding an additional layer of synchronization. This dual-rank
approach is employed in the 74AC11478. The probability of the second stage entering the metastable state is
exponentially reduced by this dual-rank architecture. The 74AC11478 provides a one-chip solution for system
designers in asynchronous applications.
The 74AC11478 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
INPUTS
OUTPUT
OE
CLK
D
Q
H
L
L
L
X
L
X
L
H
X
Z
L
H
Q0
Data presented at the D inputs
requires two clock cycles to appear at
the Q outputs.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
OE
1D
2D
3D
4D
V
CC
V
CC
5D
6D
7D
8D
CLK
DW OR NT PACKAGE
(TOP VIEW)
74AC11478
OCTAL DUAL-RANK D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS182 APRIL 1989 REVISED APRIL 1993
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
logic diagram (positive logic)
OE
To 7 Other Channels
1Q
1
1D
CLK
OE
23
13
24
C1
1D
1D
C1
1D
23
1D
22
2D
21
3D
20
4D
EN
24
13
CLK
C1
1Q
1
2Q
2
3Q
3
4Q
4
17
5D
16
6D
15
7D
14
8D
5Q
9
6Q
10
7Q
11
8Q
12
1D
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND pins
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
74AC11478
OCTAL DUAL-RANK D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS182 APRIL 1989 REVISED APRIL 1993
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 2)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5 V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
t/
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
85
C
NOTE 2: Unused or floating inputs must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
I
24
A
4.5 V
3.94
3.8
IOL = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
A
IOZ
VO = VCC or GND
5.5 V
0.5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
A
Ci
VI = VCC or GND
5 V
4.5
pF
Co
VO = VCC or GND
5 V
10
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
74AC11478
OCTAL DUAL-RANK D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS182 APRIL 1989 REVISED APRIL 1993
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
55
55
MHz
tsu
Setup time, data before CLK
3
3
ns
th
Hold time, data after CLK
1.5
1.5
ns
tw
Pulse duration, CLK high or low
9
9
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
83
83
MHz
tsu
Setup time, data before CLK
2.5
2.5
ns
th
Hold time, data after CLK
1.5
1.5
ns
tw
Pulse duration, CLK high or low
6
6
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
55
55
MHz
tPLH
CLK
Q
3.8
10.5
13.3
3.8
15
ns
tPHL
CLK
Q
5.5
13.2
16.8
5.5
18.4
ns
tPZH
OE
Q
3.7
10.8
13.9
3.7
16
ns
tPZL
OE
Q
5.4
14.7
19.2
5.4
22.5
ns
tPHZ
OE
Q
3.9
7.1
9.3
3.9
10.1
ns
tPLZ
OE
Q
4
6.9
8.9
4
9.6
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
83
83
MHz
tPLH
CLK
Q
2.9
6.1
8.9
2.9
10
ns
tPHL
CLK
Q
4.3
7.9
11.2
4.3
12.3
ns
tPZH
OE
Q
2.9
6.4
9.6
2.9
10.8
ns
tPZL
OE
Q
4.1
8.1
12.3
4.1
14.0
ns
tPHZ
OE
Q
3.2
5.7
8
3.2
8.6
ns
tPLZ
OE
Q
3.5
5.4
7.4
3.5
8
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per flip flop
Outputs enabled
CL = 50 pF
f = 1 MHz
46
pF
Cpd
Power dissipation capacitance per flip-flop
Outputs disabled
CL = 50 pF,
f = 1 MHz
33
pF
74AC11478
OCTAL DUAL-RANK D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS182 APRIL 1989 REVISED APRIL 1993
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
LOAD CIRCUIT FOR OUTPUTS
S1
2
VCC
Open
GND
500
500
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
VCC
GND
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
50%
50%
VCC
0 V
50% VCC
0 V
VCC
Data Input
Timing Input
50%
VCC
0 V
50%
50%
0 V
VCC
0 V
50%
50%
tw
Input
(see Note A)
50% VCC
20% VCC
80% VCC
tPLH
tPHL
50%
50%
0 V
50% VCC
50% VCC
VOH
VOL
Input
(see Note B)
Output
(see Note D)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC
VCC
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
3 ns, tf
3 ns.
For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright
1998, Texas Instruments Incorporated
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