74AC11874
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS236 MARCH 1990 REVISED APRIL 1993
Copyright
1993, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3-State Buffer-Type Outputs Drive Bus
Lines Directly
Asynchronous Clear
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity at
125
C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This dual 4-bit D-type edge-triggered flip-flop features 3-state outputs designed specifically for bus driving. This
makes these devices particularly suitable for implementing buffer registers, I/O ports, and working registers.
The flip-flops enter data on the low-to-high transition of the clock. The 74AC11874 has clear (1CLR and 2CLR)
inputs and noninverting outputs. Taking CLR low causes the four Q outputs to go low independently of the clock.
The 74AC11874 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each 4-bit flip-flop)
INPUTS
OUTPUT
OE
CLR
CLK
D
Q
L
L
X
X
L
L
H
H
H
L
H
L
L
L
H
L
X
Q0
H
X
X
X
Z
DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1CLK
1Q1
1Q2
1Q3
1Q4
GND
GND
GND
GND
2Q1
2Q2
2Q3
2Q4
2CLK
1OE
1CLR
1D1
1D2
1D3
1D4
V
CC
V
CC
2D1
2D2
2D3
2D4
2CLR
2OE
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
74AC11874
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS236 MARCH 1990 REVISED APRIL 1993
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
logic diagram, each quad flip-flop (positive logic)
EN
28
1
1CLK
1D
26
1D1
25
1D2
24
1D3
23
1D4
1Q1
2
1Q2
3
1Q3
4
1Q4
5
R
27
1OE
1CLR
EN
15
14
2CLK
1D
20
2D1
19
2D2
18
2D3
17
2D4
2Q1
10
2Q2
11
2Q3
12
2Q4
13
R
16
2OE
2CLR
R
1D
OE
CLK
CLR
D1
Q1
R
1D
Q2
R
1D
Q3
R
1D
Q4
D2
D3
D4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
C1
C1
1
1
C1
C1
C1
C1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND pins
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
74AC11874
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS236 MARCH 1990 REVISED APRIL 1993
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
V
VCC = 3 V
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 5.5 V
3.85
VCC = 3 V
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
V
VCC = 5.5 V
1.65
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 3 V
4
IOH
High-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
VCC = 3 V
12
IOL
Low-level output current
VCC = 4.5 V
24
mA
VCC = 5.5 V
24
t/
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
5.5 V
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
V
I
24
A
4.5 V
3.94
3.8
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
3 V
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
5.5 V
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
A
IOZ
VO = VCC or GND
5.5 V
0.5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
A
Ci
VI = VCC or GND
5 V
4.5
pF
Co
VO = VCC or GND
5 V
13.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
74AC11874
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS236 MARCH 1990 REVISED APRIL 1993
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
60
0
60
MHz
t
Pulse duration
CLR low
4
4
ns
tw
Pulse duration
CLK high or low
8.3
8.3
ns
t
Setup time before CLK
Data
3
3
ns
tsu
Setup time before CLK
CLR inactive
1.5
1.5
ns
th
Hold time after CLK
Data
1
1
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
125
0
125
MHz
t
Pulse duration
CLR low
4
4
ns
tw
Pulse duration
CLK high or low
4
4
ns
t
Setup time before CLK
Data
2
2
ns
tsu
Setup time before CLK
CLR inactive
1.5
1.5
ns
th
Hold time after CLK
Data
1
1
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
60
60
MHz
tPLH
CLK
Q
2.9
7.3
11
2.9
12.5
ns
tPHL
CLK
Q
3.7
8.8
13.1
3.7
14.6
ns
tPHL
CLR
Q
3.9
9.3
14
3.9
15.7
ns
tPZH
OE
Q
2.1
5.6
8.7
2.1
9.8
ns
tPZL
OE
Q
3.1
8.4
13.1
3.1
14.9
ns
tPHZ
OE
Q
4
6.2
8.2
4
8.7
ns
tPLZ
OE
Q
3.9
6.3
8.5
3.9
9
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
125
125
MHz
tPLH
CLK
Q
2.3
5.2
7.4
2.3
8.3
ns
tPHL
CLK
Q
2.9
6.1
8.6
2.9
9.6
ns
tPHL
CLR
Q
2.9
6.3
8.9
2.9
10
ns
tPZH
OE
Q
1.5
4
5.9
1.5
6.6
ns
tPZL
OE
Q
2.3
5.4
7.8
2.3
8.8
ns
tPHZ
OE
Q
3.8
5.7
7.3
3.8
7.7
ns
tPLZ
OE
Q
3.7
5.5
7.1
3.7
7.5
ns
74AC11874
DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS236 MARCH 1990 REVISED APRIL 1993
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per flip flop
Outputs enabled
CL = 50 pF
f = 1 MHz
31
pF
Cpd
Power dissipation capacitance per flip-flop
Outputs disabled
CL = 50 pF,
f = 1 MHz
13
pF
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
LOAD CIRCUIT FOR OUTPUTS
S1
2
VCC
Open
GND
500
500
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
VCC
GND
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
50%
50%
VCC
0 V
50% VCC
0 V
VCC
Data Input
Timing Input
50%
VCC
0 V
50%
50%
0 V
VCC
0 V
50%
50%
tw
Input
(see Note A)
50% VCC
20% VCC
80% VCC
tPLH
tPHL
50%
50%
0 V
50% VCC
50% VCC
VOH
VOL
Input
(see Note B)
Output
(see Note D)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC
VCC
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
3 ns, tf
3 ns.
For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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1998, Texas Instruments Incorporated
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