54AC16823, 74AC16823
18-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS243A APRIL 1991 REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
TM
Family
D
Provides Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
D
500-mA Typical Latch-Up Immunity
at 125
C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center Pin
Spacings
description
These 18-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, parity bus interfacing, and
working registers.
The 'AC16823 can be used as two 9-bit flip-flops
or one 18-bit flip-flop. With the clock-enable
(CLKEN) input low, the D-type flip-flops enter data
on the low-to-high transitions of the clock. Taking
CLKEN high disables the clock buffer, thus
latching the outputs. Taking the clear (CLR) input
low causes the Q outputs to go low independently
of the clock.
The output enable (OE) input can be used to place the outputs in either a normal logic state (high or low) or a
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74AC16823 is packaged in TI's shrink small-outline package (DL), which provides twice the I/O pin count
and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16374 is characterized for operation over the full military temperature range of 55
C to 125
C. The
74AC16823 is characterized for operation from 40
C to 85
C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CLR
1OE
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
1CLK
1CLKEN
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2CLKEN
2CLK
54AC16823 . . . WD PACKAGE
74AC16823 . . . DL PACKAGE
(TOP VIEW)
Copyright
1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
54AC16823, 74AC16823
18-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS243A APRIL 1991 REVISED APRIL 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each 9-bit stage)
INPUTS
OUTPUT
OE
CLR
CLKEN
CLK
D
Q
L
L
X
X
X
L
L
H
L
H
H
L
H
L
L
L
L
H
L
L
X
Q0
L
H
H
X
X
Q0
H
X
X
X
X
Z
logic symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
EN1
2
56
1CLK
3C4
4D
54
1D1
1Q1
3
52
1D2
1Q2
5
51
1D3
1Q3
6
49
1D4
1Q4
8
48
1D5
1Q5
9
47
1D6
1Q6
10
45
1D7
1Q7
12
44
1D8
1Q8
13
43
1D9
1Q9
14
1, 2
8D
42
2D1
2Q1
15
41
2D2
2Q2
16
40
2D3
2Q3
17
38
2D4
2Q4
19
37
2D5
2Q5
20
36
2D6
2Q6
21
34
2D7
2Q7
23
33
2D8
2Q8
24
31
2D9
2Q9
25
5, 6
R2
1
G3
55
EN5
27
29
2CLK
7C8
R6
28
G7
30
1OE
1CLR
2OE
2CLR
logic diagram (positive logic)
One of Nine
Channels
2Q1
1Q1
15
3
2D1
2CLK
2CLKEN
2CLR
2OE
1D1
1CLK
1CLKEN
1CLR
1OE
42
29
30
28
27
54
56
55
1
2
R
CE
C1
1D
To Eight Other Channels
1D
C1
CE
R
One of Nine
Channels
To Eight Other Channels
54AC16823, 74AC16823
18-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS243A APRIL 1991 REVISED APRIL 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
450 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power package dissipation at T
A
= 55
C (in still air)(see Note 2): DL package
1.4 W
. . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54AC16823
74AC16823
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
5
5.5
3
5
5.5
V
VCC = 3 V
2.1
2.1
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VCC = 5.5 V
3.85
3.85
VCC = 3 V
0.9
0.9
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
VCC = 5.5 V
1.65
1.65
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 3 V
4
4
IOH
High-level output current
VCC = 4.5 V
24
24
mA
VCC = 5.5 V
24
24
VCC = 3 V
12
12
IOL
Low-level output current
VCC = 4.5 V
24
24
mA
VCC = 5.5 V
24
24
t/
v
Input transition rise or fall rate
0
10
0
10
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54AC16823, 74AC16823
18-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS243A APRIL 1991 REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
54AC16823
74AC16823
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
3 V
2.9
2.9
2.9
IOH = 50
A
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
VOH
IOH = 4 mA
3 V
2.58
2.48
2.48
V
I
24
A
4.5 V
3.94
3.8
3.8
IOL = 24 mA
5.5 V
4.94
4.8
4.8
IOH = 75 mA
5.5 V
3.85
3.85
3 V
0.1
0.1
0.1
IOL = 50
A
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
VOL
IOL = 12 mA
3 V
0.36
0.44
0.44
V
IOL = 24 mA
4.5 V
0.36
0.44
0.44
IOL = 24 mA
5.5 V
0.36
0.44
0.44
IOL = 75 mA
5.5 V
1.65
1.65
II
VI = VCC or GND
5.5 V
0.1
1
1
A
IOZ
VO = VCC or GND
5.5 V
0.5
5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
80
A
Ci
VI = VCC or GND
5 V
3
pF
Co
VO = VCC or GND
5 V
11
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements over recommended operating free-air temperature range,
V
CC
= 3 V
0.3 V (unless otherwise noted) (see Figure 1)
TA = 25
C
54AC16823
74AC16823
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
60
0
60
0
60
MHz
t
Pulse duration
CLR low
3.3
3.3
3.3
ns
tw
Pulse duration
CLK high or low
8.4
8.4
8.4
ns
CLR inactive
0.5
0.5
0.5
tsu
Setup time before CLK
Data
7.2
7.2
7.2
ns
CLKEN low
5.8
5.8
5.8
th
Hold time after CLK
Data
0
0
0
ns
th
Hold time after CLK
CLKEN high or low
1
1
1
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54AC16823, 74AC16823
18-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS243A APRIL 1991 REVISED APRIL 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
TA = 25
C
54AC16823
74AC16823
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
115
0
115
0
115
MHz
t
Pulse duration
CLR low
3.3
3.3
3.3
ns
tw
Pulse duration
CLK high or low
4.4
4.4
4.4
ns
CLR inactive
0.6
0.6
0.6
tsu
Setup time before CLK
Data
5
5
5
ns
CLKEN low
4.2
4.2
4.2
th
Hold time after CLK
Data
1.3
1.3
1.3
ns
th
Hold time after CLK
CLKEN high or low
1.4
1.4
1.4
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54AC16823
74AC16823
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
60
60
60
MHz
tPLH
CLK
Q
3.9
13.8
16.8
3.9
18.8
3.9
18.8
ns
tPHL
CLK
Q
4.7
14.5
17.3
4.7
18.9
4.7
18.9
ns
tPHL
CLR
Q
4
12.4
14.9
4
16.2
4
16.2
ns
tPZH
OE
Q
3
11.1
14
3
15.4
3
15.4
ns
tPZL
OE
Q
4.3
15
18.7
4.3
20.8
4.3
20.8
ns
tPHZ
OE
Q
4.5
8.5
10.4
4.5
11.2
4.5
11.2
ns
tPLZ
OE
Q
3.9
7.7
9.3
3.9
10.3
3.9
10.3
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54AC16823
74AC16823
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
115
115
115
MHz
tPLH
CLK
Q
3.1
7.8
10.6
3.1
12
3.1
12
ns
tPHL
CLK
Q
3.9
8.6
11.4
3.9
12.7
3.9
12.7
ns
tPHL
CLR
Q
3.2
7.4
9.9
3.2
11
3.2
11
ns
tPZH
OE
Q
2.2
6.1
8.6
2.2
9.7
2.2
9.7
ns
tPZL
OE
Q
3
7.4
10.6
3
11.8
3
11.8
ns
tPHZ
OE
Q
4.2
6.8
8.7
4.2
9.3
4.2
9.3
ns
tPLZ
OE
Q
3.7
6.2
7.8
3.7
8.6
3.7
8.6
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per flip flop
Outputs enabled
CL = 50 pF
f = 1 MHz
36
pF
Cpd
Power dissipation capacitance per flip-flop
Outputs disabled
CL = 50 pF, f = 1 MHz
18
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54AC16823, 74AC16823
18-BIT BUS INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS243A APRIL 1991 REVISED APRIL 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
50%
50%
50%
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
50%
50%
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
50%
50%
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
VCC
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
VCC
0 V
50%
50%
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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Copyright
1998, Texas Instruments Incorporated
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