74ACT11174
HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS145 D3435, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Inputs Are TTL-Voltage Compatible
Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
Fully-Buffered Outputs for Maximum
Isolation From External Disturbances
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at 125
C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This device contains six D-type flip-flops and is positive-edge-triggered with a direct clear input. Information at
the D inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the
clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time
of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect
at the output.
The 74ACT11174 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
CLR
CLK
D
Q
L
X
X
L
H
H
H
H
L
L
H
L
X
Q0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1Q
2Q
3Q
GND
GND
GND
GND
4Q
5Q
6Q
CLR
1D
2D
3D
V
CC
V
CC
4D
5D
6D
CLK
DW OR N PACKAGE
(TOP VIEW)
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
74ACT11174
HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS145 D3435, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
logic symbol
logic diagram (positive logic)
6D
5D
6Q
5Q
1D
17
2
18
19
14
9
13
12
3
8
11
1
20
10
R
C1
4Q
3Q
2Q
1Q
4D
3D
2D
1D
CLK
CLR
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
CLR
CLK
1D
2D
3D
4D
5D
6D
1Q
2Q
3Q
4Q
5Q
6Q
1
2
3
8
9
10
20
11
19
18
17
14
13
12
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
150 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74ACT11174
HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS145 D3435, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
24
mA
IOL
Low-level output current
24
mA
D
t /
D
v
Input transition rise or fall rate
0
10
ns / V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
V
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
{
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
V
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
{
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
m
A
D
ICC
One input at 3 4 V
Other inputs at GND or VCC
5 5 V
0 9
1
mA
D
ICC
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
110
0
110
MHz
t
Pulse duration
CLR low
4
4
ns
tw
Pulse duration
CLK high or low
4.5
4.5
ns
t
Setup time before CLK
Data
4
4
ns
tsu
Setup time before CLK
CLR inactive
1
1
ns
th
Hold time after CLK
0.5
0.5
ns
74ACT11174
HEX D-TYPE FLIP-FLOP WITH CLEAR
SCAS145 D3435, MARCH 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
110
135
110
MHz
tPHL
CLR
Any Q
3.4
7.5
11.4
3.4
12.6
ns
tPLH
CLK
Any Q
3.1
5.8
7.9
3.1
8.7
ns
tPHL
CLK
Any Q
3.7
7.2
9.9
3.7
11
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd Power dissipation capacitance
Outputs enabled
CL = 50 pF, f = 1 MHz
30
pF
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
3 V
0 V
1.5 V
1.5 V
tw
VOLTAGE WAVEFORMS
Input
LOAD CIRCUIT
From Output
Under Test
CL = 50 pF
(see Note A)
500
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright
1998, Texas Instruments Incorporated
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