74ACT11194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS094 NOVEMBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Inputs Are TTL-Voltage Compatible
Parallel-to-Serial, Serial-to-Parallel
Conversions
Left or Right Shifts
Parallel Synchronous Loading
Direct Overriding Clear
Temporary Data Latching Capability
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity
at 125
C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This bidirectional shift register features parallel outputs, right-shift and left-shift serial inputs,
operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of
operation, namely:
Parallel (broadside) load
Shift right (in the direction Q
A
toward Q
D
)
Shift left (in the direction Q
D
toward Q
A
)
Inhibit clocking (do nothing).
Synchronous parallel loading is accomplished by applying the 4 bits of data and taking both mode control inputs,
S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive
transition of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low.
Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left
synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when
both mode control inputs are low.
The 74ACT11194 is characterized for operation from 40
C to 85
C.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SR SER
Q
A
Q
B
GND
GND
GND
GND
Q
C
Q
D
SL SER
S0
S1
A
B
V
CC
V
CC
C
D
CLR
CLK
DW OR N PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
74ACT11194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS094 NOVEMBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
MODE
CLK
SERIAL
PARALLEL
QA
QB
QC
QD
CLR
S1
S0
CLK
LEFT
RIGHT
A
B
C
D
QA
QB
QC
QD
L
X
X
X
X
X
X
X
X
X
L
L
L
L
H
X
X
L
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H
H
H
X
X
a
b
c
d
a
b
c
d
H
L
H
X
H
X
X
X
X
H
QAn
QBn
QCn
H
L
H
X
L
X
X
X
X
L
QAn
QBn
QCn
H
H
L
H
X
X
X
X
X
QBn
QCn
QDn
H
H
H
L
L
X
X
X
X
X
QBn
QCn
QDn
L
H
L
L
X
X
X
X
X
X
X
QA0
QB0
QC0
QD0
H = high level (steady state)
L = low level (steady state)
X = irrelevant (any input, including transitions)
= transition from low to high level
a,b,c,d = the level of steady-state input at inputs A, B, C, or D, respectively.
QA0, QB0, QC0, QD0 = the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were
established.
QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD respectively, before the most-recent
transition of the clock.
timing clear, load, right-shift, inhibit, and clear sequences
CLK
S0
QC
CLR
QB
QA
Load
Shift Right
Mode
Control
Inputs
S1
QD
R
Serial
Data
Inputs
L
A
Parallel
Data
Inputs
B
H
L
C
D
H
L
Outputs
Clear
Shift Left
Inhibit
Clear
74ACT11194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS094 NOVEMBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
logic symbol
CLR
SRG4
R
12
1
C4
20
S0
1
3, 4D
17
B
3, 4D
14
C
2
3
8
0
19
S1
11
CLK
QA
QB
QC
/2
M
0
3
1, 4D
1
SR SER
3, 4D
18
A
9
QD
3, 4D
13
D
2, 4D
10
SL SER
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1S
C1
1R
R
S0
Mode
Control
Inputs
S1
19
20
A
B
C
D
18
17
14
13
1
SR SER
10
SL SER
Parallel Inputs
1S
C1
1R
R
1S
C1
1R
R
1S
C1
1R
R
CLK
CLR
QA
2
QB
3
QC
8
QD
9
Parallel Outputs
74ACT11194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS094 NOVEMBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
24
mA
IOL
Low-level output current
24
mA
D
t /
D
v
Input transition rise or fall rate
0
10
ns/ V
TA
Operating free-air temperature
40
85
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
V
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
}
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
V
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
}
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
m
A
D
ICC
w
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC.
74ACT11194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS094 NOVEMBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
100
0
100
MHz
t
Pulse duration
CLK high or low
5
5
ns
tw
Pulse duration
CLR low
4.5
4.5
ns
Select
6
6
tsu
Setup time before CLK
Data
4
4
ns
CLR inactive
1
1
th
Hold time after CLK
Select
1.5
1.5
ns
th
Hold time after CLK
Data
1
1
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
100
130
100
MHz
tPLH
CLK
Any Q
2.2
5.8
6.9
2.2
7.7
ns
tPHL
CLK
Any Q
2.6
6.6
7.7
2.6
8.8
ns
tPLH
CLR
Any Q
2.9
7.1
9.1
2.9
10.3
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd Power dissipation capacitance
CL = 50 pF, f = 1 MHz
69
pF
74ACT11194
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
SCAS094 NOVEMBER 1989 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
26
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
3 V
0 V
1.5 V
1.5 V
tw
VOLTAGE WAVEFORMS
Input
LOAD CIRCUIT
From Output
Under Test
CL = 50 pF
(see Note A)
500
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright
1998, Texas Instruments Incorporated
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