74ACT11379
QUAD D-TYPE FLIP-FLOP
WITH CLOCK ENABLE
SCAS103 JANUARY 1990 REVISED APRIL 1993
Copyright
1993, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Inputs Are TTL-Voltage Compatible
Contains Four Flip-Flops with Double-Rail
Outputs
Clock Enable Latched to Avoid False
Clocking
Applications Include: Buffer/Storage
Registers, Shift Registers, Pattern
Generators
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity
at 125
C
Package Options Include Plastic Small
Outline Packages, and Standard Plastic
300-mil DIPs
description
These circuits are positive-edge-triggered D-type flip-flops with a clock-enable input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and
is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high
or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking
by transitions at the CLKEN input.
The 74ACT11379 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLKEN
CLK
D
Q
Q
H
X
X
Q0
Q0
L
H
H
L
L
L
L
H
X
L
X
Q0
Q0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1Q
2Q
2Q
GND
GND
GND
GND
3Q
3Q
4Q
1Q
CLKEN
1D
2D
V
CC
V
CC
3D
4D
CLK
4Q
DW OR N PACKAGE
(TOP VIEW)
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
74ACT11379
QUAD D-TYPE FLIP-FLOP
WITH CLOCK ENABLE
SCAS103 JANUARY 1990 REVISED APRIL 1993
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
logic diagram (positive logic)
2D
IC2
G1
4D
3D
2D
1D
CLK
CLKEN
13
14
17
18
12
19
4Q
4Q
3Q
3Q
2Q
2Q
1Q
1Q
11
10
9
8
3
2
1
20
1D
C1
1D
C1
1D
C1
1D
C1
4Q
4Q
3Q
3Q
2Q
2Q
1Q
1Q
4D
3D
2D
1D
CLK
CLKN
13
14
17
18
12
19
11
10
9
8
3
2
1
20
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
}
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
24
mA
IOL
Low-level output current
24
mA
D
t/
D
v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
40
85
C
74ACT11379
QUAD D-TYPE FLIP-FLOP
WITH CLOCK ENABLE
SCAS103 JANUARY 1990 REVISED APRIL 1993
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
V
OH
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
{
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
V
OL
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
{
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND, IO = 0
5.5 V
8
80
m
A
D
I
One input at 3.4 V,
5 5 V
0 9
1
mA
D
ICC
,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
100
0
100
MHz
t
Pulse duration
CLK high
5
5
ns
tw
Pulse duration
CLK low
5
5
ns
Data
5
5
tsu
Setup time, before CLK
CLKEN high
3.5
3.5
ns
CLKEN low
3.5
3.5
th
Hold time, after CLK
CLKEN inactive or active, data
0
0
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
100
125
100
MHz
tPLH
CLK
Any Q or Q
2.2
5
6.6
2.2
7.4
ns
tPHL
CLK
Any Q or Q
3.1
7.2
9.8
3.1
11.2
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF, f = 1 MHz
38
pF
74ACT11379
QUAD D-TYPE FLIP-FLOP
WITH CLOCK ENABLE
SCAS103 JANUARY 1990 REVISED APRIL 1993
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
500
CL = 50 pF
(see Note A)
LOAD CIRCUIT
0
0
3 V
3 V
1.5 V
1.5 V
1.5 V
1.5 V
Input
In-Phase
Output
Out-of-Phase
Output
(see Note C)
tPLH
tPHL
tPHL
tPLH
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
tw
High-Level
Input
Low-Level
Input
VOLTAGE WAVEFORMS
PULSE DURATIONS
tsu
1.5 V
th
Timing
Input
(see Note B)
Data
Input
SETUP AND HOLD TIMES
1.5 V
0
0
3 V
3 V
1.5 V
1.5 V
1.5 V
50%
50%
50%
50%
0
3 V
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Zo = 50
, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright
1998, Texas Instruments Incorporated
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