74ACT11478
METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP
WITH 3STATE OUTPUTS
SCAS131 APRIL 1990 REVISED APRIL 1993
Copyright
1993, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Inputs Are TTL-Voltage Compatible
Specifically Designed for Data
Synchronization Applications
Improved Metastable Characteristics
Provide Greater System Reliability
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity
at 125
C
Package Options Include Plastic Small
Outline Packages and Standard Plastic
300-mil DIPs
description
The 74ACT11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization
applications where the normal setup and hold time specifications are frequently violated.
Synchronization of two digital signals operating at different frequencies is a common system problem. This
problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution,
however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the
setup or hold time specification is violated, the output response is uncertain.
A flip-flop is metastable if its output hangs up in the region between V
IL
and V
IH
. The metastable condition lasts
until the flip-flop recovers into one of its two stable states. With conventional flip-flops, this recovery time can
be longer than the specified maximum propagation delay.
The problem of metastability is typically solved by adding an additional layer of synchronization. This type of
dual ranking is employed in the 74ACT11478. The probability of the second stage entering the metastable state
is exponentially reduced by this dual-rank architecture. The 74ACT11478 provides a one-chip solution for
system designers in asynchronous applications.
The 74ACT11478 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE
CLOCK
D
Q
H
X
X
Z
L
L
L
L
H
H
L
H
X
QO
Data presented at the D input requires two
clock cycles to appear at the Q output.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
OE
1D
2D
3D
4D
V
CC
V
CC
5D
6D
7D
8D
CLK
DW OR NT PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
74ACT11478
METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP
WITH 3STATE OUTPUTS
SCAS131 APRIL 1990 REVISED APRIL 1993
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
logic diagram (positive logic)
CLK
OE
1D
C1
1D
24
13
23
8D
7D
6D
5D
4D
3D
2D
1D
CLK
OE
14
15
16
17
20
21
22
23
13
24
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
12
11
10
9
4
3
2
1
1D
C1
EN
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
1D
1D
C1
1
1Q
To Seven Other Flip-Flops
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
MIN
MAX
UNIT
VCC
Supply voltage
4.5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
24
mA
IOL
Low-level output current
24
mA
D
t/
D
v
Input transition rise or fall rate
0
10
ns /V
TA
Operating free-air temperature
40
85
C
74ACT11478
METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP
WITH 3STATE OUTPUTS
SCAS131 APRIL 1990 REVISED APRIL 1993
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
m
A
4.5 V
4.4
4.4
IOH = 50
m
A
5.5 V
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
V
OH
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
{
5.5 V
3.85
IOL = 50
m
A
4.5 V
0.1
0.1
IOL = 50
m
A
5.5 V
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
V
OL
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
{
5.5 V
1.65
IOZ
VO = VCC or GND
5.5 V
0.5
5
m
A
II
VI = VCC or GND
5.5 V
0.1
1
m
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
m
A
D
ICC
One input at 3.4 V,
5 5 V
0 9
1
mA
D
ICC
,
Other inputs at GND or VCC
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4.5
pF
Co
VO = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
f
clock
Clock frequency
0
75
0
75
MHz
t
Pulse duration
CLK high
4
4
ns
tw
Pulse duration
CLK low
5
5
ns
tsu
Setup time, data before CLK
2.7
2.7
ns
th
Hold time, data after CLK
1.5
1.5
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
7.5
75
MHz
tPLH
CLK
Q
4.3
7.4
10.1
4.3
11.6
ns
tPHL
CLK
Q
5.6
9.4
12.6
5.6
14.2
ns
tPZH
OE
Q
3.7
7.5
11.1
3.7
12.6
ns
tPZL
OE
Q
4.7
9.2
13.7
4.7
15.8
ns
tPHZ
OE
Q
4.4
7.2
9.2
4.4
9.8
ns
tPLZ
OE
Q
4.7
6.6
8.7
4.7
9.3
ns
74ACT11478
METASTABLE-RESISTAND OCTAL D-TYPE DUAL-RANK FLIP-FLOP
WITH 3STATE OUTPUTS
SCAS131 APRIL 1990 REVISED APRIL 1993
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per flip flop
Outputs enabled
CL = 50 pF
f = 1 MHz
76
pF
Cpd
Power dissipation capacitance per flip-flop
Outputs disabled
CL = 50 pF, f = 1 MHz
64
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 X VCC
Open
GND
500
500
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 x VCC
GND
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data
Input
3 V
0
3 V
0
1.5 V
1.5 V
1.5 V
1.5 V
tw
High-Level
Input
Low-Level
Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0
50%
50%
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
S1 at 2 x VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
0
50%
20%
50%
80%
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
3 V
Timing Input
(see Note B)
50%
50%
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
0 V
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright
1998, Texas Instruments Incorporated
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