74ACT11825
8-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS154A D3715, NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1993, Texas Instruments Incorporated
21
Inputs Are TTL-Voltage Compatible
Multiple Output Enables Allow Multiuser
Control of the Interface
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
500-mA Typical Latch-Up Immunity at 125
C
description
This device contains eight flip-flops that feature
3-state outputs designed specifically for driving
highly-capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing multiuser registers, I/O ports,
bidirectional bus drivers, and working registers.
With the clock-enable (CLKEN) input low, the eight edge-triggered D-type flip-flops enter data on the low-to-high
transition of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. The 74ACT11825
has noninverting data (D) inputs. Taking the clear (CLR) input low causes the eight Q outputs to go low
independently of the clock.
Multiuser buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either
a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased drive provide the capability to drive bus lines without need for interface
or pullup components. The output enable (OE) does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in the high-impedance state.
The 74ACT11825 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
INPUTS
OUTPUT
OE
CLR
CLKEN
CLK
D
OUTPUT
Q
L
L
X
X
X
L
L
H
L
H
H
L
H
L
L
L
L
H
H
X
X
Q0
H
X
X
X
X
Z
OE = H if any of OE1, OE2, or OE3 are high.
OE = L if all of OE1, OE2, or OE3 are low.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE1
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
CLR
OE2
OE3
1D
2D
3D
4D
V
CC
V
CC
5D
6D
7D
8D
CLKEN
CLK
DW PACKAGE
(TOP VIEW)
74ACT11825
8-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS154A D3715, NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
22
logic symbol
logic diagram (positive logic)
CLKEN
CLR
OE3
OE2
OE1
&
EN
CLK
1D
2D
3D
4D
5D
6D
7D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
C1
C1
8D
8Q
26
15
28
25
24
23
20
19
18
17
2
3
4
5
10
11
12
13
1D
1D
1D
1D
1D
1D
1D
1D
C1
C1
C1
C1
C1
C1
16
CLKEN
CLR
14
OE3
27
OE2
1
OE1
R
R
R
R
R
R
R
R
1
15
CLK
1C2
2D
26
1D
25
2D
24
3D
23
4D
1Q
2
2Q
3
3Q
4
4Q
5
28
27
R
14
G1
16
20
5D
19
6D
18
7D
17
8D
5Q
10
6Q
11
7Q
12
8Q
13
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
74ACT11825
8-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS154A D3715, NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
23
recommended operating conditions (see Note 2)
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
24
mA
IOL
Low-level output current
24
mA
t /
v
Input transition rise or fall rate
0
10
ns / V
TA
Operating free-air temperature
40
85
C
NOTE 2: Unused or floating inputs must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
IOH = 50
A
4.5 V
4.4
4.4
IOH = 50
A
5.5 V
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
V
IOH = 24 mA
5.5 V
4.94
4.8
IOH = 75 mA
5.5 V
3.85
IOL = 50
A
4.5 V
0.1
0.1
IOL = 50
A
5.5 V
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
V
IOL = 24 mA
5.5 V
0.36
0.44
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
0.1
1
A
IOZ
VO = VCC or GND
5.5 V
0.5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
A
I
One input at 3 4 V
Other inputs at VCC or GND
5 5 V
0 9
1
mA
ICC
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4.5
pF
Co
VO = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
74ACT11825
8-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS154A D3715, NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
24
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V
0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25
C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
122
0
122
MHz
t
Pulse duration
CLR low
4
4
ns
tw
Pulse duration
CLK high or low
4.5
4.5
ns
CLR inactive
3
3
tsu
Setup time before CLK
Data
3
3
ns
CLKEN high or low
3
3
th
Hold time after CLK
Data
1.5
1.5
ns
th
Hold time after CLK
CLKEN high or low
2
2
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
MIN
MAX
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
UNIT
fmax
122
122
MHz
tPLH
CLK
Q
4.6
7.7
10.2
4.6
11.6
ns
tPHL
CLK
Q
5.1
8.4
10.9
5.1
12.3
ns
tPHL
CLR
Q
4.5
8.5
11.9
4.5
13.2
ns
tPZH
OE
Q
3.3
6.4
9.2
3.3
10.4
ns
tPZL
OE
Q
4.2
7.9
11.5
4.2
13
ns
tPHZ
OE
Q
6.1
8.5
10.7
6.1
12
ns
tPLZ
OE
Q
5.5
7.9
10
5.5
11.2
ns
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance
Outputs enabled
CL = 50 pF
f = 1 MHz
47
pF
Cpd
Power dissipation capacitance
Outputs disabled
CL = 50 pF,
f = 1 MHz
34
pF
74ACT11825
8-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS154A D3715, NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
25
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V
1.5 V
3 V
0 V
50% VCC
50% VCC
Input
(see Note B)
Out-of-Phase
Output
In-Phase
Output
Timing Input
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
[
VCC
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
3 V
0 V
1.5 V
1.5 V
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
74ACT11825
8-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS154A D3715, NOVEMBER 1990 REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
26
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1998, Texas Instruments Incorporated
PDF 
ZIP