54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCAS164A JANUARY 1991 REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
TM
Family
D
Inputs Are TTL-Voltage Compatible
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
TM
(Enhanced-Performance Implanted
CMOS) 1-
m Process
D
500-mA Typical Latch-Up Immunity at
125
C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The 'ACT16657 contain two noninverting octal
transceiver sections with separate parity
generator/checker circuits and control signals.
For either section, the transmit/receive (1T/R or
2T/R) input determines the direction of data flow.
When 1T/R (or 2T/R) is high, data flows from the
1A (or 2A) port to the 1B (or 2B) port (transmit
mode); when 1T/R (or 2T/R) is low, data flows
from the 1B (or 2B) port to the 1A (or 2A) port
(receive mode). When the output-enable (1OE or
2OE) input is high, both the 1A (or 2A) and 1B (or
2B) ports are in the high-impedance state.
Odd or even parity is selected by a logic high or
low level, respectively, on the 1ODD/EVEN (or
2ODD/EVEN) input. 1PARITY (or 2PARITY)
carries the parity bit value; it is an output from the
parity generator/checker in the transmit mode and
an input to the parity generator/checker in the
receive mode.
In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or
2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or
2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on
the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus
bits plus parity bit) are high.
Copyright
1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
NC
1ERR
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2ERR
NC
2OE
1T/R
1ODD/EVEN
1PARITY
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2PARITY
2ODD/EVEN
2T/R
54ACT16657 . . . WD PACKAGE
74ACT16657 . . . DL PACKAGE
(TOP VIEW)
NC No internal connection
54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCAS164A JANUARY 1991 REVISED APRIL 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
In the receive mode, after the 1B (or 2B) bus is polled to determine the number of high bits, the 1ERR (or 2ERR)
output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example,
if 1ODD/EVEN is high (odd parity selected), 1PARITY is high, and there are three high bits on the 1B bus, then
1ERR is low, indicating a parity error.
The 74ACT16657 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16657 is characterized for operation over the full military temperature range of 55
C to 125
C. The
74ACT16657 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
NUMBER OF A OR B
INPUTS
INPUT/OUTPUT
OUTPUTS
NUMBER OF A OR B
INPUTS THAT ARE HIGH
OE
T/R
ODD/EVEN
INPUT/OUTPUT
PARITY
ERR
OUTPUT MODE
L
H
H
H
Z
Transmit
L
H
L
L
Z
Transmit
0 2 4 6 8
L
L
H
H
H
Receive
0, 2, 4, 6, 8
L
L
H
L
L
Receive
L
L
L
H
L
Receive
L
L
L
L
H
Receive
L
H
H
L
Z
Transmit
L
H
L
H
Z
Transmit
1 3 5 7
L
L
H
H
L
Receive
1, 3, 5, 7
L
L
H
L
H
Receive
L
L
L
H
H
Receive
L
L
L
L
L
Receive
Don't care
H
X
X
Z
Z
Z
54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCAS164A JANUARY 1991 REVISED APRIL 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
1A2
6
1A3
8
1A4
9
1A5
10
1A6
12
1A7
13
1A8
14
2A2
16
2A3
17
2A4
19
2A5
20
2A6
21
2A7
23
2A8
24
1OE
1A1
5
Z11
G3
1
3 EN1/3G5 [REC]
56
3 EN2 [XMIT]
N4
55
G8
28
8 EN6/8G10 [REC]
29
8 EN7 [XMIT]
N9
30
1B1
52
1B2
51
1B3
49
1B4
48
1B5
47
1B6
45
1B7
44
1B8
43
1PARITY
54
5
3
1T/R
1ODD/EVEN
2OE
2T/R
2ODD/EVEN
1ERR
1
2
11
18
2k
4, 2
4, 1
2A1
15
Z21
2B1
42
2B2
41
2B3
40
2B4
38
2B5
37
2B6
36
2B7
34
2B8
33
2PARITY
31
10
26
21
28
2ERR
6
7
2k
9, 7
9, 6
1
1
1
1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCAS164A JANUARY 1991 REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram, each transceiver (positive logic)
T/R
OE
ERR
A1
A2
A3
A4
A5
A6
A7
A8
ODD/EVEN
PARITY
B2
B3
B4
B5
B6
B7
B8
B1
54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCAS164A JANUARY 1991 REVISED APRIL 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
500 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum package power dissipation at T
A
= 55
C (in still air) (see Note 2): DL package
1.4 W
. . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
_
C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16657
74ACT16657
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
24
24
mA
IOL
Low-level output current
24
24
mA
t/
v
Input transition rise or fall rate
0
10
0
10
ns/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCAS164A JANUARY 1991 REVISED APRIL 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
54ACT16657
74ACT16657
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
IOH = 50
A
4.5 V
4.4
4.4
4.4
IOH = 50
A
5.5 V
5.4
5.4
5.4
VOH
IOH = 24 mA
4.5 V
3.94
3.8
3.8
V
IOH = 24 mA
5.5 V
4.94
4.8
4.8
IOH = 75 mA
5.5 V
3.85
3.85
IOL = 50
A
4.5 V
0.1
0.1
0.1
IOL = 50
A
5.5 V
0.1
0.1
0.1
VOL
IOL = 24 mA
4.5 V
0.36
0.44
0.44
V
IOL = 24 mA
5.5 V
0.36
0.44
0.44
IOL = 75 mA
5.5 V
1.65
1.65
II
A or B ports
VI = VCC or GND
5.5 V
0.1
1
1
A
IOZ
Control inputs
VO = VCC or GND
5.5 V
0.5
5
5
A
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
80
A
ICC
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
0.9
1
1
mA
Ci
Control inputs
VI = VCC or GND
5 V
4.5
pF
Co
ERR
VO = VCC or GND
5 V
11
pF
Cio
A or B ports
VO = VCC or GND
5 V
12
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25
C
54ACT16657
74ACT16657
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
tPLH
A or B
B or A
4.1
7.3
9.6
4.1
10.7
4.1
10.7
ns
tPHL
A or B
B or A
3.2
6.8
9.8
3.2
10.6
3.2
10.6
ns
tPLH
A
PARITY
4
8.6
12.9
4
14.3
4
14.3
ns
tPHL
A
PARITY
4.3
9
13.1
4.3
14.3
4.3
14.3
ns
tPLH
ODD/EVEN
PARITY ERR
3.7
8.3
12.3
3.7
13.7
3.7
13.7
ns
tPHL
ODD/EVEN
PARITY, ERR
4.1
8.8
12.8
4.1
14.1
4.1
14.1
ns
tPLH
B
ERR
3.9
8.6
13
3.9
14.6
3.9
14.6
ns
tPHL
B
ERR
4.3
9
13.3
4.3
14.7
4.3
14.7
ns
tPLH
PARITY
ERR
3.8
8.4
12.2
3.8
13.8
3.8
13.8
ns
tPHL
PARITY
ERR
4.1
8
12.8
4.1
14.2
4.1
14.2
ns
tPZH
OE
A B PARITY or ERR
2.6
6.1
10.1
2.6
11.3
2.6
11.3
ns
tPZL
OE
A, B, PARITY, or ERR
3.2
7.2
11.7
3.2
13
3.2
13
ns
tPHZ
OE
A B PARITY or ERR
5.9
8.6
10.5
5.9
11.2
5.9
11.2
ns
tPLZ
OE
A, B, PARITY, or ERR
5.3
8
9.8
5.3
10.5
5.3
10.5
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
54ACT16657, 74ACT16657
16-BIT TRANSCEIVERS
WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SCAS164A JANUARY 1991 REVISED APRIL 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics, V
CC
= 5 V, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
C d
Power dissipation capacitance per transceiver
Outputs enabled
CL = 50 pF
f = 1 MHz
76
pF
Cpd
Power dissipation capacitance per transceiver
Outputs disabled
CL = 50 pF,
f = 1 MHz
35
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCC
500
500
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
tPHL
tPLH
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
1.5 V
1.5 V
[
VCC
3 V
0 V
50% VCC
50% VCC
VOH
VOL
0 V
50% VCC
20% VCC
50% VCC
80% VCC
[
0 V
3 V
GND
Open
Input
Output
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO = 50
, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright
1998, Texas Instruments Incorporated
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