SN74ALVC164245
16 BIT 2.5 V TO 3.3 V/3.3 V TO 5 V LEVEL SHIFTING TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS416L - MARCH 1994 - REVISED FEBRUARY 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
Max t
pd
of 5.8 ns at 3.3 V
D
24-mA Output Drive at 3.3 V
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
description/ordering information
This 16-bit (dual-octal) noninverting bus
transceiver contains two separate supply rails.
B port has V
CCB
, which is set to operate at 3.3 V
and 5 V. A port has V
CCA
, which is set to operate
at 2.5 V and 3.3 V. This allows for translation from
a 2.5-V to a 3.3-V environment, and vice versa, or
from a 3.3-V to a 5-V environment, and vice versa.
The SN74ALVC164245 is designed for
asynchronous communication between data
buses.
To ensure the high-impedance state during power
up or power down, the output-enable (OE) input
should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP - DL
Tube of 25
SN74ALVC164245DL
ALVC164245
SSOP - DL
Reel of 1000
SN74ALVC164245DLR
ALVC164245
-40
C to 85
C
TSSOP - DGG
Reel of 2000
SN74ALVC164245DGGR
ALVC164245
-40
C to 85
C
TSSOP - DGG
Reel of 250
SN74ALVC164245DGGT
ALVC164245
VFBGA - GQL
Reel of 1000
SN74ALVC164245KR
VC4245
VFBGA - ZQL (Pb-free)
Reel of 1000
74ALVC164245ZQLR
VC4245
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Copyright
2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
(3.3 V, 5 V) V
CCB
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
(3.3 V, 5 V) V
CCB
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CCA
(2.5 V, 3.3 V)
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CCA
(2.5 V, 3.3 V)
2A5
2A6
GND
2A7
2A8
2OE
SN74ALVC164245
16 BIT 2.5 V TO 3.3 V/3.3 V TO 5 V LEVEL SHIFTING TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS416L - MARCH 1994 - REVISED FEBRUARY 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
terminal assignments
1
2
3
4
5
6
A
1DIR
NC
NC
NC
NC
1OE
B
1B2
1B1
GND
GND
1A1
1A2
C
1B4
1B3
VCCB
VCCA
1A3
1A4
D
1B6
1B5
GND
GND
1A5
1A6
E
1B8
1B7
1A7
1A8
F
2B1
2B2
2A2
2A1
G
2B3
2B4
GND
GND
2A4
2A3
H
2B5
2B6
VCCB
VCCA
2A6
2A5
J
2B7
2B8
GND
GND
2A8
2A7
K
2DIR
NC
NC
NC
NC
2OE
NC - No internal connection
logic diagram (positive logic)
To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13
Pin numbers shown are for the DGG and DL packages.
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
K
SN74ALVC164245
16 BIT 2.5 V TO 3.3 V/3.3 V TO 5 V LEVEL SHIFTING TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS416L - MARCH 1994 - REVISED FEBRUARY 2004
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range for V
CCB
at 5 V and
V
CCA
at 3.3 V (unless otherwise noted)
Supply voltage range: V
CCA
-0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
CCB
-0.5 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: Except I/O ports (see Note 1)
-0.5 V to 6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port A (see Note 2)
-0.5 V to V
CCA
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port B (see Note 1)
-0.5 V to V
CCB
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGG package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
63
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL/ZQL package
42
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. This value is limited to 6 V maximum.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions for V
CCB
at 3.3 V and 5 V (see Note 4)
MIN
MAX
UNIT
VCCB
Supply voltage
3
5.5
V
VIH
High-level input voltage
2
V
VIL
Low-level input voltage
VCCB = 3 V to 3.6 V
0.7
V
VIL
Low-level input voltage
VCCB = 4.5 V to 5.5 V
0.8
V
VIA
Input voltage
0
VCCB
V
VOB
Output voltage
0
VCCB
V
IOH
High-level output current
-24
mA
IOL
Low-level output current
24
mA
t/
v
Input transition rise or fall rate
10
ns/V
TA
Operating free-air temperature
-40
85
C
NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVC164245
16 BIT 2.5 V TO 3.3 V/3.3 V TO 5 V LEVEL SHIFTING TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS416L - MARCH 1994 - REVISED FEBRUARY 2004
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions for V
CCA
at 2.5 V and 3.3 V (see Note 4)
MIN
MAX
UNIT
VCCA
Supply voltage
2.3
3.6
V
VIH
High-level input voltage
VCCA = 2.3 V to 2.7 V
1.7
V
VIH
High-level input voltage
VCCA = 3 V to 3.6 V
2
V
VIL
Low-level input voltage
VCCA = 2.3 V to 2.7 V
0.7
V
VIL
Low-level input voltage
VCCA = 3 V to 3.6 V
0.8
V
VIB
Input voltage
0
VCCA
V
VOA
Output voltage
0
VCCA
V
IOH
High-level output current
VCCA = 2.3 V
-18
mA
IOH
High-level output current
VCCA = 3 V
-24
mA
IOL
Low-level output current
VCCA = 2.3 V
18
mA
IOL
Low-level output current
VCCA = 3 V
24
mA
t/
v
Input transition rise or fall rate
10
ns/V
TA
Operating free-air temperature
-40
85
C
NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range for
V
CCA
= 2.7 V to 3.6 V and V
CCB
= 4.5 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
MIN
TYP
MAX
UNIT
IOH = -100
A
2.7 V to 3.6 V
VCC-0.2
VOH (B to A)
IOH = -12 mA
2.7 V
2.2
V
VOH (B to A)
IOH = -12 mA
3 V
2.4
V
IOH = -24 mA
3 V
2
IOH = -100 A
4.5 V
4.3
VOH (A to B)
IOH = -100
A
5.5 V
5.3
V
VOH (A to B)
IOH = -24 mA
4.5 V
3.7
V
IOH = -24 mA
5.5 V
4.7
IOL = 100
A
2.7 V to 3.6 V
0.2
VOL (B to A)
IOL = 12 mA
2.7 V
0.4
V
VOL (B to A)
IOL = 24 mA
3 V
0.55
V
VOL (A to B)
IOL = 100
A
4.5 V to 5.5 V
0.2
V
VOL (A to B)
IOL = 24 mA
4.5 V to 5.5 V
0.55
V
II
Control inputs
VI = VCCA/VCCB or GND
3.6 V
5.5 V
5
A
IOZ
A or B ports
VO = VCCA/VCCB or GND
3.6 V
5.5 V
10
A
ICC
VI = VCCA/VCCB or GND, IO = 0
5.5 V
5.5 V
40
A
ICC
One input at VCCA/VCCB - 0.6 V,
Other inputs at VCCA/VCCB or GND
3 V to 3.6 V
4.5 V to 5.5 V
750
A
Ci
Control inputs
VI = VCCA/VCCB or GND
3.3 V
5 V
6.5
pF
Cio
A or B ports
VO = VCCA/VCCB or GND
3.3 V
3.3 V
8.5
pF
Typical values are measured at VCCA = 3.3 V and VCCB = 5 V, TA = 25
C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associated VCC.
SN74ALVC164245
16 BIT 2.5 V TO 3.3 V/3.3 V TO 5 V LEVEL SHIFTING TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS416L - MARCH 1994 - REVISED FEBRUARY 2004
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range for
V
CCA
= 2.3 V to 2.7 V and V
CCB
= 3 V to 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
MIN
MAX
UNIT
IOH = -100
A
2.3 V to 2.7 V
3 V to 3.6 V
VCCA-0.2
VOH (B to A)
IOH = -8 mA
2.3 V
3 V to 3.6 V
1.7
V
VOH (B to A)
IOH = -12 mA
2.7 V
3 V to 3.6 V
1.8
V
VOH (A to B)
IOH = -100
A
2.3 V to 2.7 V
3 V to 3.6 V
VCCB-0.2
V
VOH (A to B)
IOH = -18 mA
2.3 V to 2.7 V
3 V
2.2
V
VOL (B to A)
IOL = 100
A
2.3 V to 2.7 V
3 V to 3.6 V
0.2
V
VOL (B to A)
IOL = 12 mA
2.3 V
3 V to 3.6 V
0.6
V
VOL (A to B)
IOL = 100
A
2.3 V to 2.7 V
3 V to 3.6 V
0.2
V
VOL (A to B)
IOL = 18 mA
2.3 V
3 V
0.55
V
II
Control inputs
VI = VCCA/VCCB or GND
2.3 V to 2.7 V
3 V to 3.6 V
5
A
IOZ
A or B ports
VO = VCCA/VCCB or GND
2.3 V to 2.7 V
3 V to 3.6 V
10
A
ICC
VI = VCCA/VCCB or GND, IO = 0
2.3 V to 2.7 V
3 V to 3.6 V
20
A
ICC
One input at VCCA/VCCB - 0.6 V,
Other inputs at VCCA/VCCB or GND
2.3 V to 2.7 V
3 V to 3.6 V
750
A
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associated VCC.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1-4)
FROM
TO
VCCB = 3.3 V
0.3 V
VCCB = 5 V
0.5 V
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCCA = 2.5 V
0.2 V
VCCA = 2.7 V
VCCA = 3.3 V
0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tpd
A
B
7.6
5.9
1
5.8
ns
tpd
B
A
7.6
6.7
1.2
5.8
ns
ten
OE
B
11.5
9.3
1
8.9
ns
tdis
OE
B
10.5
9.2
2.1
9.5
ns
ten
OE
A
12.3
10.2
2
9.1
ns
tdis
OE
A
9.3
9
2.9
8.6
ns
operating characteristics, T
A
= 25
C
VCCB = 3.3 V
VCCB = 5 V
PARAMETER
TEST CONDITIONS
VCCA = 2.5 V
VCCA = 3.3 V
UNIT
PARAMETER
TEST CONDITIONS
TYP
TYP
UNIT
Outputs enabled (B)
CL = 50 pF,
f = 10 MHz
55
56
Cpd
Power dissipation
capacitance
Outputs disabled (B)
CL = 50 pF,
f = 10 MHz
27
6
pF
Cpd
Power dissipation
capacitance
Outputs enabled (A)
CL = 50 pF,
f = 10 MHz
118
56
pF
Outputs disabled (A)
CL = 50 pF,
f = 10 MHz
58
6
SN74ALVC164245
16 BIT 2.5 V TO 3.3 V/3.3 V TO 5 V LEVEL SHIFTING TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS416L - MARCH 1994 - REVISED FEBRUARY 2004
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
power-up considerations
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up
problems:
1.
Connect ground before any supply voltage is applied.
2.
Power up the control side of the device (V
CCA
for all four of these devices).
3.
Tie OE to V
CCA
with a pullup resistor so that it ramps with V
CCA
.
4.
Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with V
CCA
. Otherwise, keep DIR low.
Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
SN74ALVC164245
16 BIT 2.5 V TO 3.3 V/3.3 V TO 5 V LEVEL SHIFTING TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS416L - MARCH 1994 - REVISED FEBRUARY 2004
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CCA
= 2.5 V
0.2 V TO V
CCB
= 3.3 V
0.3 V
VOHB
VOLB
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
VCCB = 6 V
Open
GND
500
500
tPLH
tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCCA/2
VCCA/2
VCCA/2
VCCA/2
VCCA
0 V
1.5 V
1.5 V
VOHB
VOLB
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH - 0.3 V
0 V
Input
VCCA
VCCB
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VCCB = 6 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2 ns, tf
2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
SN74ALVC164245
16 BIT 2.5 V TO 3.3 V/3.3 V TO 5 V LEVEL SHIFTING TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS416L - MARCH 1994 - REVISED FEBRUARY 2004
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CCB
= 3.3 V
0.3 V TO V
CCA
= 2.5 V
0.2 V
VCCA/2
VCCA/2
1.5 V
1.5 V
VOHA
VOLA
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCCA
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH - 0.15 V
0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCCA
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2 ns, tf
2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
tPHL
1.5 V
1.5 V
2.7 V
0 V
VOHA
VOLA
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCA/2
VCCA/2
tPLH
2
VCCA
VCCA
Figure 2. Load Circuit and Voltage Waveforms
SN74ALVC164245
16 BIT 2.5 V TO 3.3 V/3.3 V TO 5 V LEVEL SHIFTING TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS416L - MARCH 1994 - REVISED FEBRUARY 2004
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CCA
= 3.3 V
0.3 V TO V
CCB
= 5 V
0.5 V
tPLH
VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
VCCB
Open
GND
500
500
tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCCB
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
1.5 V
1.5 V
2.7 V
0 V
50% VCCB
50% VCCB
VOH
VOL
0 V
20% VCCB
50% VCCB
80% VCCB
0 V
Input
2.7 V
VCCB
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCCB
GND
TEST
S1
50% VCCB
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
SN74ALVC164245
16 BIT 2.5 V TO 3.3 V/3.3 V TO 5 V LEVEL SHIFTING TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS416L - MARCH 1994 - REVISED FEBRUARY 2004
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CCB
= 5 V
0.5 V TO V
CCA
= 2.7 V AND 3.3 V
0.3 V
VOHA
VOLA
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
VCCA = 6 V
Open
GND
500
500
tPLH
tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
1.5 V
1.5 V
3 V
0 V
1.5 V
1.5 V
VOHA
VOLA
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH - 0.3 V
0 V
Input
3 V
3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VCCA = 6 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MSSO001C JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040048 / E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
48
28
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0
8
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040078 / F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0
8
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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