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FEATURES
DESCRIPTION/ORDERING INFORMATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
Y1
GND
Y2
Y3
V
CC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
V
CC
Y16
Y17
GND
Y18
OE
LE
GND
NC
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
CLK
GND
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
NC - No internal connection
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES397A JULY 2002 REVISED AUGUST 2004
Member of the Texas Instruments WidebusTM
Family
Ideal for Use in PC133 Register DIMM
Typical Output Skew . . . <250 ps
V
CC
= 3.3 V
0.3 V . . . Normal Range
V
CC
= 2.7 V to 3.6 V . . . Extended Range
V
CC
= 2.5 V
0.2 V
Rail-to-Rail Output Swing for Increased Noise
Margin
Balanced Output Drivers . . .
18 mA
Low Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
This 18-bit universal bus driver is designed for 2.3-V
to 3.6-V V
CC
operation.
Data
flow
from
A
to
Y
is
controlled
by
the
output-enable (OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
high. When LE is low, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE is high,
the outputs are in the high-impedance state.
The
SN74ALVCF162835
has
series
damping
resistors in the device output structure that reduce
switching noise in 128-MB and 256-MB SDRAM
modules. Designed with a drive capability of
18 mA,
this
device
is
a
midway
drive
between
the
SN74ALVC162835 (
12 mA) and SN74ALVC16835
(
24 mA).
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Tube
SN74ALVCF162835DL
SSOP - DL
ALVCF162835
Tape and reel
SN74ALVCF162835DLR
-40
C to 85
C
TSSOP - DGG
Tape and reel
SN74ALVCF162835GR
ALVCF162835
TVSOP - DGV
Tape and reel
SN74ALVCF162835VR
VF2835
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 20022004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
OE
CLK
Y1
1D
C1
CLK
To 17 Other Channels
LE
A1
27
30
28
54
3
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES397A JULY 2002 REVISED AUGUST 2004
The SN74ALVCF162835 is a faster version of the SN74ALVC162835. It is suitable for PC133 applications and,
particularly, SDRAM modules clocked at 133 MHz.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
LE
CLK
A
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
L
L
L
L
H
H
L
L
L or H
X
Y
0
(1)
(1)
Output level before the indicated steady-state input conditions were
established
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
(1)
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES397A JULY 2002 REVISED AUGUST 2004
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC
Supply voltage range
-0.5
4.6
V
V
I
Input voltage range
(2)
-0.5
4.6
V
V
O
Output voltage range
(2) (3)
-0.5
V
CC
+ 0.5
V
I
IK
Input clamp current
V
I
< 0 or V
I
< V
CC
-50
mA
I
OK
Output clamp current
V
O
< 0
-50
mA
I
O
Continuous output current
50
mA
Continuous current through each V
CC
or GND
100
mA
DGG package
64
JA
Package thermal impedance
(4)
DGV package
48
C/W
DL package
56
T
stg
Storage temperature range
-65
150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
This value is limited to 4.6 V maximum.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
MIN
MAX
UNIT
V
CC
Supply voltage
2.3
3.6
V
V
CC
= 2.3 V to 2.7 V
1.7
V
IH
High-level input voltage
V
V
CC
= 2.7 V to 3.6 V
2
V
CC
= 2.3 V to 2.7 V
0.7
V
IL
Low-level input voltage
V
V
CC
= 2.7 V to 3.6 V
0.8
V
I
Input voltage
0
V
CC
V
V
O
Output voltage
0
V
CC
V
-6
V
CC
= 2.3 V
-8
-6
I
OH
High-level output current
V
CC
= 2.7 V
mA
-12
-8
V
CC
= 3 V
-18
6
V
CC
= 2.3 V
8
6
I
OL
Low-level output current
V
CC
= 2.7 V
mA
12
8
V
CC
= 3 V
18
t/
v
Input transition rise or fall rate
10
ns/V
T
A
Operating free-air temperature
-40
85
C
(1)
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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ELECTRICAL CHARACTERISTICS
TIMING REQUIREMENTS
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES397A JULY 2002 REVISED AUGUST 2004
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
(1)
MAX
UNIT
I
OH
= -0.1 mA
2.3 V to 3.6 V
V
CC
- 0.2
I
OH
= -6 mA
1.9
2.3 V
I
OH
= -8 mA
1.7
V
OH
I
OH
= -6 mA
2.2
V
2.7 V
I
OH
= -12 mA
2
I
OH
= -8 mA
2.4
3 V
I
OH
= -18 mA
2
I
OL
= 0.1 mA
2.3 V to 3.6 V
0.2
I
OL
= 6 mA
0.4
2.3 V
I
OL
= 8 mA
0.55
V
OL
I
OL
= 6 mA
0.4
V
2.7 V
I
OL
= 12 mA
0.6
I
OL
= 8 mA
0.55
3 V
I
OL
= 18 mA
0.8
V
IK
V
CC
= 2.3 V,
I
I
= -18 mA
3.6 V
-1.2
V
V
hys
V
CC
= 3.6 V
3.6 V
100
mV
I
I
V
I
= V
CC
or GND
3.6 V
5
A
I
OZ
V
O
= V
CC
or GND
3.6 V
10
A
I
CC
V
I
= V
CC
or GND,
I
O
= 0
3.6 V
0.1
40
A
I
CC
One input at V
CC
- 0.6 V,
Other inputs at V
CC
or GND
3 V to 3.6 V
750
A
C
i
Inputs
V
I
= 0 V
3.3 V
3.5
pF
C
o
Outputs
V
O
= 0 V
3.3 V
4.5
pF
(1)
All typical values are at V
CC
= 3.3 V, T
A
= 25
C.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Figure 2)
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 2.7 V
0.2 V
0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
f
clock
Clock frequency
150
150
150
MHz
LE high
3.3
3.3
3.3
t
w
Pulse duration
ns
CLK high or low
3.3
3.3
3.3
Data before CLK
1.8
1.5
1
t
su
Setup time
CLK high
1.9
1.6
1.5
ns
Data before LE
CLK low
1.3
1.1
1
Data after CLK
0.6
0.6
0.6
t
h
Hold time
ns
Data after LE
CLK high or low
1.4
1.7
1.4
4
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SWITCHING CHARACTERISTICS
SWITCHING CHARACTERISTICS
OPERATING CHARACTERISTICS
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES397A JULY 2002 REVISED AUGUST 2004
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Figure 2)
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 2.7 V
FROM
TO
0.2 V
0.3 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
f
max
150
150
150
MHz
A
1
4
4.6
1
3.5
t
pd
LE
Y
1.3
5.5
5.4
1.3
4.6
ns
CLK
1.4
5.9
5.6
1.4
3.5
t
en
OE
Y
1.4
5.9
6
1.1
5
ns
t
dis
OE
Y
1
4.7
4.6
1.3
4.2
ns
t
sk(o)
500
ps
from 0
C to 65
C, C
L
= 50 pF
V
CC
= 3.3 V
FROM
TO
0.15 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
t
pd
CLK
Y
1.8
3.5
ns
T
A
= 25
C
V
CC
= 2.5 V
V
CC
= 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
Outputs enabled
27
33
C
pd
Power dissipation capacitance
C
L
= 0 pF,
f = 10 MHz
pF
Outputs disabled
16
21
5
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PARAMETER MEASUREMENT INFORMATION
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
C
L
= 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
V
OL
+ 0.15 V
V
OH
- 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
2
V
CC
GND
TEST
S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
, t
r
2 ns, t
f
2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
0 V
V
CC
V
CC
/2
t
PHL
V
CC
/2
V
CC
/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
CC
/2
V
CC
/2
t
PLH
2
V
CC
V
CC
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES397A JULY 2002 REVISED AUGUST 2004
V
CC
= 2.5 V
0.2 V
Figure 1. Load Circuit and Voltage Waveforms
6
www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
OH
V
OL
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500
500
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
1.5 V
1.5 V
2.7 V
0 V
1.5 V
1.5 V
V
OH
V
OL
0 V
1.5 V
V
OL
+ 0.3 V
1.5 V
V
OH
- 0.3 V
0 V
1.5 V
2.7 V
0 V
0 V
2.7 V
0 V
Input
2.7 V
2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
6 V
GND
TEST
S1
1.5 V
1.5 V
t
w
t
h
t
su
1.5 V
1.5 V
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
, t
r
2.5 ns, t
f
2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES397A JULY 2002 REVISED AUGUST 2004
V
CC
= 2.7 V AND 3.3 V
0.3 V
Figure 2. Load Circuit and Voltage Waveforms
7
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74ALVCF162835GRE4
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ALVCF162835VRE4
ACTIVE
TVSOP
DGV
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVCF162835DL
ACTIVE
SSOP
DL
56
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVCF162835GR
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVCF162835LR
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVCF162835VR
ACTIVE
TVSOP
DGV
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
Addendum-Page 1
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50
4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
1
12
24
13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
38
24
16
4,90
5,10
3,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins MO-153
14/16/20/56 Pins MO-194
MECHANICAL DATA
MSSO001C JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040048 / E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
48
28
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0
8
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040078 / F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0
8
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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2005, Texas Instruments Incorporated
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