SN74ALVCH32501
36 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
SCES144E - OCTOBER 1998 - REVISED AUGUST 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus+
Family
D
UBT
Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, or
Clocked Mode
D
Operates From 1.65 V to 3.6 V
D
Max t
pd
of 3.9 ns at 3.3 V
D
24-mA Output Drive at 3.3 V
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
description/ordering information
This 36-bit universal bus transceiver is designed for 1.65-V to 3.6-V V
CC
operation.
This device can be used as two 18-bit transceivers or one 36-bit transceiver. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When
OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or power down, OEBA should be tied to V
CC
through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
-40
C to 85
C
LFBGA - GKF
Tape and reel
SN74ALVCH32501KR
ACH501
-40
C to 85
C
LFBGA - ZKF (Pb-free)
Tape and reel
74ALVCH32501ZKFR
ACH501
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UBT and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74ALVCH32501
36 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
SCES144E - OCTOBER 1998 - REVISED AUGUST 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
terminal assignments
1
2
3
4
5
6
A
1A2
1A1
1LEAB
1CLKAB
1B1
1B2
B
1A4
1A3
1OEAB
GND
1B3
1B4
C
1A6
1A5
GND
GND
1B5
1B6
D
1A8
1A7
VCC
VCC
1B7
1B8
E
1A10
1A9
GND
GND
1B9
1B10
F
1A12
1A11
GND
GND
1B11
1B12
G
1A14
1A13
VCC
VCC
1B13
1B14
H
1A15
1A16
GND
GND
1B16
1B15
J
1A17
1A18
1OEBA
1CLKBA
1B18
1B17
K
NC
2LEAB
1LEBA
GND
2CLKAB
NC
L
2A2
2A1
2OEAB
GND
2B1
2B2
M
2A4
2A3
GND
GND
2B3
2B4
N
2A6
2A5
VCC
VCC
2B5
2B6
P
2A8
2A7
GND
GND
2B7
2B8
R
2A10
2A9
GND
GND
2B9
2B10
T
2A12
2A11
VCC
VCC
2B11
2B12
U
2A14
2A13
GND
GND
2B13
2B14
V
2A15
2A16
2OEBA
2CLKBA
2B16
2B15
W
2A17
2A18
2LEBA
GND
2B18
2B17
FUNCTION TABLE
INPUTS
OUTPUT
OEAB
LEAB
CLKAB
A
OUTPUT
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
H
X
B0
H
L
L
X
B0
A-to-B data flow is shown; B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low
Output level before the indicated steady-state input
conditions were established
GKF OR ZKF PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
P
N
M
L
K
T
R
U
W
V
NC - No internal connection
SN74ALVCH32501
36 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
SCES144E - OCTOBER 1998 - REVISED AUGUST 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
1B1
1OEAB
1CLKAB
1LEAB
1LEBA
1CLKBA
1OEBA
1A1
B3
A4
A3
K3
J4
J3
A2
A5
To 17 Other Channels
SN74ALVCH32501
36 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
SCES144E - OCTOBER 1998 - REVISED AUGUST 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
2B1
2OEAB
2CLKAB
2LEAB
2LEBA
2CLKBA
2OEBA
2A1
L3
K5
K2
W3
V4
V3
L2
L5
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: Except I/O ports (see Note 1)
-0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): GKF/ZKF
36
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74ALVCH32501
36 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
SCES144E - OCTOBER 1998 - REVISED AUGUST 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
0.65
VCC
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
2
V
VCC = 1.65 V to 1.95 V
0.35
VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
-4
IOH
High-level output current
VCC = 2.3 V
-12
mA
IOH
High-level output current
VCC = 2.7 V
-12
mA
VCC = 3 V
-24
VCC = 1.65 V
4
IOL
Low-level output current
VCC = 2.3 V
12
mA
IOL
Low-level output current
VCC = 2.7 V
12
mA
VCC = 3 V
24
t/
v
Input transition rise or fall rate
10
ns/V
TA
Operating free-air temperature
-40
85
C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74ALVCH32501
36 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
SCES144E - OCTOBER 1998 - REVISED AUGUST 2003
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
IOH = -100
A
1.65 V to 3.6 V
VCC-0.2
IOH = -4 mA
1.65 V
1.2
IOH = -6 mA
2.3 V
2
VOH
2.3 V
1.7
V
VOH
IOH = -12 mA
2.7 V
2.2
V
IOH = -12 mA
3 V
2.4
IOH = -24 mA
3 V
2
IOL = 100
A
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
VOL
IOL = 6 mA
2.3 V
0.4
V
VOL
IOL = 12 mA
2.3 V
0.7
V
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3 V
0.55
II
VI = VCC or GND
3.6 V
5
A
VI = 0.58 V
1.65 V
25
VI = 1.07 V
1.65 V
-25
VI = 0.7 V
2.3 V
45
II(hold)
VI = 1.7 V
2.3 V
-45
A
II(hold)
VI = 0.8 V
3 V
75
A
VI = 2 V
3 V
-75
VI = 0 to 3.6 V
3.6 V
500
IOZ
VO = VCC or GND
3.6 V
10
A
ICC
VI = VCC or GND,
IO = 0
3.6 V
80
A
ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
3 V to 3.6 V
750
A
Ci
Control inputs
VI = VCC or GND
3.3 V
4
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
8
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 1.8 V
VCC = 2.5 V
0.2 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
150
150
150
MHz
tw
Pulse
LE high
3.3
3.3
3.3
ns
tw
Pulse
duration
CLK high or low
3.3
3.3
3.3
ns
Data before CLK
2.2
2.1
1.7
tsu
Setup time
Data before LE
CLK high
1.9
1.6
1.5
ns
tsu
Setup time
Data before LE
CLK low
1.3
1.1
1
ns
th
Hold time
Data after CLK
0.6
0.6
0.7
ns
th
Hold time
Data after LE
CLK high or low
1.4
1.7
1.4
ns
This information was not available at the time of publication.
SN74ALVCH32501
36 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
SCES144E - OCTOBER 1998 - REVISED AUGUST 2003
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
VCC = 2.5 V
0.2 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
150
150
150
MHz
A or B
B or A
1
4.8
4.5
1
3.9
tpd
LE
A or B
1.1
5.7
5.3
1.3
4.6
ns
tpd
CLK
A or B
1.2
6.1
5.6
1.4
4.9
ns
ten
OEAB
B
1
5.8
5.3
1
4.6
ns
tdis
OEAB
B
1.5
6.2
5.7
1.4
5
ns
ten
OEBA
A
1.3
6.3
6
1.1
5
ns
tdis
OEBA
A
1.3
5.3
4.6
1.3
4.2
ns
This information was not available at the time of publication.
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
UNIT
PARAMETER
TEST CONDITIONS
TYP
TYP
TYP
UNIT
Cpd
Power dissipation
Outputs enabled
CL = 0,
f = 10 MHz
44
54
pF
Cpd
Power dissipation
capacitance
Outputs disabled
CL = 0,
f = 10 MHz
6
6
pF
This information was not available at the time of publication.
SN74ALVCH32501
36 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
SCES144E - OCTOBER 1998 - REVISED AUGUST 2003
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
VM
VM
VM
VM
VM
VM
VM
VOH
VOL
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
Open
GND
RL
RL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + V
VOH - V
0 V
VI
0 V
0 V
tw
VI
VI
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
0 V
VI
VM
tPHL
VM
VM
VI
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
VM
tPLH
VLOAD
VLOAD/2
1.8 V
0.15 V
2.5
0.2 V
2.7 V
3.3 V
0.3 V
1 k
500
500
500
VCC
RL
2
VCC
2
VCC
6 V
6 V
VLOAD
CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
2.7 V
2.7 V
VI
VCC/2
VCC/2
1.5 V
1.5 V
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUT
Figure 1. Load Circuit and Voltage Waveforms
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2003, Texas Instruments Incorporated
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