74ALVCHS162830A
1 BIT TO 2 BIT ADDRESS DRIVER
WITH 3 STATE OUTPUTS
SCES624 - FEBRUARY 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
Output Ports Have Series Damping
Resistors, So No External Resistors Are
Required
D
Diodes on Inputs Clamp Overshoot
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
description/ordering information
This 1-bit to 2-bit address driver is designed for
2.3-V to 3.6-V V
CC
operation.
Diodes to V
CC
have been added on the inputs to
clamp overshoot.
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not
recommended.
The outputs, which are designed to sink up to
12 mA, include series damping resistors to reduce
overshoot and undershoot.
The ALVCHS162830A is an improved version of
the LVCHS162830 (non-A version) and has been
optimized for lower power consumption and
higher AC drive. Higher AC drive provides
capability to drive loads with a faster edge rate.
To ensure the high-impedance state during power
up or power down, the output-enable (OE) input
should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking capability of the driver.
Copyright
2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
DBB PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
2Y2
1Y2
GND
2Y1
1Y1
V
CC
A1
A2
GND
A3
A4
GND
A5
A6
V
CC
A7
A8
GND
A9
OE1
OE2
A10
GND
A11
A12
V
CC
A13
A14
GND
A15
A16
GND
A17
A18
V
CC
2Y18
1Y18
GND
2Y17
1Y17
1Y3
2Y3
GND
1Y4
2Y4
V
CC
1Y5
2Y5
GND
1Y6
2Y6
GND
1Y7
2Y7
V
CC
1Y8
2Y8
GND
1Y9
2Y9
1Y10
2Y10
GND
1Y11
2Y11
V
CC
1Y12
2Y12
GND
1Y13
2Y13
GND
1Y14
2Y14
V
CC
1Y15
2Y15
GND
1Y16
2Y16
74ALVCHS162830A
1 BIT TO 2 BIT ADDRESS DRIVER
WITH 3 STATE OUTPUTS
SCES624 - FEBRUARY 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
-40
C to 85
C
TVSOP - DBB
Tape and reel
74ALVCHS162830AGR
ALVCHS162830A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUTS
OE1
OE2
A
1Yn
2Yn
L
H
H
H
Z
L
H
L
L
Z
H
L
H
Z
H
H
L
L
Z
L
L
L
H
H
H
L
L
L
L
L
H
H
X
Z
Z
logic diagram (positive logic)
To 17 Other Channels
1Y1
2Y1
A1
OE2
OE1
21
20
7
5
4
VCC
VCC
VCC
74ALVCHS162830A
1 BIT TO 2 BIT ADDRESS DRIVER
WITH 3 STATE OUTPUTS
SCES624 - FEBRUARY 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0, V
I
> V
CC
)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3)
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC
Supply voltage
2.3
3.6
V
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
2
V
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
0.8
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2.3 V
-6
IOH
High-level output current
VCC = 2.7 V
-8
mA
IOH
High-level output current
VCC = 3 V
-12
mA
VCC = 2.3 V
6
IOL
Low-level output current
VCC = 2.7 V
8
mA
IOL
Low-level output current
VCC = 3 V
12
mA
t/
v
Input transition rise or fall rate
10
ns/V
TA
Operating free-air temperature
-40
85
C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
74ALVCHS162830A
1 BIT TO 2 BIT ADDRESS DRIVER
WITH 3 STATE OUTPUTS
SCES624 - FEBRUARY 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VIK
II = -18 mA
2.3 V
-1.2
V
VIK
II = 18 mA
2.3 V
VCC + 1.2
V
IOH = -100
A
2.3 V to 3.6 V
VCC - 0.2
IOH = -4 mA,
VIH = 1.7 V
2.3 V
1.9
VOH
IOH = -6 mA
VIH = 1.7 V
2.3 V
1.7
V
VOH
IOH = -6 mA
VIH = 2 V
3 V
2.4
V
IOH = -8 mA,
VIH = 2 V
2.7 V
2
IOH = -12 mA,
VIH = 2 V
3 V
2
IOL = 100
A
2.3 V to 3.6 V
0.2
IOL = 4 mA,
VIL = 0.7 V
2.3 V
0.4
VOL
IOL = 6 mA
VIL = 0.7 V
2.3 V
0.55
V
VOL
IOL = 6 mA
VIL = 0.8 V
3 V
0.55
V
IOL = 8 mA,
VIL = 0.8 V
2.7 V
0.6
IOL = 12 mA,
VIL = 0.8 V
3 V
0.8
II
VI = VCC or GND
3.6 V
5
A
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
-45
II(hold)
VI = 0.8 V
3 V
75
A
II(hold)
VI = 2 V
3 V
-75
A
VI = 0 to 3.6 V
3.6 V
500
IOZ
VO = VCC or GND
3.6 V
10
A
ICC
VI = VCC or GND,
IO = 0
3.6 V
20
A
ICC
One input at VCC - 0.6 V,
Other inputs at VCC or GND
3 V to 3.6 V
500
A
Ci
Control inputs
VI = VCC or GND
3.3 V
3.5
pF
Ci
Data inputs
VI = VCC or GND
3.3 V
4.5
pF
Co
Outputs
VO = VCC or GND
3.3 V
4.5
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 2.5 V
0.2 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tpd
A
Y
1.2
3.8
4
1.7
3.5
ns
ten
OE
Y
1
5.7
5.7
1
4.8
ns
tdis
OE
Y
1
4.9
5.4
1.7
5.2
ns
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
VCC = 2.5 V VCC = 3.3 V
UNIT
PARAMETER
TEST CONDITIONS
TYP
TYP
UNIT
Cpd
Power dissipation capacitance
One OE enabled
CL = 0,
f = 10 MHz
17
17.5
pF
Cpd
Power dissipation capacitance
per bit (one output switching)
All outputs disabled
CL = 0,
f = 10 MHz
0.4
0.5
pF
74ALVCHS162830A
1 BIT TO 2 BIT ADDRESS DRIVER
WITH 3 STATE OUTPUTS
SCES624 - FEBRUARY 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
VM
VM
VM
VM
VM
VM
VM
VOH
VOL
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
Open
GND
RL
RL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + V
VOH - V
0 V
VI
0 V
0 V
tw
VI
VI
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
0 V
VI
VM
tPHL
VM
VM
VI
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
VM
tPLH
VLOAD
VLOAD/2
2.5 V
0.2 V
2.7 V
3.3 V
0.3 V
500
500
500
VCC
RL
2
VCC
6 V
6 V
VLOAD
CL
30 pF
50 pF
50 pF
0.15 V
0.3 V
0.3 V
V
VCC
2.7 V
2.7 V
VI
VCC/2
1.5 V
1.5 V
VM
tr/tf
2 ns
2.5 ns
2.5 ns
INPUT
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74ALVCHS162830AGR
ACTIVE
TSSOP
DBB
80
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ALVCHS162830AGRE4
ACTIVE
TSSOP
DBB
80
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ALVCHS162830AGRG4
ACTIVE
TSSOP
DBB
80
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2005
Addendum-Page 1
MECHANICAL DATA
MTSS005D JANUARY 1995 REVISED MARCH 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DBB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040212 / E 03/02
80 PINS SHOWN
0,25
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,45
Seating Plane
100
20,90
20,70
41
0,23
0,13
40
A
80
1
0,15
80
DIM
A MAX
A MIN
PINS**
1,20 MAX
17,10
16,90
0,08
0,40
M
0,07
0
8
0,05
0,20
0,09
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC : 80 Pin MO-153 Variation FF
100 Pin MO-194 Variation BB
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Copyright
2005, Texas Instruments Incorporated
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