SN54ALVTH16245, SN74ALVTH16245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus
Design for
2.5-V and 3.3-V Operation and Low
Static-Power Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
CC
)
D
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
High Drive (32/64 mA at 3.3-V V
CC
)
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
D
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
description
The 'ALVTH16245 devices are 16-bit (dual-octal)
noninverting 3-state transceivers designed for
2.5-V or 3.3-V V
CC
operation, but with the
capability to provide a TTL interface to a 5-V
system environment.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively
isolated.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.2 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright
2002, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
SN54ALVTH16245 . . . WD PACKAGE
SN74ALVTH16245 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
1OE
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V
CC
2A5
2A6
GND
2A7
2A8
2OE
SN54ALVTH16245, SN74ALVTH16245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
terminal assignments
1
2
3
4
5
6
A
1DIR
NC
NC
NC
NC
1OE
B
1B2
1B1
GND
GND
1A1
1A2
C
1B4
1B3
VCC
VCC
1A3
1A4
D
1B6
1B5
GND
GND
1A5
1A6
E
1B8
1B7
1A7
1A8
F
2B1
2B2
2A2
2A1
G
2B3
2B4
GND
GND
2A4
2A3
H
2B5
2B6
VCC
VCC
2A6
2A5
J
2B7
2B8
GND
GND
2A8
2A7
K
2DIR
NC
NC
NC
NC
2OE
NC No internal connection
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP DL
Tape and reel
SN74ALVTH16245DLR
ALVTH16245
40
C to 85
C
TSSOP DGG
Tape and reel
SN74ALVTH16245GR
ALVTH16245
40
C to 85
C
TVSOP DGV
Tape and reel
SN74ALVTH16245VR
VT245
VFBGA GQL
Tape and reel
SN74ALVTH16245QR
55
C to 125
C
CFP WD
Tube
SNJ54ALVTH16245WD
SNJ54ALVTH16245WD
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
SN74ALVTH16245 . . . GQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
K
SN54ALVTH16245, SN74ALVTH16245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13
Pin numbers shown are for the DGG, DGV, DL, and WD packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
(see Note 1)
0.5 V to 7 V
. . . . . . . . .
Output current in the low state, I
O
: SN54ALVTH16245 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALVTH16245 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current in the high state, I
O
: SN54ALVTH16245
48 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALVTH16245
64 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DGG package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
63
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL package
42
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54ALVTH16245, SN74ALVTH16245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions, V
CC
= 2.5 V
0.2 V (see Note 3)
SN54ALVTH16245
SN74ALVTH16245
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VCC
Supply voltage
2.3
2.7
2.3
2.7
V
VIH
High-level input voltage
1.7
1.7
V
VIL
Low-level input voltage
0.7
0.7
V
VI
Input voltage
0
VCC
5.5
0
VCC
5.5
V
IOH
High-level output current
6
8
mA
IOL
Low-level output current
6
8
mA
IOL
Low-level output current; current duty cycle
50%; f
1 kHz
18
24
mA
t/
v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions, V
CC
= 3.3 V
0.3 V (see Note 3)
SN54ALVTH16245
SN74ALVTH16245
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VCC
Supply voltage
3
3.6
3
3.6
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
5.5
0
VCC
5.5
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
24
32
mA
IOL
Low-level output current; current duty cycle
50%; f
1 kHz
48
64
mA
t/
v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH16245, SN74ALVTH16245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
V
CC
= 2.5 V
0.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALVTH16245
SN74ALVTH16245
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 2.3 V,
II = 18 mA
1.2
1.2
V
VCC = 2.3 V to 2.7 V,
IOH = 100
A
VCC0.2
VCC0.2
VOH
VCC = 2 3 V
IOH = 6 mA
1.8
V
VCC = 2.3 V
IOH = 8 mA
1.8
VCC = 2.3 V to 2.7 V,
IOL = 100
A
0.2
0.2
IOL = 6 mA
0.4
VOL
VCC = 2 3 V
IOL = 8 mA
0.4
V
VCC = 2.3 V
IOL = 18 mA
0.5
IOL = 24 mA
0.5
Control inputs
VCC = 2.7 V,
VI = VCC or GND
1
1
Control inputs
VCC = 0 or 2.7 V,
VI = 5.5 V
10
10
II
VI = 5.5 V
20
20
A
A or B ports
VCC = 2.7 V
VI = VCC
1
1
VI = 0
5
5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
100
A
IBHL
VCC = 2.3 V,
VI = 0.7 V
115
115
A
IBHH
VCC = 2.3 V,
VI = 1.7 V
10
10
A
IBHLO
VCC = 2.7 V,
VI = 0 to VCC
300
300
A
IBHHO#
VCC = 2.7 V,
VI = 0 to VCC
300
300
A
IEX||
VCC = 2.3 V,
VO = 5.5 V
125
125
A
IOZ(PU/PD)
k
VCC
1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don't care
100
100
A
VCC = 2.7 V,
Outputs high
0.04
0.1
0.04
0.1
ICC
VCC = 2.7 V,
IO = 0,
Outputs low
2.3
4.5
2.3
4.5
mA
VI = VCC or GND
Outputs disabled
0.04
0.1
0.04
0.1
Ci
VCC = 2.5 V,
VI = 2.5 V or 0
3.5
3.5
pF
Cio
VCC = 2.5 V,
VO = 2.5 V or 0
8
8
pF
All typical values are at VCC = 2.5 V, TA = 25
C.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| Current into an output in the high state when VO > VCC
k
High-impedance state during power up or power down
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH16245, SN74ALVTH16245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALVTH16245
SN74ALVTH16245
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 3 V,
II = 18 mA
1.2
1.2
V
VCC = 3 V to 3.6 V,
IOH = 100
A
VCC0.2
VCC0.2
VOH
VCC = 3 V
IOH = 24 mA
2
V
VCC = 3 V
IOH = 32 mA
2
VCC = 3 V to 3.6 V,
IOL = 100
A
0.2
0.2
IOL = 16 mA
0.4
VOL
IOL = 24 mA
0.5
V
VOL
VCC = 3 V
IOL = 32 mA
0.5
V
IOL = 48 mA
0.55
IOL = 64 mA
0.55
Control inputs
VCC = 3.6 V,
VI = VCC or GND
1
1
Control inputs
VCC = 0 or 3.6 V,
VI = 5.5 V
10
10
II
VI = 5.5 V
20
20
A
A or B ports
VCC = 3.6 V
VI = VCC
1
1
VI = 0
5
5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
100
A
IBHL
VCC = 3 V,
VI = 0.8 V
75
75
A
IBHH
VCC = 3 V,
VI = 2 V
75
75
A
IBHLO
VCC = 3.6 V,
VI = 0 to VCC
500
500
A
IBHHO#
VCC = 3.6 V,
VI = 0 to VCC
500
500
A
IEX||
VCC = 3 V,
VO = 5.5 V
125
125
A
IOZ(PU/PD)
k
VCC
1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don't care
100
100
A
VCC = 3.6 V,
Outputs high
0.07
0.1
0.07
0.1
ICC
VCC = 3.6 V,
IO = 0,
Outputs low
3.2
5
3.2
5
mA
VI = VCC or GND
Outputs disabled
0.07
0.1
0.07
0.1
ICC
h
VCC = 3 V to 3.6 V, One input at VCC 0.6 V,
Other inputs at VCC or GND
0.2
0.2
mA
Ci
VCC = 3.3 V,
VI = 3.3 V or 0
3.5
3.5
pF
Cio
VCC = 3.3 V,
VO = 3.3 V or 0
8
8
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| Current into an output in the high state when VO > VCC
k
High-impedance state during power up or power down
h
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH16245, SN74ALVTH16245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 30 pF,
V
CC
= 2.5 V
0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
SN54ALVTH16245
SN74ALVTH16245
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
tPLH
A or B
B or A
0.5
3.6
0.5
3.6
ns
tPHL
A or B
B or A
0.5
3.4
0.5
3.4
ns
tPZH
OE
A or B
1.5
4.9
1.5
4.9
ns
tPZL
OE
A or B
1
4
1
4
ns
tPHZ
OE
A or B
1.5
4.9
1.5
4.9
ns
tPLZ
OE
A or B
1
4.2
1
4.2
ns
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
SN54ALVTH16245
SN74ALVTH16245
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
tPLH
A or B
B or A
0.5
3.1
0.5
3.1
ns
tPHL
A or B
B or A
0.5
2.9
0.5
2.9
ns
tPZH
OE
A or B
1
4.2
1
4.2
ns
tPZL
OE
A or B
1
3.5
1
3.5
ns
tPHZ
OE
A or B
1.5
5.3
1.5
5.3
ns
tPLZ
OE
A or B
1.5
5
1.5
5
ns
skew
t
ps
(pin or transition skew), t
ps
= |t
PHL
t
PHL
|
VCC = 2.5 V VCC = 3.3 V
UNIT
TYP
TYP
UNIT
tpsmax
438
118
ps
t
OST
=
|t
p
m
t
p
n
|, where
is any edge transition (high to low or low to high) measured between any two
outputs (m or n) within any given device (see Note 4)
VCC = 2.5 V VCC = 3.3 V
UNIT
TYP
TYP
UNIT
tOST
AB
227
248
ps
tOST
BA
223
243
ps
NOTE 4: One output switching, TA = 25
C
t
OSHL
/t
OSLH
(common edge skew), t
OSHL
= |t
PHL
max t
PHL
min| (output skew for low-to-high transitions), and
t
OSLH
= |t
PLH
max t
PLH
min| (output skew for high-to-low transitions) (see Note 4)
VCC = 2.5 V VCC = 3.3 V
UNIT
TYP
TYP
UNIT
tOSLH
A B
210
145
ps
tOSHL
AB
243
351
ps
tOSLH
B A
207
136
ps
tOSHL
BA
238
350
ps
NOTE 4: One output switching, TA = 25
C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH16245, SN74ALVTH16245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES066G JUNE 1996 REVISED APRIL 2002
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC/2
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
2
VCC
Open
GND
RL
RL
Data Input
Timing Input
VCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
Input
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V
VOH V
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2 ns, tf
2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC
VCC/2
VCC/2
2.5 V
0.2 V
3.3 V
0.3 V
500
500
VCC
RL
0.15 V
0.3 V
V
CL
30 pF
50 pF
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74ALVTH16245GRE4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ALVTH16245VRE4
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ALVTH16245ZQLR
ACTIVE
VFBGA
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SN74ALVTH16245DL
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVTH16245DLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVTH16245GR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVTH16245KR
ACTIVE
VFBGA
GQL
56
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74ALVTH16245VR
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2005
Addendum-Page 1
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50
4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
1
12
24
13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
38
24
16
4,90
5,10
3,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins MO-153
14/16/20/56 Pins MO-194
MECHANICAL DATA
MSSO001C JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040048 / E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
48
28
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0
8
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040078 / F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0
8
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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