SN54ALVTH32374, SN74ALVTH32374
2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES280 SEPTEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
State-of-the-Art Advanced BiCMOS
Technology (ABT)
Widebus
TM
Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
CC
)
D
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
High Drive (24/24 mA at 2.5-V V
CC
and
32/64 mA at 3.3-V V
CC
)
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
NOTE: For tape and reel order entry:
The GKER package is abbreviated to KR.
D
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
CC
+ 0.5 V
D
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
ESD Protection Exceeds JESD-22
2000-V Human-Body Model
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
(A114-A)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Packaged in Plastic Fine-Pitch Ball Grid
Array Package
description
The 'ALVTH32374 devices are 32-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V
or 3.3-V) V
CC
operation, but with the capability to provide a TTL interface to a 5-V system environment. These
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.
These devices can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive
transition of the clock (CLK), the Q outputs of the flip-flops take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
When V
CC
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the device when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH32374 is characterized for operation over the full military temperature range of 55
C to
125
C. The SN74ALVTH32374 is characterized for operation from 40
C to 85
C.
Copyright
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
SN54ALVTH32374, SN74ALVTH32374
2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES280 SEPTEMBER 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE
CLK
D
Q
L
H
H
L
L
L
L
H or L
X
Q0
H
X
X
Z
terminal assignments
1
2
3
4
5
6
A
1Q2
1Q1
1OE
1CLK
1D1
1D2
B
1Q4
1Q3
GND
GND
1D3
1D4
C
1Q6
1Q5
1VCC
1VCC
1D5
1D6
D
1Q8
1Q7
GND
GND
1D7
1D8
E
2Q2
2Q1
GND
GND
2D1
2D2
F
2Q4
2Q3
1VCC
1VCC
2D3
2D4
G
2Q6
2Q5
GND
GND
2D5
2D6
H
2Q7
2Q8
2OE
2CLK
2D8
2D7
J
3Q2
3Q1
3OE
3CLK
3D1
3D2
K
3Q4
3Q3
GND
GND
3D3
3D4
L
3Q6
3Q5
2VCC
2VCC
3D5
3D6
M
3Q8
3Q7
GND
GND
3D7
3D8
N
4Q2
4Q1
GND
GND
4D1
4D2
P
4Q4
4Q3
2VCC
2VCC
4D3
4D4
R
4Q6
4Q5
GND
GND
4D5
4D6
T
4Q7
4Q8
4OE
4CLK
4D8
4D7
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
SN54ALVTH32374, SN74ALVTH32374
2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES280 SEPTEMBER 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1CLK
1D1
To Seven Other Channels
1Q1
C1
1D
A3
A4
A5
A2
2OE
2CLK
2D1
To Seven Other Channels
2Q1
C1
1D
H3
H4
E5
E2
3OE
3CLK
3D1
To Seven Other Channels
3Q1
C1
1D
J3
J4
J5
J2
4OE
4CLK
4D1
To Seven Other Channels
4Q1
C1
1D
T3
T4
N5
N2
NOTE A: 1VCC is associated with these channels.
NOTE B: 2VCC is associated with these channels.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in
the high-impedance or power-off state, V
O
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . .
Output current in the low state, I
O
: SN54ALVTH32374 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALVTH32374 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current in the high state, I
O
: SN54ALVTH32374 48
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALVTH32374 64
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2)
40
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
SN54ALVTH32374, SN74ALVTH32374
2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES280 SEPTEMBER 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions, V
CC
= 2.5 V
0.2 V (see Note 3)
SN54ALVTH32374
SN74ALVTH32374
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VCC
Supply voltage
2.3
2.7
2.3
2.7
V
VIH
High-level input voltage
1.7
1.7
V
VIL
Low-level input voltage
0.7
0.7
V
VI
Input voltage
0
VCC
5.5
0
VCC
5.5
V
IOH
High-level output current
6
8
mA
IOL
Low-level output current
6
8
mA
IOL
Low-level output current; current duty cycle
50%; f
1 kHz
18
24
mA
t/
v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions, V
CC
= 3.3 V
0.3 V (see Note 3)
SN54ALVTH32374
SN74ALVTH32374
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VCC
Supply voltage
3
3.6
3
3.6
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
0
VCC
5.5
0
VCC
5.5
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
24
32
mA
IOL
Low-level output current; current duty cycle
50%; f
1 kHz
48
64
mA
t/
v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH32374, SN74ALVTH32374
2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES280 SEPTEMBER 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
V
CC
= 2.5 V
0.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALVTH32374
SN74ALVTH32374
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 2.3 V,
II = 18 mA
1.2
1.2
V
VCC = 2.3 V to 2.7 V,
IOH = 100
A
VCC0.2
VCC0.2
VOH
VCC = 2 3 V
IOH = 6 mA
1.8
V
VCC = 2.3 V
IOH = 8 mA
1.8
VCC = 2.3 V to 2.7 V,
IOL = 100
A
0.2
0.2
IOL = 6 mA
0.4
VOL
VCC = 2 3 V
IOL = 8 mA
0.4
V
VCC = 2.3 V
IOL = 18 mA
0.5
IOL = 24 mA
0.5
Control inputs
VCC = 2.7 V,
VI = VCC or GND
1
1
Control inputs
VCC = 0 or 2.7 V,
VI = 5.5 V
10
10
II
VI = 5.5 V
10
10
A
Data inputs
VCC = 2.7 V
VI = VCC
1
1
VI = 0
5
5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
100
A
IBHL
VCC = 2.3 V,
VI = 0.7 V
115
115
A
IBHH
VCC = 2.3 V,
VI = 1.7 V
10
10
A
IBHLO
VCC = 2.7 V,
VI = 0 to VCC
300
300
A
IBHHO#
VCC = 2.7 V,
VI = 0 to VCC
300
300
A
IEX||
VCC = 2.3 V,
VO = 5.5 V
125
125
A
IOZ(PU/PD)
k
VCC
1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don't care
100
100
A
IOZH
VCC = 2.7 V
VO = 2.3 V,
VI = 0.7 V or 1.7 V
5
5
A
IOZL
VCC = 2.7 V
VO = 0.5 V,
VI = 0.7 V or 1.7 V
5
5
A
VCC = 2.7 V,
Outputs high
0.04
0.1
0.04
0.1
ICC
VCC = 2.7 V,
IO = 0,
Outputs low
2.3
4.5
2.3
4.5
mA
VI = VCC or GND
Outputs disabled
0.04
0.1
0.04
0.1
Ci
VCC = 2.5 V,
VI = 2.5 V or 0
3.5
3.5
pF
Co
VCC = 2.5 V,
VO = 2.5 V or 0
6
6
pF
All typical values are at VCC = 2.5 V, TA = 25
C.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| Current into an output in the high state when VO > VCC
k
High-impedance state during power up or power down
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH32374, SN74ALVTH32374
2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES280 SEPTEMBER 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
0.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN54ALVTH32374
SN74ALVTH32374
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 3 V,
II = 18 mA
1.2
1.2
V
VCC = 3 V to 3.6 V,
IOH = 100
A
VCC0.2
VCC0.2
VOH
VCC = 3 V
IOH = 24 mA
2
V
VCC = 3 V
IOH = 32 mA
2
VCC = 3 V to 3.6 V,
IOL = 100
A
0.2
0.2
IOL = 16 mA
0.4
VOL
IOL = 24 mA
0.5
V
VOL
VCC = 3 V
IOL = 32 mA
0.5
V
IOL = 48 mA
0.55
IOL = 64 mA
0.55
Control inputs
VCC = 3.6 V,
VI = VCC or GND
1
1
Control inputs
VCC = 0 or 3.6 V,
VI = 5.5 V
10
10
II
VI = 5.5 V
10
10
A
Data inputs
VCC = 3.6 V
VI = VCC
1
1
VI = 0
5
5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
100
A
IBHL
VCC = 3 V,
VI = 0.8 V
75
75
A
IBHH
VCC = 3 V,
VI = 2 V
75
75
A
IBHLO
VCC = 3.6 V,
VI = 0 to VCC
500
500
A
IBHHO#
VCC = 3.6 V,
VI = 0 to VCC
500
500
A
IEX||
VCC = 3 V,
VO = 5.5 V
125
125
A
IOZ(PU/PD)
k
VCC
1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don't care
100
100
A
IOZH
VCC = 3.6 V
VO = 3 V,
VI = 0.8 V or 2 V
5
5
A
IOZL
VCC = 3.6 V
VO = 0.5 V,
VI = 0.8 V or 2 V
5
5
A
VCC = 3.6 V,
Outputs high
0.07
0.1
0.07
0.1
ICC
VCC = 3.6 V,
IO = 0,
Outputs low
3.2
5
3.2
5
mA
VI = VCC or GND
Outputs disabled
0.07
0.1
0.07
0.1
ICC
h
VCC = 3 V to 3.6 V, One input at VCC 0.6 V,
Other inputs at VCC or GND
0.4
0.4
mA
Ci
VCC = 3.3 V,
VI = 3.3 V or 0
3.5
3.5
pF
Co
VCC = 3.3 V,
VO = 3.3 V or 0
6
6
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
|| Current into an output in the high state when VO > VCC
k
High-impedance state during power up or power down
h
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH32374, SN74ALVTH32374
2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES280 SEPTEMBER 1999
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 2.5 V
0.2 V
(unless otherwise noted) (see Figure 1)
SN54ALVTH32374
SN74ALVTH32374
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
150
150
MHz
tw
Pulse duration, CLK high or low
1.5
1.5
ns
t
Setup time data before CLK
Data high
1.1
1
ns
tsu
Setup time, data before CLK
Data low
1.4
1.3
ns
th
Hold time data after CLK
Data high
0.6
0.5
ns
th
Hold time, data after CLK
Data low
0.9
0.8
ns
timing requirements over recommended operating free-air temperature range, V
CC
= 3.3 V
0.3 V
(unless otherwise noted) (see Figure 2)
SN54ALVTH32374
SN74ALVTH32374
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
250
250
MHz
tw
Pulse duration, CLK high or low
1.5
1.5
ns
t
Setup time data before CLK
Data high
1.1
1
ns
tsu
Setup time, data before CLK
Data low
1.6
1.5
ns
th
Hold time data after CLK
Data high
0.6
0.5
ns
th
Hold time, data after CLK
Data low
1.1
1
ns
switching characteristics over recommended operating free-air temperature range, C
L
= 30 pF,
V
CC
= 2.5 V
0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
SN54ALVTH32374
SN74ALVTH32374
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
fmax
150
150
MHz
tPLH
CLK
Q
1.4
3.9
1.5
3.8
ns
tPHL
CLK
Q
1.4
3.9
1.5
3.8
ns
tPZH
OE
Q
1
4.2
1
4.1
ns
tPZL
OE
Q
1
3.8
1
3.7
ns
tPHZ
OE
Q
1.7
4.3
1.8
4.2
ns
tPLZ
OE
Q
1
3.5
1
3.4
ns
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF,
V
CC
= 3.3 V
0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
TO
SN54ALVTH32374
SN74ALVTH32374
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
fmax
250
250
MHz
tPLH
CLK
Q
1
3.4
1
3.2
ns
tPHL
CLK
Q
1
3.3
1
3.2
ns
tPZH
OE
Q
1
3.9
1
3.8
ns
tPZL
OE
Q
1
3.4
1
3.3
ns
tPHZ
OE
Q
1
4.7
1
4.6
ns
tPLZ
OE
Q
1
4.4
1
4.2
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
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SN54ALVTH32374, SN74ALVTH32374
2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES280 SEPTEMBER 1999
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V
0.2 V
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH 0.15 V
0 V
VCC
0 V
0 V
tw
VCC
VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2 ns, tf
2 ns.
D. The outputs are measured one at a time with one transition per measurement.
0 V
VCC
VCC/2
tPHL
VCC/2
VCC/2
VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
VCC/2
tPLH
2
VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
SN54ALVTH32374, SN74ALVTH32374
2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES280 SEPTEMBER 1999
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 3.3 V
0.3 V
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500
500
tPLH
tPHL
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH 0.3 V
0 V
3 V
0 V
0 V
tw
Input
3 V
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Timing
Input
Data
Input
Output
Input
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
0 V
3 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 2. Load Circuit and Voltage Waveforms
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