SN54ALS160B THRU SN54ALS163B, SN54AS160 THRU SN54AS163
SN74ALS160B THRU SN74ALS163B, SN74AS160 THRU SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS024A D2661, APRIL 1982 REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1986, Texas Instruments Incorporated
5BASIC
1
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable
Package Options include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
Dependable Texas Instruments Quality and
Reliability
description
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. The 'ALS160B,
'ALS162B, 'AS160, and 'AS162 are decade
counters, and the 'ALS161B, 'ALS163B, 'AS161,
and 'AS163 are 4-bit binary counters. Synchro-
nous operation is provided by having all flip-flops
clocked simultaneously so that the outputs
change coincident with each other when so
instructed by the count-enable inputs and internal
gating. This mode of operation eliminates the
output counting spikes that are normally asso-
ciated with asynchronous (ripple clock)
counters. A buffered clock input triggers the four
flip-flops on the rising (positive-going) edge of the
clock input waveform.
These counters are fully programmable; that is, they may be preset to any number between 0 and 9, or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs.
The clear function for the 'ALS160B, 'ALS161B, 'AS160, and 'AS161 is asynchronous and a low level at the clear
input sets all four of the flip-flop outputs low regardless of the levels of the clock, load, or enable inputs. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to the clear input to
synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry
output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the
ripple carry output. The ripple carry output (RCO) thus enabled will produce a high-level pulse while the count
is maximum (9 or 15 with Q
A
high). This high-level overflow ripple carry pulse can be used to enable successive
cascaded stages. Transitions at the ENP or ENT are allowed regardless of the level of the clock input.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function
of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting
the stable setup and hold times.
The SN54ALS160B through SN54ALS163B and SN54AS160 through SN54AS163 are characterized for
operation over the full military temperature range of 55
C to 125
C. The SN74ALS160B through
SN74ALS163B and SN74AS160 through SN74AS163 are characterized for operation from 0
C to 70
C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
SN54ALS', SN54AS' . . . J PACKAGE
SN74ALS', SN74AS' . . . D OR N PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Q
A
Q
B
NC
Q
C
Q
D
A
B
NC
C
D
SN54ALS', SN54AS' . . . FK PACKAGE
(TOP VIEW)
CLK
CLR
NC
LOAD
ENT
RCO
ENP
GND
NC
NCNo internal connection
V
CC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS160B, SN54ALS162B, SN54AS160, SN54AS162
SN74ALS160B, SN74ALS162B, SN74AS160, SN74AS162
SYNCHRONOUS 4-BIT BINARY COUNTERS
SDAS024A D2661, APRIL 1982 REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2
logic symbols
9
LOAD
CLR
1
ENT
10
ENP
7
CLK
2
A
3
B
4
C
5
D
6
CTRDIV10
3CT = 9
15
RCO
QA
14
QB
13
QC
12
QD
11
5CT=0
M1
M2
G3
G4
C5/2,3,4+
1,5D
[1]
[2]
[4]
[8]
[8]
[4]
[2]
[1]
1,5D
C5/2,3,4+
G4
G3
M2
M1
CT=0
11
QD
12
QC
13
QB
14
QA
RCO
15
3CT = 9
CTRDIV10
6
D
5
C
4
B
3
A
2
CLK
7
ENP
10
ENT
1
CLR
LOAD
9
'ALS160B AND 'AS160 BINARY
COUNTERS WITH DIRECT CLEAR
'ALS162B AND 'AS162 BINARY
COUNTERS WITH SYNCHRONOUS CLEAR
'ALS160B and 'AS160 logic diagram (positive logic)
6
D
C
5
4
B
11
QD
R
1D
C1
12
QC
R
1D
C1
C1
1D
R
R
15
RCO
QA
14
QB
13
9
LOAD
CLR
1
ENT
10
ENP
7
CLK
2
A
3
1D
C1
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
'ALS162B and 'AS162 decade counters are similar; however the clear is synchronous as shown for the 'ALS163B and 'AS163 binary counters.
SN54ALS161B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT BINARY COUNTERS
SDAS024A D2661, APRIL 1982 REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
logic symbols
9
LOAD
CLR
1
ENT
10
ENP
7
CLK
2
A
3
B
4
C
5
D
6
CTRDIV16
3CT = 15
15
RCO
QA
14
QB
13
QC
12
QD
11
5CT=0
M1
M2
G3
G4
C5/2,3,4+
1,5D [1]
[2]
[4]
[8]
[8]
[4]
[2]
[1]
1,5D
C5/2,3,4+
G4
G3
M2
M1
CT=0
11
QD
12
QC
13
QB
14
QA
RCO
15
3CT = 15
CTRDIV16
6
D
5
C
4
B
3
A
2
CLK
7
ENP
10
ENT
1
CLR
LOAD
9
'ALS161B AND 'AS161 BINARY
COUNTERS WITH DIRECT CLEAR
'ALS163B AND 'AS163 BINARY
COUNTERS WITH SYNCHRONOUS CLEAR
'ALS163B and 'AS163 logic diagram (positive logic)
10
6
D
C
5
4
B
11
QD
1D
C1
12
QC
1D
C1
C1
1D
15
RCO
QA
14
QB
13
9
LOAD
CLR
1
ENT
ENP
7
CLK
2
A
3
1D
C1
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
'ALS161B and 'AS161 synchronous binary counters are similar; however the clear is asynchronous as shown for the 'ALS160B and 'AS160 decade
counters.
SN54ALS160B, SN54ALS162B, SN54AS160, SN54AS162
SN74ALS160B, SN74ALS162B, SN74AS160, SN74AS162
SYNCHRONOUS 4-BIT DECADE COUNTERS
SDAS024A D2661, APRIL 1982 REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
typical clear, preset, count, and inhibit sequences
0
Async
Clear
3
2
1
9
8
7
Preset
Sync
Clear
Outputs
Data
Inputs
RCO
QD
QC
QB
QA
ENT
ENP
CLK
D
C
B
A
LOAD
CLR
Inhibit
Count
'ALS160B, 'AS160, 'ALS162B, 'AS162
Illustrated below is the following sequence:
1. Clear outputs to zero ('ALS160B and 'AS160 are asynchronous; 'ALS162B and 'AS1162 are synchronous)
2. Preset to BCD seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit
SN54ALS161B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT BINARY COUNTERS
SDAS024A D2661, APRIL 1982 REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
typical clear, preset, count, and inhibit sequences
0
3
2
1
14
13
12
Outputs
Data
Inputs
RCO
QD
QC
QB
QA
ENT
ENP
CLK
D
C
B
A
LOAD
CLR
'ALS161B, 'AS161, 'ALS163B, 'AS163
Illustrated below is the following sequence:
1. Clear outputs to zero ('ALS161B and 'AS161 are asynchronous; 'ALS163B and 'AS163 are synchronous)
2. Preset to binary twelve
3. Count to thirteen, fourteen, fiften, zero, one, and two
4. Inhibit
Async
Clear
Preset
Sync
Clear
Inhibit
Count
Setup time
before CLK
ns
tw
Pulse duration
ENP, ENT
'ALS162B, 'ALS163B
UNIT
UNIT
VOL
V
TEST CONDITIONS
PARAMETER
SN54ALS160B THRU SN54ALS163B
SN74ALS160B THRU SN74ALS163B
SYNCHRONOUS 4-BIT DECADE COUNTERS
SDAS024A D2661, APRIL 1982 REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
6
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range:
SN54ALS160B thru SN54ALS163B
55
C to 125
C
. . . . . . . . . . .
SN74ALS160B thru SN74ALS163B
0
C to 70
C
. . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
SN54ALS160B
THRU
SN54ALS163B
SN74ALS160B
THRU
SN74ALS163B
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.7
0.8
V
IOH
High-level output current
0.4
0.4
mA
IOL
Low-level output current
4
8
mA
fclock
Clock frequency
0
22
0
40
MHz
CLR high or low
20
12.5
'ALS160B, 'ALS161B CLR low
20
15
A, B, C, D
50
15
LOAD
20
15
'ALS160B, 'ALS161B
25
15
tsu
'ALS162B, 'ALS163B
20
15
ns
'ALS160B, 'ALS161B
CLR inactive
10
10
CLR low
20
15
CLR high (inactive)
10
10
th
Hold time, all synchronous inputs after CLK
0
0
ns
TA
Operating free-air temperature
55
125
0
70
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS160B
THRU
SN54ALS163B
SN74ALS160B
THRU
SN74ALS163B
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = 4.5 V,
II = 18 mA
1.5
1.5
V
VOH
VCC = 4.5 V to 5.5 V,
IOH = 0.4 mA
VCC 2
VCC 2
V
VCC = 4.5 V,
IOL = 4 mA
0.25
0.4
0.25
0.4
VCC = 4.5 V,
IOL = 8 mA
0.35
0.5
II
VCC = 5.5 V,
VI = 7 V
0.1
0.1
mA
IIH
VCC = 5.5 V,
VI = 2.7 V
20
20
A
IIL
VCC = 5.5 V,
VI = 0.4 V
0.2
0.2
mA
IO
VCC = 5.5 V,
VO = 2.25 V
30
112
30
112
mA
ICC
VCC = 5.5 V
12
21
12
21
mA
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
ns
Any Q
RCO
CLK
CLK
ENT
ns
ns
FROM
(INPUT)
TO
(OUTPUT)
RCO
ns
Any Q
RCO
CLK
CLK
ENT
ns
ns
FROM
(INPUT)
TO
(OUTPUT)
RCO
SN54ALS160B THRU SN54ALS163B
SN74ALS160B THRU SN74ALS163B
SYNCHRONOUS 4-BIT BINARY COUNTERS
SDAS024A D2661, APRIL 1982 REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
7
'ALS160B, 'ALS161B switching characteristics (see Note 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
PARAMETER
SN54ALS160B
SN54ALS161B
SN74ALS160B
SN74ALS161B
UNIT
MIN
MAX
MIN
MAX
fmax
22
40
MHz
tPLH
5
34
5
20
tPHL
5
27
5
20
tPLH
4
19
4
15
tPHL
6
25
6
20
tPLH
3
18
3
13
tPHL
3
17
3
13
tPHL
CLR
Any Q
8
27
8
24
ns
tPHL
CLR
RCO
11
32
11
23
ns
'ALS162B, 'ALS163B switching characteristics (see Note 1)
PARAMETER
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
UNIT
SN54ALS162B
SN54ALS163B
SN74ALS162B
SN74ALS163B
MIN
MAX
MIN
MAX
fmax
35
40
MHz
tPLH
5
25
5
20
tPHL
5
25
5
20
tPLH
4
18
4
15
tPHL
6
25
6
20
tPLH
3
16
3
13
tPHL
3
16
3
13
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
Setup time
before CLK
ns
tw
Pulse duration
'ALS162, 'ALS163
UNIT
tsu
ns
UNIT
TEST CONDITIONS
PARAMETER
SN54AS160 THRU SN54AS163
SN74AS160 THRU SN74AS163
SYNCHRONOUS 4-BIT DECADE COUNTERS
SDAS024A D2661, APRIL 1982 REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range:
SN54AS160 thru SN54AS163
55
C to 125
C
. . . . . . . . . . . . . . . .
SN74AS160 thru SN74AS163
0
C to 70
C
. . . . . . . . . . . . . . . . . . . .
Storage temperature range
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
SN54AS160
THRU
SN54AS163
SN74AS160
THRU
SN74AS163
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
2
2
mA
IOL
Low-level output current
20
20
mA
fclock
Clock frequency
0
65
0
75
MHz
CLR high or low
7.7
6.7
'ALS160, 'ALS161 CLR low
10
8
A, B, C, D
10
8
LOAD
10
8
ENP, ENT
10
8
'ALS160, 'ALS161 CLR inactive
10
8
CLR low
14
12
CLR high (inactive)
10
9
th
Hold time, all synchronous inputs after CLK
2
0
ns
TA
Operating free-air temperature
55
125
0
70
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS160
THRU
SN54AS163
SN74AS160
THRU
SN74AS163
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = 4.5 V,
II = 18 mA
1.2
1.2
V
VOH
VCC = 4.5 V to 5.5 V,
IOH = 2 mA
VCC 2
VCC 2
V
VOL
VCC = 4.5 V,
IOL = 20 mA
0.25
0.5
0.25
0.5
V
LOAD
0.3
0.3
II
ENT
VCC = 5.5 V,
VI = 7 V
0.2
0.2
mA
All other
0.1
0.1
LOAD
60
60
IIH
ENT
VCC = 5.5 V,
VI = 2.7 V
40
40
A
All other
20
20
LOAD
1.5
1.5
IIL
ENT
VCC = 5.5 V,
VI = 0.4 V
1
1
mA
All other
0.5
0.5
IO
VCC = 5.5 V,
VO = 2.25 V
30
112
30
112
mA
ICC
VCC = 5.5 V
35
53
35
53
mA
All typical values are at VCC = 5 V, TA = 25
C.
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
RCO
ENT
ns
ns
CLK
Any Q
PARAMETER
UNIT
RCO
ENT
ns
ns
CLK
Any Q
FROM
(INPUT)
TO
(OUTPUT)
SN54AS160 THRU SN54AS163
SN74AS160 THRU SN74AS163
SYNCHRONOUS 4-BIT BINARY COUNTERS
SDAS024A D2661, APRIL 1982 REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
9
'AS160, 'AS161 switching characteristics (see Note 1)
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
SN54AS160
SN54AS161
SN74AS160
SN74AS161
MIN
MAX
MIN
MAX
fmax
65
75
MHz
tPHL
RCO
2
14
2
12.5
tPLH
CLK
RCO (with LOAD high)
1
8.5
1
8
ns
tPLH
RCO (with LOAD low)
3
17.5
3
16.5
tPLH
1
7.5
1
7
tPHL
2
14
2
13
tPLH
1.5
10
1.5
9
tPHL
1
9.5
1
8.5
tPHL
CLR
Any Q
2
14
2
13
ns
tPHL
CLR
RCO
2
14
2
12.5
ns
'AS162, 'AS163 switching characteristics (see Note 1)
PARAMETER
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500
,
TA = MIN to MAX
UNIT
SN54AS162
SN54AS163
SN74AS162
SN74AS163
MIN
MAX
MIN
MAX
fmax
65
75
MHz
tPHL
RCO
2
14
2
12.5
tPLH
CLK
RCO (with LOAD high)
1
8.5
1
8
ns
tPLH
RCO (with LOAD low)
3
17.5
3
16.5
tPLH
1
7.5
1
7
tPHL
2
14
2
13
tPLH
1.5
10
1.5
9
tPHL
1
9.5
1
8.5
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
SN54ALS160B THRU SN54ALS163B, SN54AS160 THRU SN54AS163
SN74ALS160B THRU SN74ALS163B, SN74AS160 THRU SN74AS163
SYNCHRONOUS 4-BIT DECADE COUNTERS
SDAS024A D2661, APRIL 1982 REVISED MAY 1986
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
10
APPLICATION INFORMATION
Nbit synchronous counters
This application demonstrates how the ripple mode carry circuit (Figure 1) and the carry-look-ahead circuit
(Figure 2) can be used to implement a high-speed N-bit counter. The 'ALS160B, 'AS160, 'ALS162B, and 'AS162
will count in BCD and the 'ALS161B, 'AS161, 'ALS163B, and 'AS163 will count in binary. When additional stages
are added, the f
MAX
decreases in Figure 1 , but remains unchanged in Figure 2.
fMAX = 1/(CLK to RCO tPLH) + (ENP tsu)
fMAX = 1/(CLK to RCO tPLH) + (ENT to RCO tPLH) (N2) + (ENT tsu)
CLOCK
CLEAR (L)
COUNT (H)
DISABLE (L)
LOAD (L)
LOAD
CLR
ENT
ENP
CLK
A
B
C
CTR
3CT=MAX
QA
QB
QC
QD
CT=0
M1
G3
G4
C5/T,3,4+
1,5D
LSB
D
D
1,5D
C5/T,3,4+
G4
G3
M1
CT=0
QD
QC
QB
QA
3CT=MAX
CTR
C
B
A
CLK
ENP
ENT
CLR
LOAD
D
1,5D
C5/T,3,4+
G4
G3
M1
CT=0
QD
QC
QB
QA
3CT=MAX
CTR
C
B
A
CLK
ENP
ENT
CLR
LOAD
D
1,5D
C5/T,3,4+
G4
G3
M1
CT=0
QD
QC
QB
QA
RCO
3CT=MAX
CTR
C
B
A
CLK
ENP
ENT
CLR
LOAD
RCO
RCO
RCO
To More Significant Stages
CLOCK
DISABLE (L)
COUNT (H)
LOAD (L)
DISABLE (L)
COUNT (H)
CLEAR (L)
To More Significant Stages
RCO
RCO
RCO
LOAD
CLR
ENT
ENP
CLK
A
B
C
CTR
3CT=MAX
RCO
QA
QB
QC
QD
CT=0
M1
G3
G4
C5/T,3,4+
1,5D
D
LOAD
CLR
ENT
ENP
CLK
A
B
C
CTR
3CT=MAX
QA
QB
QC
QD
CT=0
M1
G3
G4
C5/T,3,4+
1,5D
D
LOAD
CLR
ENT
ENP
CLK
A
B
C
CTR
3CT=MAX
QA
QB
QC
QD
CT=0
M1
G3
G4
C5/T,3,4+
1,5D
D
D
LSB
1,5D
C5/T,3,4+
G4
G3
M1
CT=0
QD
QC
QB
QA
3CT=MAX
CTR
C
B
A
CLK
ENP
ENT
CLR
LOAD
Figure 1. Ripple Mode Carry Circuit
Figure 2. Carry-Look-Ahesd Circuit
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER'S RISK.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI's publication of information regarding any third
party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright
1998, Texas Instruments Incorporated
PDF 
ZIP