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FEATURES
DESCRIPTION/ORDERING INFORMATION
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403D JULY 2002 REVISED JUNE 2005
Member of the Texas Instruments WidebusTM
Family
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
I
off
Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max t
pd
of 2 ns at 1.8 V
Low Power Consumption, 20-
A Max I
CC
8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)
This
16-bit
edge-triggered
D-type
flip-flop
is
operational at 0.8-V to 2.7-V V
CC
, but is designed
specifically for 1.65-V to 1.95-V V
CC
operation.
The
SN74AUC16374
is
particularly
suitable
for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. It can be used as
two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (CLK) input, the Q
outputs of the flip-flop take on the logic levels set up
at the data (D) inputs.
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TSSOP DGG
Tape and reel
SN74AUC16374DGGR
AUC16374
40C to 85C
TVSOP DGV
Tape and reel
SN74AUC16374DGVR
MH374
VFBGA GQL
(2)
Tape and reel
SN74AUC16374GQLR
MH374
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
Package preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 20022005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
1OE
1CLK
1D1
To Seven Other Channels
1Q1
2OE
2CLK
2D1
2Q1
To Seven Other Channels
1
48
47
24
25
36
C1
1D
13
2
C1
1D
Pin numbers shown are for the DGG and DGV packages.
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403D JULY 2002 REVISED JUNE 2005
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TERMINAL ASSIGNMENTS
(1)
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1CLK
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
V
CC
V
CC
1D3
1D4
D
1Q6
1Q5
GND
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
V
CC
V
CC
2D6
2D5
J
2Q7
2Q8
GND
GND
2D8
2D7
K
2OE
NC
NC
NC
NC
2CLK
(1)
NC - No internal connection
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OUTPUT
Q
OE
CLK
D
L
H
H
L
L
L
L
H or L
X
Q
0
H
X
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403D JULY 2002 REVISED JUNE 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CC
Supply voltage range
0.5
3.6
V
V
I
Input voltage range
(2)
0.5
3.6
V
V
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
0.5
3.6
V
V
O
Output voltage range
(2)
0.5
V
CC
+ 0.5
V
I
IK
Input clamp current
V
I
< 0
50
mA
I
OK
Output clamp current
V
O
< 0
50
mA
I
O
Continuous output current
20
mA
Continuous current through V
CC
or GND
100
mA
DGG package
70
JA
Package thermal impedance
(3)
DGV package
58
C/W
GQL package
42
T
stg
Storage temperature range
65
150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The package thermal impedance is calculated in accordance with JESD 51-7.
MIN
MAX
UNIT
V
CC
Supply voltage
0.8
2.7
V
V
CC
= 0.8 V
V
CC
V
IH
High-level input voltage
V
CC
= 1.1 V to 1.95 V
0.65 V
CC
V
V
CC
= 2.3 V to 2.7 V
1.7
V
CC
= 0.8 V
0
V
IL
Low-level input voltage
V
CC
= 1.1 V to 1.95 V
0.35 V
CC
V
V
CC
= 2.3 V to 2.7 V
0.7
V
I
Input voltage
0
3.6
V
V
O
Output voltage
0
V
CC
V
V
CC
= 0.8 V
0.7
V
CC
= 1.1 V
3
I
OH
High-level output current
V
CC
= 1.4 V
5
mA
V
CC
= 1.65 V
8
V
CC
= 2.3 V
9
V
CC
= 0.8 V
0.7
V
CC
= 1.1 V
3
I
OL
Low-level output current
V
CC
= 1.4 V
5
mA
V
CC
= 1.65 V
8
V
CC
= 2.3 V
9
t/
v
Input transition rise or fall rate
20
ns/V
T
A
Operating free-air temperature
40
85
C
(1)
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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Electrical Characteristics
Timing Requirements
Switching Characteristics
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403D JULY 2002 REVISED JUNE 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
(1)
MAX
UNIT
I
OH
= 100
A
0.8 V to 2.7 V
V
CC
0.1
I
OH
= 0.7 mA
0.8 V
0.55
I
OH
= 3 mA
1.1 V
0.8
V
OH
V
I
OH
= 5 mA
1.4 V
1
I
OH
= 8 mA
1.65 V
1.2
I
OH
= 9 mA
2.3 V
1.8
I
OL
= 100
A
0.8 V to 2.7 V
0.2
I
OL
= 0.7 mA
0.8 V
0.25
I
OL
= 3 mA
1.1 V
0.3
V
OL
V
I
OL
= 5 mA
1.4 V
0.4
I
OL
= 8 mA
1.65 V
0.45
I
OL
= 9 mA
2.3 V
0.6
I
I
All inputs
V
I
= V
CC
or GND
0 to 2.7 V
5
A
I
off
V
I
or V
O
= 2.7 V
0
10
A
I
OZ
V
O
= V
CC
or GND
2.7 V
10
A
I
CC
V
I
= V
CC
or GND,
I
O
= 0
0.8 V to 2.7 V
20
A
C
i
V
I
= V
CC
or GND
2.5 V
3
pF
C
o
V
O
= V
CC
or GND
2.5 V
5
pF
(1)
All typical values are at T
A
= 25C.
over recommended operating free-air temperature range (unless otherwise noted) (see
Figure 1
)
V
CC
= 1.2 V
V
CC
= 1.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 0.8 V
0.1 V
0.1 V
0.15 V
0.2 V
UNIT
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
clock
Clock frequency
85
250
250
250
250
MHz
t
w
Pulse duration, CLK high or low
5.9
1.9
1.9
1.9
1.9
ns
t
su
Setup time, data before CLK
1.4
1.2
0.7
0.6
0.6
ns
t
h
Hold time, data after CLK
0.1
0.4
0.4
0.4
0.4
ns
over recommended operating free-air temperature range (unless otherwise noted) (see
Figure 1
)
V
CC
= 1.2 V
V
CC
= 1.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 0.8 V
FROM
TO
0.1 V
0.1 V
0.15 V
0.2 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
TYP
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
f
max
85
250
250
250
250
MHz
t
pd
CLK
Q
7.3
1
4.5
0.8
2.9
0.7
1.5
2.8
0.7
2.2
ns
t
en
OE
Q
7
1.2
5.3
0.8
3.6
0.8
1.5
2.9
0.7
2.2
ns
t
dis
OE
Q
8.2
2
7.1
1
4.8
1.4
2.7
4.5
0.5
2.2
ns
4
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Operating Characteristics
(1)
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403D JULY 2002 REVISED JUNE 2005
T
A
= 25C
V
CC
= 0.8 V
V
CC
= 1.2 V
V
CC
= 1.5 V
V
CC
= 1.8 V
V
CC
= 2.5 V
TEST
PARAMETER
UNIT
CONDITIONS
TYP
TYP
TYP
TYP
TYP
1 f
data
= 5 MHz,
Outputs
C
pd
Power
1 f
clk
= 10 MHz,
enabled,
(each
dissipation
1 f
out
= 5 MHz,
24
24
24.1
26.2
31.2
pF
1 output
output)
(2)
capacitance
OE = GND,
switching
C
L
= 0 pF
Outputs
1 f
data
= 5 MHz,
disabled,
1 f
clk
= 10 MHz,
Power
1 clock
f
out
= not
C
pd(Z)
dissipation
7.5
7.5
8
9.4
13.2
pF
and 1
switching,
capacitance
data
OE = V
CC
,
switching
C
L
= 0 pF
1 f
data
= 0 MHz,
Outputs
1 f
clk
= 10 MHz,
C
pd
Power
disabled,
f
out
= not
(each
dissipation
clock
13.8
13.8
14
14.7
17.5
pF
switching,
clock)
(3)
capacitance
only
OE = V
CC
,
switching
C
L
= 0 pF
(1)
Total device C
pd
for multiple (n) outputs switching and (y) clocks inputs switching = {n * C
pd
(each output)} + {y * C
pd
(each clock)}
(2)
C
pd
(each output) is the C
pd
for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz
in this test, but its I
CC
component has been subtracted out).
(3)
C
pd
(each clock) is the C
pd
for the clock circuitry only as it operates at 10 MHz.
5
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PARAMETER MEASUREMENT INFORMATION
V
CC
/2
t
h
t
su
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
2
V
CC
Open
GND
R
L
R
L
Data Input
Timing Input
V
CC
0 V
V
CC
0 V
0 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
V
CC
0 V
Input
Output
Waveform 1
S1 at 2
V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
V
CC
0 V
V
OL
+ V
V
OH
- V
0 V
V
CC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
2
V
CC
GND
TEST
S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, Z
O
= 50
, slew rate
1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
V
CC
/2
V
CC
/2
0.8 V
1.2 V
0.1 V
1.5 V
0.1 V
1.8 V
0.15 V
2.5 V
0.2 V
2 k
2 k
2 k
1 k
500
V
CC
R
L
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
V
C
L
15 pF
15 pF
15 pF
30 pF
30 pF
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES403D JULY 2002 REVISED JUNE 2005
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74AUC16374DGGRE4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AUC16374DGVRE4
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUC16374DGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUC16374DGVR
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUC16374GQLR
ACTIVE
VFBGA
GQL
56
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74AUC16374ZQLR
ACTIVE
VFBGA
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2005
Addendum-Page 1
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50
4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
1
12
24
13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
38
24
16
4,90
5,10
3,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins MO-153
14/16/20/56 Pins MO-194
MECHANICAL DATA
MTSS003D JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040078 / F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0
8
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
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amplifier.ti.com
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www.ti.com/audio
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dsp.ti.com
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www.ti.com/broadband
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interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
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www.ti.com/security
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www.ti.com/telephony
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www.ti.com/video
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www.ti.com/wireless
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2005, Texas Instruments Incorporated
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