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FEATURES
DCT OR DCU PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
V
CCA
A1
A2
GND
V
CCB
B1
B2
DIR
4
3
2
1
5
6
7
8
GND
A2
A1
V
CCA
DIR
B2
B1
V
CCB
YEP OR YZP PACKAGE
(BOTTOM VIEW)
DESCRIPTION/ORDERING INFORMATION
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
Max Data Rates
Available in the Texas Instruments
500 Mbps (1.8-V to 3.3-V Translation)
NanoStarTM and NanoFreeTM Packages
320 Mbps (<1.8-V to 3.3-V Translation)
Control Inputs V
IH
/V
IL
Levels Are Referenced
320 Mbps (Translate to 2.5 V or 1.8 V)
to V
CCA
Voltage
180 Mbps (Translate to 1.5 V)
Fully Configurable Dual-Rail Design Allows
240 Mbps (Translate to 1.2 V)
Each Port to Operate Over the Full 1.2-V to
Latch-Up Performance Exceeds 100 mA Per
3.6-V Power-Supply Range
JESD 78, Class II
I/Os Are 4.6-V Tolerant
ESD Protection Exceeds JESD 22
I
off
Supports Partial-Power-Down Mode
2000-V Human-Body Model (A114-A)
Operation
200-V Machine Model (A115-A)
Bus Hold on Data Inputs Eliminates the Need
1000-V Charged-Device Model (C101)
for External Pullup/Pulldown Resistors
This
dual-bit
noninverting
bus
transceiver
uses
two
separate
configurable
power-supply
rails.
The
SN74AVCH2T45 is optimized to operate with V
CCA
/V
CCB
set at 1.4 V to 3.6 V. It is operational with V
CCA
/V
CCB
as
low as 1.2 V. The A port is designed to track V
CCA
. V
CCA
accepts any supply voltage from 1.2 V to 3.6 V. The B
port is designed to track V
CCB
. V
CCB
accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH2T45 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
(2)
NanoStarTM WCSP (DSBGA)
SN74AVCH2T45YEPR
(3)
0.23-mm Large Bump YEP
Tape and reel
NanoFreeTM WCSP (DSBGA)
SN74AVCH2T45YZPR
(3)
40
C to 85
C
0.23-mm Large Bump YZP (Pb-free)
SSOP DCT
Tape and reel
SN74AVCH2T45DCTR
ET2_ _ _
VSSOP DCU
Tape and reel
SN74AVCH2T45DCUR
ET2_
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2)
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
= Pb-free).
(3)
Package preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 20042005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
B1
DIR
5
7
A1
2
V
CCA
V
CCB
B2
6
A2
3
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
The SN74AVCH2T45 is designed so that the DIR input is powered by V
CCA
.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The V
CC
isolation feature ensures that if either V
CC
input is at GND, then both outputs are in the high-impedance
state. The bus-hold circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
FUNCTION TABLE
(EACH TRANSCEIVER)
INPUT
OPERATION
DIR
L
B data to A bus
H
A data to B bus
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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Absolute Maximum Ratings
(1)
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
CCA
Supply voltage range
0.5
4.6
V
V
CCB
I/O ports (A port)
0.5
4.6
V
I
Input voltage range
(2)
I/O ports (B port)
0.5
4.6
V
Control inputs
0.5
4.6
A port
0.5
4.6
Voltage range applied to any output
V
O
V
in the high-impedance or power-off state
(2)
B port
0.5
4.6
A port
0.5
V
CCA
+ 0.5
V
O
Voltage range applied to any output in the high or low state
(2) (3)
V
B port
0.5
V
CCB
+ 0.5
I
IK
Input clamp current
V
I
< 0
50
mA
I
OK
Output clamp current
V
O
< 0
50
mA
I
O
Continuous output current
50
mA
Continuous current through V
CCA
, V
CCB
, or GND
100
mA
DCT package
220
JA
Package thermal impedance
(4)
DCU package
227
C/W
YEP/YZP package
102
T
stg
Storage temperature range
65
150
C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
3
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Recommended Operating Conditions
(1) (2) (3) (4) (5)
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
V
CCI
V
CCO
MIN
MAX
UNIT
V
CCA
Supply voltage
1.2
3.6
V
V
CCB
Supply voltage
1.2
3.6
V
1.2 V to 1.95 V
V
CC
0.65
High-level
V
IH
Data inputs
(4)
1.95 V to 2.7 V
1.6
V
input voltage
2.7 V to 3.6 V
2
1.2 V to 1.95 V
V
CCI
0.35
Low-level
V
IL
Data inputs
(4)
1.95 V to 2.7 V
0.7
V
input voltage
2.7 V to 3.6 V
0.8
1.2 V to 1.95 V
V
CCA
0.65
High-level
DIR
V
IH
1.95 V to 2.7 V
1.6
V
input voltage
(referenced to V
CCA
)
(5)
2.7 V to 3.6 V
2
1.2 V to 1.95 V
V
CCA
0.35
Low-level
DIR
V
IL
1.95 V to 2.7 V
0.7
V
input voltage
(referenced to V
CCA
)
(5)
2.7 V to 3.6 V
0.8
V
I
Input voltage
0
3.6
V
Active state
0
V
CCO
V
O
Output voltage
V
3-state
0
3.6
1.2 V
3
1.4 V to 1.6 V
6
I
OH
High-level output current
1.65 V to 1.95 V
8
mA
2.3 V to 2.7 V
9
3 V to 3.6 V
12
1.2 V
3
1.4 V to 1.6 V
6
I
OL
Low-level output current
1.65 V to 1.95 V
8
mA
2.3 V to 2.7 V
9
3 V to 3.6 V
12
t/
v
Input transition rise or fall rate
5
ns/V
T
A
Operating free-air temperature
40
85
C
(1)
V
CCI
is the V
CC
associated with the data input port.
(2)
V
CCO
is the V
CC
associated with the output port.
(3)
All unused data inputs of the device must be held at V
CCI
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(4)
For V
CCI
values not specified in the data sheet, V
IH
min = V
CCI
0.7 V, V
IL
max = V
CCI
0.3 V.
(5)
For V
CCA
values not specified in the data sheet, V
IH
min = V
CCA
0.7 V, V
IL
max = V
CCA
0.3 V.
4
www.ti.com
Electrical Characteristics
(1) (2)
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
over recommended operating free-air temperature range (unless otherwise noted)
T
A
= 25
C
40
C to 85
C
PARAMETER
TEST CONDITIONS
V
CCA
V
CCB
UNIT
MIN
TYP
MAX
MIN MAX
I
OH
= 100
A
1.2 V to 3.6 V
1.2 V to 3.6 V
V
CCO
0.2 V
I
OH
= 3 mA
1.2 V
1.2 V
0.95
I
OH
= 6 mA
1.4 V
1.4 V
1.05
V
OH
V
I
= V
IH
V
I
OH
= 8 mA
1.65 V
1.65 V
1.2
I
OH
= 9 mA
2.3 V
2.3 V
1.75
I
OH
= 12 mA
3 V
3 V
2.3
I
OL
= 100
A
1.2 V to 3.6 V
1.2 V to 3.6 V
0.2
I
OL
= 3 mA
1.2 V
1.2 V
0.15
I
OL
= 6 mA
1.4 V
1.4 V
0.35
V
OL
V
I
= V
IL
V
I
OL
= 8 mA
1.65 V
1.65 V
0.45
I
OL
= 9 mA
2.3 V
2.3 V
0.55
I
OL
= 12 mA
3 V
3 V
0.7
I
I
DIR input
V
I
= V
CCA
or GND
1.2 V to 3.6 V
1.2 V to 3.6 V
0.025
0.25
1
A
V
I
= 0.42 V
1.2 V
1.2 V
25
V
I
= 0.49 V
1.4 V
1.4 V
15
I
BHL
(3)
V
I
= 0.58 V
1.65 V
1.65 V
25
A
V
I
= 0.7 V
2.3 V
2.3 V
45
V
I
= 0.8 V
3.3 V
3.3 V
100
V
I
= 0.78 V
1.2 V
1.2 V
25
V
I
= 0.91 V
1.4 V
1.4 V
15
I
BHH
(4)
V
I
= 1.07 V
1.65 V
1.65 V
25
A
V
I
= 1.6 V
2.3 V
2.3 V
45
V
I
= 2 V
3.3 V
3.3 V
100
1.2 V
1.2 V
50
1.6 V
1.6 V
125
I
BHLO
(5)
V
I
= 0 to V
CC
1.95 V
1.95 V
200
A
2.7 V
2.7 V
300
3.6 V
3.6 V
500
1.2 V
1.2 V
50
1.6 V
1.6 V
125
I
BHHO
(6)
V
I
= 0 to V
CC
1.95 V
1.95 V
200
A
2.7 V
2.7 V
300
3.6 V
3.6 V
500
(1)
V
CCO
is the V
CC
associated with the output port.
(2)
V
CCI
is the V
CC
associated with the input port.
(3)
The bus-hold circuit can sink at least the minimum low sustaining current at V
IL
max. I
BHL
should be measured after lowering V
IN
to GND
and then raising it to V
IL
max.
(4)
The bus-hold circuit can source at least the minimum high sustaining current at V
IH
min. I
BHH
should be measured after raising V
IN
to
V
CC
and then lowering it to V
IH
min.
(5)
An external driver must source at least I
BHLO
to switch this node from low to high.
(6)
An external driver must sink at least I
BHHO
to switch this node from high to low.
5
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Electrical Characteristics
(1) (2)
Switching Characteristics
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
over recommended operating free-air temperature range (unless otherwise noted) (continued)
T
A
= 25
C
40
C to 85
C
PARAMETER
TEST CONDITIONS
V
CCA
V
CCB
UNIT
MIN
TYP
MAX
MIN
MAX
A port
0 V
0 to 3.6 V
0.1
1
5
I
off
V
I
or V
O
= 0 to 3.6 V
A
B port
0 to 3.6 V
0 V
0.1
1
5
I
OZ
A or B port
V
O
= V
CCO
or GND
1.2 V to 3.6 V
1.2 V to 3.6 V
0.5
2.5
5
A
1.2 V to 3.6 V
1.2 V to 3.6 V
10
I
CCA
V
I
= V
CCI
or GND,
I
O
= 0
0 V
3.6 V
2
A
3.6 V
0 V
10
1.2 V to 3.6 V
1.2 V to 3.6 V
10
I
CCB
V
I
= V
CCI
or GND,
I
O
= 0
0 V
3.6 V
10
A
3.6 V
0 V
2
I
CCA
+ I
CCB
V
I
= V
CCI
or GND,
I
O
= 0
1.2 V to 3.6 V
1.2 V to 3.6 V
20
A
Control
C
i
V
I
= 3.3 V or GND
3.3 V
3.3 V
2.5
pF
inputs
C
io
A or B port
V
O
= 3.3 V or GND
3.3 V
3.3 V
6
pF
(1)
V
CCO
is the V
CC
associated with the output port.
(2)
V
CCI
is the V
CC
associated with the input port.
over recommended operating free-air temperature range, V
CCA
= 1.2 V (see
Figure 11
)
V
CCB
= 1.2 V
V
CCB
= 1.5 V
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
FROM
TO
PARAMETER
UNIT
(INPUT)
(OUTPUT)
TYP
TYP
TYP
TYP
TYP
t
PLH
3.1
2.6
2.4
2.2
2.2
A
B
ns
t
PHL
3.1
2.6
2.4
2.2
2.2
t
PLH
3.4
3.1
3
2.9
2.9
B
A
ns
t
PHL
3.4
3.1
3
2.9
2.9
t
PHZ
5.2
5.2
5.1
5
4.8
DIR
A
ns
t
PLZ
5.2
5.2
5.1
5
4.8
t
PHZ
5
4
3.8
2.8
3.2
DIR
B
ns
t
PLZ
5
4
3.8
2.8
3.2
t
PZH
(1)
8.4
7.1
6.8
5.7
6.1
DIR
A
ns
t
PZL
(1)
8.4
7.1
6.8
5.7
6.1
t
PZH
(1)
8.3
7.8
7.5
7.2
7
DIR
B
ns
t
PZL
(1)
8.3
7.8
7.5
7.2
7
(1)
The enable time is a calculated value derived using the formula shown in the enable times section.
6
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Switching Characteristics
Switching Characteristics
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
over recommended operating free-air temperature range, V
CCA
= 1.5 V
0.1 V (see
Figure 11
)
V
CCB
= 1.5 V
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.2 V
FROM
TO
0.1 V
0.15 V
0.2 V
0.3 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
PLH
2.8
0.7
5.4
0.5
4.6
0.4
3.7
0.3
3.5
A
B
ns
t
PHL
2.8
0.7
5.4
0.5
4.6
0.4
3.7
0.3
3.5
t
PLH
2.7
0.8
5.4
0.7
5.2
0.6
4.9
0.5
4.7
B
A
ns
t
PHL
2.7
0.8
5.4
0.7
5.2
0.6
4.9
0.5
4.7
t
PHZ
3.9
1.3
8.5
1.3
7.1
1.1
5.5
1.4
4.6
DIR
A
ns
t
PLZ
3.9
1.3
8.5
1.3
7.1
1.1
5.5
1.4
4.6
t
PHZ
4.7
1.1
7
1.4
6.9
1.2
6.9
1.7
7.1
DIR
B
ns
t
PLZ
4.7
1.1
7
1.4
6.9
1.2
6.9
1.7
7.1
t
PZH
(1)
7.4
12.4
12.1
11.8
11.8
DIR
A
ns
t
PZL
(1)
7.4
12.4
12.1
11.8
11.8
t
PZH
(1)
6.7
13.9
11.6
9.1
7.8
DIR
B
ns
t
PZL
(1)
6.7
13.9
11.6
9.1
7.8
(1)
The enable time is a calculated value derived using the formula shown in the enable times section.
over recommended operating free-air temperature range, V
CCA
= 1.8 V
0.15 V (see
Figure 11
)
V
CCB
= 1.5 V
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.2 V
FROM
TO
0.1 V
0.15 V
0.2 V
0.3 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
PLH
2.7
0.5
5.2
0.4
4.3
0.2
3.4
0.2
3.1
A
B
ns
t
PHL
2.7
0.5
5.2
0.4
4.3
0.2
3.4
0.2
3.1
t
PLH
2.4
0.7
4.7
0.5
4.4
0.5
4
0.4
3.8
B
A
ns
t
PHL
2.4
0.7
4.7
0.5
4.4
0.5
4
0.4
3.8
t
PHZ
3.7
1.3
8.1
0.7
6.9
1.4
5.3
1.1
4.5
DIR
A
ns
t
PLZ
3.7
1.3
8.1
0.7
6.9
1.4
5.3
1.1
4.5
t
PHZ
4.4
1.3
5.8
1.3
5.9
0.8
5.7
1.5
5.9
DIR
B
ns
t
PLZ
4.4
1.3
5.8
1.3
5.9
0.8
5.7
1.5
5.9
t
PZH
(1)
6.8
10.4
10.3
9.7
9.7
DIR
A
ns
t
PZL
(1)
6.8
10.4
10.3
9.7
9.7
t
PZH
(1)
6.4
13.3
11.2
8.6
7.4
DIR
B
ns
t
PZL
(1)
6.4
13.3
11.2
8.6
7.4
(1)
The enable time is a calculated value derived using the formula shown in the enable times section.
7
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Switching Characteristics
Switching Characteristics
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
over recommended operating free-air temperature range, V
CCA
= 2.5 V
0.2 V (see
Figure 11
)
V
CCB
= 1.5 V
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.2 V
FROM
TO
0.1 V
0.15 V
0.2 V
0.3 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
PLH
2.6
0.4
4.9
0.2
4
0.2
3
0.2
2.6
A
B
ns
t
PHL
2.6
0.4
4.9
0.2
4
0.2
3
0.2
2.6
t
PLH
2.1
0.6
3.8
0.5
3.4
0.4
3
0.3
2.8
B
A
ns
t
PHL
2.1
0.6
3.8
0.5
3.4
0.4
3
0.3
2.8
t
PHZ
2.4
0.7
7.9
0.8
6.4
0.8
5
0.5
4.3
DIR
A
ns
t
PLZ
2.4
0.7
7.9
0.8
6.4
0.8
5
0.5
4.3
t
PHZ
3.8
1
4.3
0.6
4.3
0.5
4.2
1.1
4.1
DIR
B
ns
t
PLZ
3.8
1
4.3
0.6
4.3
0.5
4.2
1.1
4.1
t
PZH
(1)
5.9
7.9
7.7
7.2
6.9
DIR
A
ns
t
PZL
(1)
5.9
7.9
7.7
7.2
6.9
t
PZH
(1)
5
12.8
10.4
7.9
6.8
DIR
B
ns
t
PZL
(1)
5
12.8
10.4
7.9
6.8
(1)
The enable time is a calculated value derived using the formula shown in the enable times section.
over recommended operating free-air temperature range, V
CCA
= 3.3 V
0.3 V (see
Figure 11
)
V
CCB
= 1.5 V
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.2 V
FROM
TO
0.1 V
0.15 V
0.2 V
0.3 V
PARAMETER
UNIT
(INPUT)
(OUTPUT)
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
PLH
2.5
0.3
4.7
0.2
3.8
0.2
2.8
0.2
2.4
A
B
ns
t
PHL
2.5
0.3
4.7
0.2
3.8
0.2
2.8
0.2
2.4
t
PLH
2.1
0.6
3.6
0.4
3.1
0.3
2.6
0.3
2.4
B
A
ns
t
PHL
2.1
0.6
3.6
0.4
3.1
0.3
2.6
0.3
2.4
t
PHZ
2.9
1.1
8
1
6.5
1.3
4.7
1.2
4
DIR
A
ns
t
PLZ
2.9
1.1
8
1
6.5
1.3
4.7
1.2
4
t
PHZ
3.4
0.5
6.6
0.3
5.6
0.3
4.6
1.1
3.5
DIR
B
ns
t
PLZ
3.4
0.5
6.6
0.3
5.6
0.3
4.6
1.1
3.5
t
PZH
(1)
5.5
6.9
6.6
6.2
5.9
DIR
A
ns
t
PZL
(1)
5.5
6.9
6.6
6.2
5.9
t
PZH
(1)
5.4
12.7
10.3
7.4
6.3
DIR
B
ns
t
PZL
(1)
5.4
12.7
10.3
7.4
6.3
(1)
The enable time is a calculated value derived using the formula shown in the enable times section.
8
www.ti.com
Operating Characteristics
POWER-UP CONSIDERATIONS
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
T
A
= 25
C
V
CCA
=
V
CCA
=
V
CCA
=
V
CCA
=
V
CCA
=
TEST
V
CCB
= 1.2 V
V
CCB
= 1.5 V
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
PARAMETER
UNIT
CONDITIONS
TYP
TYP
TYP
TYP
TYP
A-port input,
3
3
3
3
4
C
L
= 0,
B-port output
C
pdA
(1)
f = 10 MHz,
pF
B-port input,
t
r
= t
f
= 1 ns
13
13
14
15
15
A-port output
A-port input,
13
13
14
15
15
C
L
= 0,
B-port output
C
pdB
(1)
f = 10 MHz,
pF
B-port input,
t
r
= t
f
= 1 ns
3
3
3
3
4
A-port output
(1)
Power dissipation capacitance per transceiver
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up V
CCA
.
3. V
CCB
can be ramped up along with or after V
CCA
.
Table 1. Typical Total Static Power Consumption (I
CCA
+ I
CCB
)
V
CCA
V
CCB
UNIT
0 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0 V
0
<0.5
<0.5
<0.5
<0.5
<0.5
1.2 V
<0.5
<1
<1
<1
<1
1
1.5 V
<0.5
<1
<1
<1
<1
1
A
1.8 V
<0.5
<1
<1
<1
<1
<1
2.5 V
<0.5
1
<1
<1
<1
<1
3.3 V
<0.5
1
<1
<1
<1
<1
9
www.ti.com
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
0
1
2
3
4
5
6
0
10
20
30
40
50
60
t
P
L
H
- ns
C
L
- pF
60
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.5 V
V
CCB
= 1.2 V
C
L
- pF - 1.5
t
P
H
L
- ns
C
L
- pF
0
1
2
3
4
5
6
0
10
20
30
40
50
60
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.5 V
V
CCB
= 1.2 V
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
T
A
= 25
C, V
CCA
= 1.2 V
Figure 1.
Figure 2.
10
www.ti.com
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
0
1
2
3
4
5
6
0
10
20
30
40
50
60
t
P
L
H
- ns
C
L
- pF
60
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.5 V
V
CCB
= 1.2 V
C
L
- pF - 1.5
t
P
H
L
- ns
C
L
- pF
0
1
2
3
4
5
6
0
10
20
30
40
50
60
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.5 V
V
CCB
= 1.2 V
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
T
A
= 25
C, V
CCA
= 1.5 V
Figure 3.
Figure 4.
11
www.ti.com
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
0
1
2
3
4
5
6
0
10
20
30
40
50
60
t
P
L
H
- ns
C
L
- pF
60
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.5 V
V
CCB
= 1.2 V
0
1
2
3
4
5
6
0
10
20
30
40
50
60
C
L
- pF - 1.5
t
P
H
L
- ns
C
L
- pF
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.5 V
V
CCB
= 1.2 V
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
T
A
= 25
C, V
CCA
= 1.8 V
Figure 5.
Figure 6.
12
www.ti.com
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
0
1
2
3
4
5
6
0
10
20
30
40
50
60
t
P
L
H
- ns
C
L
- pF
60
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.5 V
V
CCB
= 1.2 V
C
L
- pF - 1.5
t
P
H
L
- ns
C
L
- pF
0
1
2
3
4
5
6
0
10
20
30
40
50
60
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.5 V
V
CCB
= 1.2 V
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
T
A
= 25
C, V
CCA
= 2.5 V
Figure 7.
Figure 8.
13
www.ti.com
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE
0
1
2
3
4
5
6
0
10
20
30
40
50
60
t
P
L
H
- ns
C
L
- pF
60
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.5 V
V
CCB
= 1.2 V
C
L
- pF - 1.5
t
P
H
L
- ns
C
L
- pF
0
1
2
3
4
5
6
0
10
20
30
40
50
60
V
CCB
= 1.8 V
V
CCB
= 2.5 V
V
CCB
= 3.3 V
V
CCB
= 1.5 V
V
CCB
= 1.2 V
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
T
A
= 25
C, V
CCA
= 3.3 V
Figure 9.
Figure 10.
14
www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
OH
V
OL
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
2
V
CCO
Open
GND
R
L
R
L
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
V
CCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
V
CCA
/2
V
CCA
/2
V
CCI
/2
V
CCI
/2
V
CCI
0 V
V
CCO
/2
V
CCO
/2
V
OH
V
OL
0 V
V
CCO
/2
V
OL
+ V
TP
V
CCO
/2
V
OH
- V
TP
0 V
V
CCI
0 V
V
CCI
/2
V
CCI
/2
t
w
Input
V
CCA
V
CCO
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
Input
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
2
V
CCO
GND
TEST
S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
v
10 MHz, Z
O
= 50
, dv/dt
1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
H. V
CCI
is the V
CC
associated with the input port.
I. V
CCO
is the V
CC
associated with the output port.
1.2 V
1.5 V
0.1 V
1.8 V
0.15 V
2.5 V
0.2 V
3.3 V
0.3 V
2 k
2 k
2 k
2 k
2 k
V
CCO
R
L
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
V
TP
C
L
15 pF
15 pF
15 pF
15 pF
15 pF
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
Figure 11. Load Circuit and Voltage Waveforms
15
www.ti.com
APPLICATION INFORMATION
V
CC1
V
CC1
V
CC2
SYSTEM-1
SYSTEM-2
V
CC1
1
2
3
4
8
7
6
5
V
CC2
V
CC2
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
Figure 12
is an example of the SN74AVCH2T45 circuit used in a bidirectional logic level-shifting application.
Figure 12. Bidirectional Logic Level-Shifting Application
PIN
NAME
FUNCTION
DESCRIPTION
1
V
CCA
V
CC1
SYSTEM-1 supply voltage (1.2 V to 3.6 V)
2
A1
OUT1
Output level depends on V
CC1
voltage.
3
A2
OUT2
Output level depends on V
CC1
voltage.
4
GND
GND
Device GND
5
DIR
DIR
GND (low level) determines B-port to A-port direction.
6
B2
IN2
Input threshold value depends on V
CC2
voltage.
7
B1
IN1
Input threshold value depends on V
CC2
voltage.
8
V
CCB
V
CC2
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
16
www.ti.com
APPLICATION INFORMATION
V
CC1
V
CC1
V
CC2
SYSTEM-1
SYSTEM-2
1
2
3
4
8
7
6
5
DIR CTRL
I/O-1
V
CC2
I/O-2
Enable Times
SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D JULY 2004 REVISED AUGUST 2005
Figure 13
shows the SN74AVCH2T45 used in a bidirectional logic level-shifting application. Since the
SN74AVCH2T45 does not have an output-enable (OE) pin, system designers should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
Figure 13. Bidirectional Logic Level-Shifting Application
Following is a sequence that shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2
to SYSTEM-1.
STATE
DIR CTRL
I/O-1
I/O-2
DESCRIPTION
1
H
Out
In
SYSTEM-1 data to SYSTEM-2
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2
2
H
Hi-Z
Hi-Z
are disabled.
The bus-line state depends on bus hold.
DIR bit is flipped. I/O-1 and I/O-2 still are disabled.
3
L
Hi-Z
Hi-Z
The bus-line state depends on bus hold.
4
L
Out
In
SYSTEM-2 data to SYSTEM-1
Calculate the enable times for the SN74AVCH2T45 using the following formulas:
t
PZH
(DIR to A) = t
PLZ
(DIR to B) + t
PLH
(B to A)
t
PZL
(DIR to A) = t
PHZ
(DIR to B) + t
PHL
(B to A)
t
PZH
(DIR to B) = t
PLZ
(DIR to A) + t
PLH
(A to B)
t
PZL
(DIR to B) = t
PHZ
(DIR to A) + t
PHL
(A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVCH2T45 initially is transmitting from A to B, the
DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port
has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
17
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74AVCH2T45DCURE4
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AVCH2T45DCUTE4
ACTIVE
US8
DCU
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVCH2T45DCTR
ACTIVE
SM8
DCT
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVCH2T45DCTT
ACTIVE
SM8
DCT
8
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVCH2T45DCUR
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVCH2T45DCUT
ACTIVE
US8
DCU
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVCH2T45YEPR
PREVIEW
WCSP
YEP
8
3000
TBD
Call TI
Call TI
SN74AVCH2T45YZPR
ACTIVE
WCSP
YZP
8
3000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
7-Feb-2006
Addendum-Page 1
MECHANICAL DATA
MPDS049B MAY 1999 REVISED OCTOBER 2002
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,60
0,20
0,25
0
8
0,15 NOM
Gage Plane
4188781/C 09/02
4,25
5
0,30
0,15
2,90
3,75
2,70
8
4
3,15
2,75
1
0,10
0,00
1,30 MAX
Seating Plane
0,10
M
0,13
0,65
PIN 1
INDEX AREA
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
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