SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
TI-OPC
Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D
OEC
Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
D
LVTTL Interfaces Are 5-V Tolerant
D
High-Drive GTLP Open-Drain Outputs
(100 mA)
D
LVTTL Outputs (24 mA/24 mA)
D
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D
I
off
, Power-Up 3-State, and BIAS V
CC
Support Live Insertion
D
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
1000-V Charged-Device Model (C101)
description
The SN74GTLP2033 is a high-drive, 8-bit, three-wire registered transceiver that provides inverted
LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and
flip-flop modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback
path for control and diagnostics monitoring, the same functionality as the SN74FB2033. The device provides
a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result
of GTLP's reduced output swing (
<
1 V), reduced input threshold levels, improved differential input, OEC
circuitry, and TI-OPC
circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have
been designed and tested using several backplane models. The high drive allows incident-wave switching in
heavily loaded backplanes with equivalent load impedance down to 11
.
Copyright
2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
IMODE1
AI1
AO1
GND
AI2
AO2
V
CC
AI3
AO3
GND
AI4
AO4
AO5
AI5
GND
AO6
AI6
V
CC
AO7
AI7
GND
AO8
AI8
OMODE0
IMODE0
BIAS V
CC
B1
GND
OEAB
B2
ERC
OEAB
B3
GND
CLKAB/LEAB
B4
B5
CLKBA/LEBA
GND
B6
OEBA
V
CC
B7
LOOPBACK
GND
B8
V
REF
OMODE1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLP2033 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V
and V
REF
= 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI
application reports, Texas Instruments GTLP Frequently Asked Questions,
literature number SCEA019, and
GTLP in BTL Applications, literature number SCEA017.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and can be directly driven by TTL or 5-V CMOS devices. V
REF
is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between low and high adjusts the B-port output rise and fall times.
This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OEAB should be tied to V
CC
through a pullup resistor
and OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the driver.
terminal assignments
1
2
3
4
5
6
A
IMODE1
NC
NC
NC
NC
IMODE0
B
AO1
AI1
GND
GND
BIAS VCC
B1
C
AO2
AI2
VCC
ERC
OEAB
B2
D
AO3
AI3
GND
GND
OEAB
B3
E
AO4
AI4
CLKAB/LEAB
B4
F
AO5
AI5
CLKBA/LEBA
B5
G
AO6
AI6
GND
GND
OEBA
B6
H
AO7
AI7
VCC
VCC
LOOPBACK
B7
J
AO8
AI8
GND
GND
VREF
B8
K
OMODE0
NC
NC
NC
NC
OMODE1
NC = No internal connection
GQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP DGG
Tape and reel
SN74GTLP2033DGGR
GTLP2033
40
C to 85
C
TVSOP DGV
Tape and reel
SN74GTLP2033DGVR
GT2033
VFBGA GQL
Tape and reel
SN74GTLP2033GQLR
GR033
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional description
The SN74GTLP2033 is a high-drive (100 mA), 8-bit, three-wire registered transceiver containing D-type latches
and D-type flip-flops for data-path operation in the transparent, latched, or flip-flop modes. Data transmission
is complementary, with inverted AI data going to the B port and inverted B data going to AO. The split LVTTL
AI and AO provides a feedback path for control and diagnostics monitoring.
The logic element for data flow in each direction is configured by two mode (IMODE1 and IMODE0 for B to A,
OMODE1 and OMODE0 for A to B) inputs as a buffer, D-type flip-flop, or D-type latch. When configured in the
buffer mode, the inverted input data appears at the output port. In the flip-flop mode, data is stored on the rising
edge of the appropriate clock (CLKAB/LEAB or CLKBA/LEBA) input. In the latch mode, the clock inputs serve
as active-high transparent latch enables.
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the
LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the
output of the selected A-to-B logic element (prior to inversion) is the B-to-A input.
The AO enable/disable control is provided by OEBA. When OEBA is low or when V
CC
is less than 1.5 V, AO
is in the high-impedance state. When OEBA is high, AO is active (high or low logic levels).
The B port is controlled by OEAB and OEAB. If OEAB is low, OEAB is high, or V
CC
is less than 1.5 V, the B port
is inactive. If OEAB is high and OEAB is low, the B port is active.
The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic
elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated
outputs are in the high-impedance (AO) or inactive (B port) states.
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Function Tables
FUNCTION/MODE
INPUTS
OUTPUT
MODE
OEBA
OEAB
OEAB
OMODE1
OMODE0
IMODE1
IMODE0
LOOPBACK
OUTPUT
MODE
L
L
X
X
X
X
X
X
Z
Isolation
L
X
H
X
X
X
X
X
Z
Isolation
X
H
L
L
L
X
X
X
Buffer
X
H
L
L
H
X
X
X
Inverted AI to B
Flip-flop
X
H
L
H
X
X
X
X
Latch
H
L
X
X
X
L
L
L
I
t d B t AO
B ff
H
X
H
X
X
L
L
L
Inverted B to AO
Buffer
H
L
X
X
X
L
H
L
I
t d B t AO
Fli fl
H
X
H
X
X
L
H
L
Inverted B to AO
Flip-flop
H
L
X
X
X
H
X
L
I
t d B t AO
L t h
H
X
H
X
X
H
X
L
Inverted B to AO
Latch
H
L
X
X
X
L
L
H
AI to AO
Buffer
H
X
H
X
X
L
L
H
AI to AO
Buffer
H
L
X
X
X
L
H
H
AI to AO
Flip flop
H
X
H
X
X
L
H
H
AI to AO
Flip-flop
H
L
X
X
X
H
X
H
AI to AO
Latch
H
X
H
X
X
H
X
H
AI to AO
Latch
H
H
L
X
X
X
X
L
Inverted AI to B,
Inverted B to AO
Transparent with
feedback path
ENABLE/DISABLE
INPUTS
OUTPUTS
OEBA
OEAB
OEAB
AO
B
L
X
X
Z
H
X
X
Active
X
L
L
Z
X
L
H
Z
X
H
L
Active
X
H
H
Z
BUFFER
INPUT
OUTPUT
L
H
H
L
LATCH
INPUTS
OUTPUT
CLK/LE
DATA
OUTPUT
H
L
H
H
H
L
L
X
Q0
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Function Tables (Continued)
LOOPBACK
LOOPBACK
Q
L
B port
H
Point P
Q is the input to the B-to-A
logic element.
P is the output of the A-to-B
logic element (see functional
block diagram).
SELECT
INPUTS
SELECTED LOGIC
MODE1
MODE0
ELEMENT
L
L
Buffer
L
H
Flip-flop
H
X
Latch
FLIP-FLOP
INPUTS
OUTPUT
CLK/ LE
DATA
OUTPUT
L
X
Q0
L
H
H
L
B-PORT EDGE-RATE CONTROL (ERC)
INPUT
ERC
OUTPUT
B-PORT
LOGIC LEVEL
EDGE RATE
H
Slow
L
Fast
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
CLKBA/LEBA
OEAB
OEAB
OMODE0
OMODE1
CLKAB/LEAB
AI1
IMODE0
IMODE1
B1
AO1
OEBA
LOOPBACK
44
41
24
25
38
2
48
1
35
3
32
29
46
One of Eight Channels
Transceiver
1D
C1
1D
C1
1D
C1
1D
C1
P
Q
VREF
ERC
26
42
Pin numbers shown are for the DGG and DGV packages.
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
and BIAS V
CC
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1): AI port, ERC, and control inputs
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . .
B port and V
REF
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1): AO port
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
: AO port
48 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any A-port output in the high state, I
O
(see Note 2)
48 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGG package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL package
42
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Notes 4 through 7)
MIN
NOM
MAX
UNIT
VCC,
BIAS VCC
Supply voltage
3.15
3.3
3.45
V
VTT
Termination voltage
GTL
1.14
1.2
1.26
V
VTT
Termination voltage
GTLP
1.35
1.5
1.65
V
VREF
Reference voltage
GTL
0.74
0.8
0.87
V
VREF
Reference voltage
GTLP
0.87
1
1.1
V
VI
Input voltage
B port
VTT
V
VI
Input voltage
Except B port and VREF
VCC
5.5
V
VIH
High level input voltage
B port
VREF+0.05
V
VIH
High-level input voltage
Except B port
2
V
VIL
Low level input voltage
B port
VREF0.05
V
VIL
Low-level input voltage
Except B port
0.8
V
IIK
Input clamp current
18
mA
IOH
High-level output current
AO
24
mA
IOL
Low level output current
AO
24
mA
IOL
Low-level output current
B port
100
mA
t/
v
Input transition rise or fall rate
Outputs enabled
10
ns/V
t/
VCC
Power-up ramp rate
20
s/V
TA
Operating free-air temperature
40
85
C
NOTES:
4. All unused control and B-port inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable but, generally, GND is connected first.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction
and is activated when VTT
>
0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to
minimize current drain.
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VCC = 3.15 V,
II = 18 mA
1.2
V
VCC = 3.15 V to 3.45 V,
IOH = 100
A
VCC0.2
VOH
AO
VCC = 3 15 V
IOH = 12 mA
2.4
V
VCC = 3.15 V
IOH = 24 mA
2
VCC = 3.15 V to 3.45 V,
IOL = 100
A
0.2
AO
VCC = 3 15 V
IOL = 12 mA
0.4
VOL
VCC = 3.15 V
IOL = 24 mA
0.5
V
VOL
IOL = 10 mA
0.2
V
B port
VCC = 3.15 V
IOL = 64 mA
0.4
IOL = 100 mA
0.55
II
AI and
control inputs
VCC = 3.45 V,
VI = 0 or 5.5 V
10
A
I
AO
VCC = 3.45 V,
VO = 0 to 5.5 V
10
A
IOZ
B port
VCC = 3.45 V, VREF within 0.6 V of VTT,
VO = 0 to 2.3 V
10
A
VCC = 3.45 V, IO = 0,
Outputs high
40
ICC
AO or B port
VCC = 3.45 V, IO = 0,
VI (A-port or control input) = VCC or GND,
Outputs low
40
mA
VI (B port) = VTT or GND
Outputs disabled
40
ICC
VCC = 3.45 V, One AI or control input at VCC 0.6 V,
Other AI or control inputs at VCC or GND
1.5
mA
Ci
AI
VI = 3 15 V or 0
3.5
4.5
pF
Ci
Control inputs
VI = 3.15 V or 0
3.5
5.5
pF
Co
AO
VO = 3.15 V or 0
5
6
pF
Cio
B port
VO = 1.5 V or 0
8.5
10
pF
All typical values are at VCC = 3.3 V, TA = 25
C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Ioff
VCC = 0,
VI or VO = 0 to 5.5 V
10
A
IOZPU
VCC = 0 to 1.5 V,
VO = 0.5 V to 3 V,
OEBA = VCC
30
A
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
OEBA = VCC
30
A
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Ioff
VCC = 0,
BIAS VCC = 0,
VI or VO = 0 to 1.5 V
10
A
IOZPU
VCC = 0 to 1.5 V, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OEAB = 0 and OEAB = VCC
30
A
IOZPD
VCC = 1.5 V to 0, BIAS VCC = 0, VO = 0.5 V to 1.5 V, OEAB = 0 and OEAB = VCC
30
A
ICC
VCC = 0 to 3.15 V
BIAS VCC = 3 15 V to 3 45 V
VO (B port) = 0 to 1 5 V
5
mA
CC
(BIAS VCC)
VCC = 3.15 V to 3.45 V
BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0 to 1.5 V
10
A
VO
VCC = 0,
BIAS VCC = 3.3 V,
IO = 0
0.95
1.05
V
IO
VCC = 0,
BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V
1
A
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTLP (unless otherwise noted)
MIN
MAX
UNIT
fclock
Clock frequency
175
MHz
tw
Pulse duration
CLKAB/LEAB or CLKBA/LEBA
2.8
ns
AI before CLKAB
1.1
AI before CLKBA
1.4
t
Setup time
B before CLKBA
1
ns
tsu
Setup time
AI before LEAB
1.6
ns
AI before LEBA
2.1
B before LEBA
2.2
AI after CLKAB
0.3
AI after CLKBA
0.2
th
Hold time
B after CLKBA
0.6
ns
th
Hold time
AI after LEAB
0.3
ns
AI after LEBA
0
B after LEBA
0
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
MIN
TYP
MAX
UNIT
fmax
175
MHz
tPLH
AI
B
Sl
3
7.4
ns
tPHL
(buffer)
B
Slow
3
7.1
ns
tPLH
AI
B
F
t
2
5.9
ns
tPHL
(buffer)
B
Fast
2
5.8
ns
tPLH
B
AO
1
5.7
ns
tPHL
B
(buffer)
AO
1
5
ns
tPLH
LEAB
B
Slo
4.2
8.6
ns
tPHL
(latch mode)
B
Slow
3.2
7.7
ns
tPLH
LEAB
B
F
t
3.2
7.6
ns
tPHL
(latch mode)
B
Fast
2.8
6.7
ns
tPLH
LEAB
AO
2
7
ns
tPHL
(latch mode)
AO
1.8
6.3
ns
tPLH
LEBA
AO
1
5.7
ns
tPHL
LEBA
(latch mode)
AO
1
4.7
ns
tPLH
OEAB
B
Sl
3.8
7.5
ns
tPHL
OEAB
B
Slow
3.1
7
ns
tPLH
OEAB
B
Fast
2.5
6
ns
tPHL
OEAB
B
Fast
2.5
6
ns
tPLH
OEAB
B
Sl
3.5
7.5
ns
tPHL
OEAB
B
Slow
3
7.2
ns
tPLH
OEAB
B
F
t
2.5
6
ns
tPHL
OEAB
B
Fast
2.5
6
ns
tPZH
OEBA
AO
1
4.7
ns
tPZL
OEBA
AO
1
3.4
ns
tPHZ
OEBA
AO
1
5.2
ns
tPLZ
OEBA
AO
1
4.9
ns
tPLH
CLKAB
B
Sl
4.4
8.8
ns
tPHL
(flip-flop mode)
B
Slow
3.6
8.1
ns
tPLH
CLKAB
B
F
t
3.2
7.2
ns
tPHL
(flip-flop mode)
B
Fast
3.1
6.9
ns
tPLH
CLKAB
AO
2
6.9
ns
tPHL
(flip-flop mode)
AO
1.8
6.4
ns
tPLH
CLKBA
AO
1
5.6
ns
tPHL
(flip-flop mode)
AO
1
4.9
ns
tPLH
OMODE
B
Sl
3.8
8.7
ns
tPHL
OMODE
B
Slow
3.2
8.2
ns
tPLH
OMODE
B
F
t
2.7
7.2
ns
tPHL
OMODE
B
Fast
2.7
7.2
ns
tPLH
IMODE
AO
1
5.6
ns
tPHL
IMODE
AO
1
4.6
ns
Slow (ERC = H) and Fast (ERC = L)
All typical values are at VCC = 3.3 V, TA = 25
C.
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
TT
= 1.5 V and V
REF
= 1 V for GTLP (see Figure 1) (continued)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
MIN
TYP
MAX
UNIT
tPLH
LOOPBACK
AO
2.5
6.2
6.2
ns
tPHL
LOOPBACK
AO
2
5
5
ns
tPLH
AI
AO
1
5.6
5.6
ns
tPHL
(loopback high)
AO
1
5
5
ns
Rise time B port outputs (20% to 80%)
Slow
2.8
tr
Rise time, B-port outputs (20% to 80%)
Fast
1.5
ns
Rise time, AO (10% to 90%)
3.5
Fall time B port outputs (80% to 20%)
Slow
3
tf
Fall time, B-port outputs (80% to 20%)
Fast
1.8
ns
Fall time, AO (90% to 10%)
1.5
Slow (ERC = H) and Fast (ERC = L)
All typical values are at VCC = 3.3 V, TA = 25
C.
skew characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
MIN
TYP
MAX
UNIT
tsk(LH)
AI
B
Slow
0.5
1
ns
tsk(HL)
AI
B
Slow
0.5
1
ns
tsk(LH)
AI
B
Fast
0.4
0.9
ns
tsk(HL)
AI
B
Fast
0.4
0.9
ns
tsk(LH)
CLKAB/LEAB
B
Slow
0.5
1
ns
tsk(HL)
CLKAB/LEAB
B
Slow
0.5
1
ns
tsk(LH)
CLKAB/LEAB
B
Fast
0.4
0.9
ns
tsk(HL)
CLKAB/LEAB
B
Fast
0.4
0.9
ns
AI
B
Slow
1.4
2
t k(t)
AI
B
Fast
0.6
1.4
ns
tsk(t)
CLKAB/LEAB
B
Slow
1.8
2.5
ns
CLKAB/LEAB
B
Fast
0.9
1.8
Slow (ERC = L) and Fast (ERC = H)
All typical values are at VCC = 3.3 V, TA = 25
C.
Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
tsk(LH)/tsk(HL) and tsk(t) Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs
switching in the same direction either high to low [tsk(HL)] or low to high [tsk(LH)] or in opposite directions, both low to high and high to low [tsk(t)].
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1
Open
GND
500
500
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
GND
tPLH
tPHL
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH 0.3 V
0 V
3 V
0 V
tw
Input
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(VM = 1.5 V for A port and 1 V for B port)
(VOH = 3 V for A port and 1.5 V for B port)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(AI to B port)
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(AO)
Output
Input
1.5 V
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
12.5
LOAD CIRCUIT FOR B OUTPUTS
0 V
VOH
VOL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to AO)
Output
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2 ns, tf
2 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
tPLH
tPHL
VOH
0 V
VM
VM
Data
Input
3 V
0 V
tsu
th
Timing
Input
1.5 V
1.5 V
1.5 V
1.5 V
1 V
1 V
1 V
1 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuits and Voltage Waveforms
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer's backplane application is probably a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer to better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
Drvr
1.5 V
.25"
1"
1"
1"
1.5 V
1"
1"
1"
.25"
Rcvr
Rcvr
Rcvr
Figure 2. High-Drive Test Backplane
Slot 1
Slot 2
Slot 19
Slot 20
Conn.
Conn.
Conn.
Conn.
ZO = 50
22
22
From Output
Under Test
Test
Point
1.5 V
CL = 18 pF
11
LL = 14 nH
Figure 3. High-Drive RLC Network
SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C JUNE 2001 REVISED SEPTEMBER 2001
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE
TYP
UNIT
tPLH
AI
B
Sl
4.7
ns
tPHL
(buffer)
B
Slow
5
ns
tPLH
AI
B
F
t
3.7
ns
tPHL
(buffer)
B
Fast
4
ns
tPLH
LEAB
B
Sl
5.5
ns
tPHL
(latch mode)
B
Slow
5.8
ns
tPLH
LEAB
B
Fast
4.6
ns
tPHL
(latch mode)
B
Fast
4.8
ns
tPLH
CLKAB
B
Sl
5.8
ns
tPHL
(flip-flop mode)
B
Slow
6
ns
tPLH
CLKAB
B
F
t
4.9
ns
tPHL
(flip-flop mode)
B
Fast
4.9
ns
tPLH
OMODE
B
Sl
5.5
ns
tPHL
OMODE
B
Slow
5.7
ns
tPLH
OMODE
B
F
t
4.5
ns
tPHL
OMODE
B
Fast
4.7
ns
t
Rise time B port outputs (20% to 80%)
Slow
1.8
ns
tr
Rise time, B-port outputs (20% to 80%)
Fast
1.1
ns
tf
Fall time B port outputs (80% to 20%)
Slow
3.4
ns
tf
Fall time, B-port outputs (80% to 20%)
Fast
2.6
ns
Slow (ERC = H) and Fast (ERC = L)
All typical values are at VCC = 3.3 V, TA = 25
C. All values are derived from TI-SPICE models.
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74GTLP2033DGGRE4
ACTIVE
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
74GTLP2033DGVRE4
ACTIVE
TVSOP
DGV
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74GTLP2033DGGR
ACTIVE
TSSOP
DGG
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74GTLP2033DGVR
ACTIVE
TVSOP
DGV
48
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74GTLP2033GQLR
ACTIVE
VFBGA
GQL
56
1000
TBD
SNPB
Level-1-240C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2005
Addendum-Page 1
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50
4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
1
12
24
13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
38
24
16
4,90
5,10
3,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins MO-153
14/16/20/56 Pins MO-194
MECHANICAL DATA
MTSS003D JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040078 / F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0
8
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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