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FEATURES
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
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51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1DIR
1A1
1A2
GND
1A3
1A4
V
CC
GND
1A5
1A6
GND
1A7
1A8
GND
ERC
2A1
2A2
GND
2A3
2A4
GND
V
CC
2A5
2A6
GND
2A7
2A8
2DIR
1OE
1B1
1B2
GND
1B3
1B4
V
CC
GND
1B5
1B6
GND
1B7
1B8
BIAS V
CC
V
REF
2B1
2B2
GND
2B3
2B4
GND
V
CC
2B5
2B6
GND
2B7
2B8
2OE
DESCRIPTION/ORDERING INFORMATION
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D OCTOBER 1999 REVISED JUNE 2005
Member of the Texas Instruments WidebusTM
Family
TI-OPCTM Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OECTM Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Outputs (100 mA)
LVTTL Outputs (24 mA/24 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
Data-Transfer Rate and Signal Integrity in
Distributed Loads
I
off
, Power-Up 3-State, and BIAS V
CC
Support
Live Insertion
Bus Hold on A-Port Data Inputs
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
The SN74GTLPH1645 is a high-drive, 16-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL
signal-level translation. It is partitioned as two 8-bit transceivers. The device provides a high-speed interface
between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed
(about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced
output swing (<1 V), reduced input threshold levels, improved differential input, OECTM circuitry, and TI-OPCTM
circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and
tested using several backplane models. The high drive allows incident-wave switching in heavily loaded
backplanes with equivalent load impedance down to 11
.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH1645 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (V
TT
= 1.2 V and V
REF
= 0.8 V) or GTLP (V
TT
= 1.5 V and
V
REF
= 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
REF
is the B-port differential input
reference voltage.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, TI-OPC, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 19992005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D OCTOBER 1999 REVISED JUNE 2005
This device is fully specified for live-insertion applications using I
off
, power-up 3-state, and BIAS V
CC
. The I
off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
CC
circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal
integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and V
CC
adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TSSOP DGG
Tape and reel
SN74GTLPH1645DGGR
GTLPH1645
40
C to 85
C
TVSOP DGV
Tape and reel
SN74GTLPH1645DGVR
GL45
VFBGA GQL
Tape and reel
SN74GTLPH1645GQLR
GL45
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2
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GQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D OCTOBER 1999 REVISED JUNE 2005
TERMINAL ASSIGNMENTS
1
2
3
4
5
6
A
1A2
1A1
1DIR
1OE
1B1
1B2
B
1A4
1A3
GND
GND
1B3
1B4
C
1A5
GND
V
CC
V
CC
GND
1B5
D
1A7
1A6
GND
GND
1B6
1B7
E
GND
1A8
1B8
BIAS V
CC
F
ERC
2A1
2B1
V
REF
G
2A2
2A3
GND
GND
2B3
2B2
H
2A4
GND
V
CC
V
CC
GND
2B4
J
2A5
2A6
GND
GND
2B6
2B5
K
2A7
2A8
2DIR
2OE
2B8
2B7
3
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FUNCTIONAL DESCRIPTION
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D OCTOBER 1999 REVISED JUNE 2005
The SN74GTLPH1645 is a high-drive (100-mA), 16-bit bus transceiver partitioned as two 8-bit segments and is
designed for asynchronous communication between data buses. The device transmits data from the A port to the
B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input. OE can
be used to disable the device so the buses are effectively isolated. Data polarity is noninverting.
For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs.
When OE is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except OE and DIR are low.
FUNCTION TABLES
<br/>
OUTPUT CONTROL
INPUTS
OUTPUT
MODE
OE
DIR
H
X
Z
Isolation
L
L
B data to A port
True transparent
L
H
A data to B port
B-PORT EDGE-RATE CONTROL (ERC)
INPUT ERC
OUTPUT
B-PORT
LOGIC
NOMINAL
EDGE RATE
LEVEL
VOLTAGE
L
GND
Slow
H
V
CC
Fast
4
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1DIR
1OE
1A1
1B1
1
2
56
55
V
REF
42
2DIR
2OE
2A1
2B1
To Seven Other Channels
28
16
29
41
ERC
15
To Seven Other Channels
SN74GTLPH1645
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290D OCTOBER 1999 REVISED JUNE 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
(1)
(1)
Pin numbers shown are for the DGG and DGV packages.
5
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