1
Data sheet acquired from Harris Semiconductor
SCHS123
Features
Retriggerable/Resettable Capability
Trigger and Reset Propagation Delays Independent of
R
X
, C
X
Triggering from the Leading or Trailing Edge
Q and Q Buffered Outputs Available
Separate Resets
Wide Range of Output-Pulse Widths
Schmitt Trigger Input on A and B Inputs
Retrigger Time is Independent of C
X
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
1
A at V
OL
, V
OH
Pinout
CD54HC4538, CD74HC4538, CD74HCT4538
(PDIP, SOIC, CERDIP)
TOP VIEW
Description
The
Harris
CD54HC4538,
CD74HC4538
and
CD74HCT4538 are dual retriggerable/resettable monostable
precision multivibrators for fixed voltage timing applications.
An external resistor (R
X
) and an external capacitor (C
X
)
control the timing and the accuracy for the circuit.
Adjustment of R
X
and C
X
provides a wide range of output
pulse widths from the Q and Q terminals. The propagation
delay
from
trigger
input-to-output
transition
and
the
propagation delay from reset input-to-output transition are
independent of R
X
and C
X
.
Leading-edge triggering (A) and trailing edge triggering (B)
inputs are provided for triggering from either edge of the
input pulse. An unused "A" input should be tied to GND and
an unused B should be tied to V
CC
. On power up the IC is
reset. Unused resets and sections must be terminated. In
normal operation the circuit retriggers on the application of
each new trigger pulse. To operate in the non-triggerable
mode Q is connected to B when leading edge triggering (A)
is used or Q is connected to A when trailing edge triggering
(B) is used. The period (
) can be calculated from
= (0.7)
R
X
, C
X
; R
MIN
is 5k
. C
MIN
is 0pF.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
1C
X
1R
X
C
X
1R
1A
1B
1Q
GND
1Q
V
CC
2R
X
C
X
2R
2A
2B
2Q
2Q
2C
X
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG.
NO.
CD54HC4538F
-55 to 125
16 Ld CERDIP
F16.3
CD74HC4538E
-55 to 125
16 Ld PDIP
E16.3
CD74HCT4538E
-55 to 125
16 Ld PDIP
E16.3
CD74HC4538M
-55 to 125
16 Ld SOIC
M16.15
CD74HCT4538M
-55 to 125
16 Ld SOIC
M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1998
File Number
1671.2
CD54HC4538, CD74HC4538,
CD74HCT4538
High Speed CMOS Logic Dual Retriggerable
Precision Monostable Multivibrator
[ /Title
(CD54
HC453
8,
CD74
HC453
8,
CD74
HCT45
38)
/Sub-
ject
(High
Speed
CMOS
Logic
June 1998
2
Functional Diagram
2R
13
2A
12
11
10
9
2Q
2Q
2B
MONO 2
V
CC
15
14
2Cx
2RxCx
1R
3
1A
5
4
6
7
1Q
1Q
1B
MONO 1
V
CC
1
2
1Cx
1RxCx
1Cx
1Rx
2Cx
2Rx
GND = 8
V
CC
= 16
TRUTH TABLE
INPUTS
OUTPUTS
R
A
B
Q
Q
L
X
X
L
H
X
H
X
L
H
X
X
L
L
H
H
L
H
H
NOTE: H = High Level, L = Low Level,
= Transition from Low to
High,
= Transition from High to Low,
One High Level Pulse,
One Low Level Pulse, X = Irrelevant.
FIGURE 1. FF DETAIL
CL
CL
CL
CL
p
n
p
n
p
n
CL
R1
R2
CL
R1
Q
Q
CL
D
CD54HC4538, CD74HC4538, CD74HCT4538
3
FIGURE 2. LOGIC DIAGRAM (1 MONO)
FUNCTIONAL TERMINAL CONNECTIONS
FUNCTION
V
CC
TO
TERMINAL NUMBER
GND TO
TERMINAL NUMBER
INPUT PULSE TO
TERMINAL NUMBER
OTHER
CONNECTIONS
MONO
1
MONO
2
MONO
1
MONO
2
MONO
1
MONO
2
MONO
1
MONO
2
Leading-Edge
Trigger/Retriggerable
3, 5
11, 13
4
12
Leading-Edge
Trigger/Non-Retriggerable
3
13
4
12
5-7
11-9
Trailing-Edge
Trigger/Retriggerable
3
13
4
12
5
11
Trailing-Edge
Trigger/Non-Retriggerable
3
13
5
11
4-6
12-10
NOTES:
3. A retriggerable one-shot multivibrator has an output pulse width which is extended one full time period (T) after application of the last
trigger pulse.
4. A non-triggerable one-shot multivibrator has a time period (T) referenced from the application of the first trigger pulse.
FIGURE 3. INPUT PULSE TRAIN
FIGURE 4. RETRIGGERABLE MODE
PULSE WIDTH (A MODE)
FIGURE 5. NON-RETRIGGERABLE MODE
PULSE WIDTH
(A MODE)
D
CL
CL
Q
Q
R2
R1
FF
V
CC
V
CC
R
X
C
X
2(14)
1(15)
8
R
A
B
3(13)
4(12)
5(11)
V
CC
V
CC
HIGH Z
V
CC
V
CC
R1
R2
COMP II
-
+
6(10)
7(9)
Q
Q
V
CC
16
T
T
CD54HC4538, CD74HC4538, CD74HCT4538
4
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
(Note 5)
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Times, t
r
, t
f
Reset Input:
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Trigger Inputs A or B:
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max)
External Timing Resistor, R
X
(Note 6) . . . . . . . . . . . . . . . .5k
(Min)
External Timing Capacitor, C
X
(Note 6) . . . . . . . . . . . . . . . . . 0 (Min)
Thermal Resistance (Typical, Note 7)
JA
(
o
C/W)
J
C (
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
90
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
160
N/A
CERDIP Package . . . . . . . . . . . . . . . .
130
55
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
5. Unless otherwise specified, all voltages are referenced to ground.
6. The maximum allowable values of R
X
and C
X
are a function of leakage of capacitor C
X
, the leakage of the HC4538, and leakage due to
board layout and surface resistance. Values of R
X
and C
X
should be chosen so that the maximum current into pin 2 or pin 14 is 30mA.
Susceptibility to externally induced noise signals may occur for R
X
> 1M
.
7.
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
CD54HC4538, CD74HC4538, CD74HCT4538
5
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current A, B, R
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
Input Leakage
Current R
X
C
X
(Note 9)
-
6
-
-
0.05
-
0.5
-
0.5
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
8
-
80
-
160
A
Active Device Current
Q = High & Pins 2, 14
at V
CC
/4
I
CC
V
CC
or
GND
0
6
-
-
0.6
-
0.8
-
1
mA
HCT TYPES
High Level Input
Voltage
V
IH
-
-
4.5 to
5.5
2
-
-
2
-
2
-
V
Low Level Input
Voltage
V
IL
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
and
GND
-
5.5
-
0.1
-
1
-
1
A
Input Leakage
Current R
X
C
X
(Note 9)
-
5.5
-
-
0.05
-
0.5
-
0.5
A
Quiescent Device
Current
I
CC
V
CC
or
GND
0
5.5
-
-
8
-
80
-
160
A
Active Device Current
Q = High & Pins 2, 14
at V
CC
/4
I
CC
V
CC
or
GND
0
5.5
-
-
0.6
-
0.8
-
1
mA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
I
CC
(Note 8)
V
CC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTES:
8. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
9. When testing I
IL
the Q output must be high. If Q is low (device not triggered) the pull-up P device will be ON and the low resistance path
from V
DD
to the test pin will cause a current far exceeding the specification.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CD54HC4538, CD74HC4538, CD74HCT4538
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