SN54HC590A, SN74HC590A
8 BIT BINARY COUNTERS
WITH 3 STATE OUTPUT REGISTERS
SCLS039F - DECEMBER 1982 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
2-V to 6-V V
CC
Operation
D
High-Current 3-State Parallel Register
Outputs Can Drive Up To 15 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 14 ns
D
6-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
D
8-Bit Counter With Register
D
Counter Has Direct Clear
SN54HC590A . . . J OR W PACKAGE
SN74HC590A . . . D, DW, OR N PACKAGE
(TOP VIEW)
SN54HC590A . . . FK PACKAGE
(TOP VIEW)
NC - No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
GND
V
CC
Q
A
OE
RCLK
CCKEN
CCLK
CCLR
RCO
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
OE
RCLK
NC
CCKEN
CCLK
Q
D
Q
E
NC
Q
F
Q
G
Q
NC
RCO
CCLR
H
GND
NC
C
Q
B
V
CC
Q
A
Q
description/ordering information
The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register
has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary
counter features direct clear (CCLR) and count-enable (CCKEN) inputs. A ripple-carry output (RCO) is provided
for cascading. Expansion is accomplished easily for two stages by connecting RCO of the first stage to CCKEN
of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage
to the counter clock (CCLK) input of the following stage.
CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together,
the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock
enable.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube of 25
SN74HC590AN
SN74HC590AN
Tube of 40
SN74HC590AD
-40
C to 85
C
SOIC - D
Reel of 2500
SN74HC590ADR
HC590A
-40
C to 85
C
SOIC - D
Reel of 250
SN74HC590ADT
HC590A
SOIC - DW
Tube of 40
SN74HC590ADW
HC590A
SOIC - DW
Reel of 2000
SN74HC590ADWR
HC590A
CDIP - J
Tube of 25
SNJ54HC590AJ
SNJ54HC590AJ
-55
C to 125
C
CFP - W
Tube of 150
SNJ54HC590AW
SNJ54HC590AW
-55 C to 125 C
LCCC - FK
Tube of 55
SNJ54HC590AFK
SNJ54HC590AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC590A, SN74HC590A
8 BIT BINARY COUNTERS
WITH 3 STATE OUTPUT REGISTERS
SCLS039F - DECEMBER 1982 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing diagram
RCO
QA-QH
CCKEN
CCLR
OE
CCLK
COUNTER
(internal)
RCLK
Hex 01
Hex 02
Hex 03
Hex 04
Hex 05
Hex FD
Hex FE
Hex FF
Hex 00
Hex01
Hex 00
Hex 01
Hi-Z
Hex 01
Hex 05
Hex 00
TIMING SEQUENCE
1. Clear Counter (asynchronous).
2. Count up: 0x01. Store 0x00 in register.
3. Inhibit counter clock (CCKEN = HIGH). Store 0x01 in register.
4. Count 0x02, 0x03.
5. 3-state the outputs
6. Count up: 0x04
7. Enable outputs.
8. Continue up: 0x05
9. Store 0x05 in register.
10. Continue counting: 0x06...0xFD, 0xFE, 0xFF, 0x00, etc.
11. Store 0x00 in register.
Don't
Care
Hex 00
Don't
Care
SN54HC590A, SN74HC590A
8 BIT BINARY COUNTERS
WITH 3 STATE OUTPUT REGISTERS
SCLS039F - DECEMBER 1982 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
1R
C1
1S
T
R
14
13
12
11
10
9
15
1
2
3
4
5
6
7
OE
RCLK
CCKEN
CCLK
CCLR
RCO
QA
QB
QC
QD
QE
QF
QG
QH
Pin numbers shown are for the D, DW, J, N, and W packages.
SN54HC590A, SN74HC590A
8 BIT BINARY COUNTERS
WITH 3 STATE OUTPUT REGISTERS
SCLS039F - DECEMBER 1982 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
70 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
57
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC590A
SN74HC590A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
2
5
6
2
5
6
V
VCC = 2 V
1.5
1.5
VIH
High-level input voltage
VCC = 4.5 V
3.15
3.15
V
VIH
High-level input voltage
VCC = 6 V
4.2
4.2
V
VCC = 2 V
0.5
0.5
VIL
Low-level input voltage
VCC = 4.5 V
1.35
1.35
V
VIL
Low-level input voltage
VCC = 6 V
1.8
1.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
1000
1000
tt
Input transition (rise and fall) time
VCC = 4.5 V
500
500
ns
tt
Input transition (rise and fall) time
VCC = 6 V
400
400
ns
TA
Operating free-air temperature
-55
125
-40
85
C
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CCLK and RCLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54HC590A, SN74HC590A
8 BIT BINARY COUNTERS
WITH 3 STATE OUTPUT REGISTERS
SCLS039F - DECEMBER 1982 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HC590A
SN74HC590A
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
2 V
1.9
1.998
1.9
1.9
IOH = -20
A
4.5 V
4.4
4.499
4.4
4.4
IOH = -20
A
6 V
5.9
5.999
5.9
5.9
VOH
VI = VIH or VIL
RCO, IOH = -4 mA
4.5 V
3.98
4.3
3.7
3.84
V
VOH
VI = VIH or VIL
QA-QH, IOH = -6 mA
4.5 V
3.98
4.3
3.7
3.84
V
RCO, IOH = -5.2 mA
6 V
5.48
5.8
5.2
5.34
QA-QH, IOH = -7.8 mA
6 V
5.48
5.8
5.2
5.34
2 V
0.002
0.1
0.1
0.1
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
IOL = 20
A
6 V
0.001
0.1
0.1
0.1
VOL
VI = VIH or VIL
RCO, IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
V
VOL
VI = VIH or VIL
QA-QH, IOL = 6 mA
4.5 V
0.17
0.26
0.4
0.33
V
RCO, IOL = 5.2 mA
6 V
0.15
0.26
0.4
0.33
QA-QH, IOL = 7.8 mA
6 V
0.15
0.26
0.4
0.33
II
VI = VCC or 0
6 V
0.1
100
1000
1000
nA
IOZ
VO = VCC or 0
6 V
0.01
0.5
10
5
A
ICC
VI = VCC or 0,
IO = 0
6 V
8
160
80
A
Ci
2 V
to 6 V
3
10
10
10
pF
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