SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A DECEMBER 1983 REVISED MARCH 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Quad Bus Buffers
D
3-State Outputs
D
Separate Control for Each Channel
description
These bus buffers feature three-state outputs
that, when enabled, have the low impedance
characteristics of a TTL output with additional
drive capability at high logic levels to permit
driving heavily loaded bus lines without external
pullup resistors. When disabled, both output
transistors are turned off, presenting a
high-impedance state to the bus so the output will
act neither as a significant load nor as a driver. The
'125 and 'LS125A devices' outputs are disabled
when G is high. The '126 and 'LS126A devices'
outputs are disabled when G is low.
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54125, SN54126, SN54LS125A,
SN54LS126A . . . J OR W PACKAGE
SN74125, SN74126 . . . N PACKAGE
SN74LS125A, SN74LS126A . . . D, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1G, 1G*
1A
1Y
2G, 2G*
2A
2Y
GND
V
CC
4G, 4G*
4A
4Y
3G, 3G*
3A
3Y
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3G, 3G*
1Y
NC
2G, 2G*
NC
2A
1A
1G, 1G*
NC
3Y
3A
4G, 4G*
2Y
GND
NC
V
CC
SN54LS125A, SN54LS126A . . . FK PACKAGE
(TOP VIEW)
*G on '125 and 'LS125A devices;
G on 126 and 'LS126A devices
NC No internal connection
*G on '125 and 'LS125A devices;
G on 126 and 'LS126A devices
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A DECEMBER 1983 REVISED MARCH 2002
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP
N
Tube
SN74LS125AN
SN74LS125AN
PDIP N
Tube
SN74LS126AN
SN74LS126AN
Tube
SN74LS125AD
LS125A
0
C to 70
C
SOIC
D
Tape and reel
SN74LS125ADR
LS125A
0
C to 70
C
SOIC D
Tube
SN74LS126AD
LS126A
Tape and reel
SN74LS126ADR
LS126A
SOP
NS
Tape and reel
SN74LS125ANSR
74LS125A
SOP NS
Tape and reel
SN74LS126ANSR
74LS126A
CDIP
J
Tube
SN54LS125AJ
SN54LS125AJ
55
C to 125
C
CDIP J
Tube
SNJ54LS125AJ
SNJ54LS125AJ
55
C to 125
C
CFP W
Tube
SNJ54LS125AW
SNJ54LS125AW
LCCC FK
Tube
SNJ54LS125AFK
SNJ54LS125AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
logic diagram (each gate)
A
Y
Y = A
G
'125, 'LS125A
A
Y
G
'126, 'LS126A
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A DECEMBER 1983 REVISED MARCH 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
schematics (each gate)
'125 CIRCUITS
'126 CIRCUITS
1.6 k
W
OUTPUT Y
OUTPUT Y
1.6 k
W
1.6 k
W
1.6 k
W
625
W
625
W
4 k
W
4 k
W
4 k
W
4 k
W
4.25 k
W
2.5 k
W
2.5 k
W
2.5 k
W
2.5 k
W
1 k
W
1 k
W
4 k
W
85
W
85
W
DATA
INPUT A
CONTROL
INPUT G
GND
GND
VCC
VCC
CONTROL
INPUT G
DATA
INPUT A
4 k
W
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
('125 and '126)
Supply voltage, V
CC
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
5.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A DECEMBER 1983 REVISED MARCH 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
schematics (each gate)
10 k
W
18 k
W
12 k
W
8 k
W
18 k
W
18 k
W
8 k
W
6 k
W
6 k
W
4 k
W
4 k
W
5 k
W
4 k
W
750
W
750
W
5 k
W
4 k
W
20 k
W
20 k
W
1.5 k
W
1.5 k
W
50
W
50
W
INPUT G
INPUT G
INPUT A
INPUT A
OUTPUT
GND
OUTPUT
GND
VCC
VCC
'LS125A CIRCUITS
'LS126A CIRCUITS
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
('LS125A and 'LS126A)
Supply voltage, V
CC
(see Note 1)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
86
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
80
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
76
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. Voltage values are with respect to network ground terminal.
2. The package termal impedance is calculated in accordance with JESD 51-7.
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A DECEMBER 1983 REVISED MARCH 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
SN54125
SN54126
SN74125
SN74126
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
IOH
High-level output current
2
5.2
mA
IOL
Low-level output current
16
16
mA
TA
Operating free-air temperature
55
125
0
70
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54125
SN54126
SN74125
SN74126
UNIT
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = MIN,
II = 12 mA
1.5
1.5
V
VOH
VCC = MIN,
VIH = 2 V,
IOH = 2 mA
2.4
3.3
V
VOH
VIL = 0.8 V
IOH = 5.2 mA
2.4
3.1
V
VOL
VCC = MIN,
VIH = 2 V,
VIL = 0.8 V,
0 4
0 4
V
VOL
IOL = 16 mA
0.4
0.4
V
I
VCC = MAX
VIH = 2 V,
VO = 2.4 V
40
40
A
IOZ
VIL = 0.8 V
VO = 0.4 V
40
40
A
II
VCC = MAX,
VI = 6.5 V
1
1
mA
IIH
VCC = MAX,
VI = 2.4 V
40
40
A
IIL
VCC = MAX,
VI = 0.4 V
1.6
1.6
mA
IOS
VCC = MAX
30
70
28
70
mA
ICC
VCC = MAX
'125
32
54
32
54
mA
ICC
CC
(see Note 3)
'126
36
62
36
62
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time.
NOTE 3: Data inputs = 0 V; output control = 4.5 V for '125 and 0 V for '126.
switching characteristics, V
CC
= 5 V, T
A
= 25
C (see Figure 1)
PARAMETER
TEST CONDITIONS
SN54125
SN74125
SN54126
SN74126
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
tPLH
RL = 400
CL = 50 pF
8
13
8
13
ns
tPHL
RL = 400
,
CL = 50 F
12
18
12
18
ns
tPZH
RL = 400
CL = 50 pF
11
17
11
18
ns
tPZL
RL = 400
,
CL = 50 F
16
25
16
25
ns
tPHZ
RL = 400
CL = 5 pF
5
8
10
16
ns
tPLZ
RL = 400
,
CL = 5 F
7
12
12
18
ns
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A DECEMBER 1983 REVISED MARCH 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
SN54LS125A
SN54LS126A
SN74LS125A
SN74LS126A
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
4.75
5
5.25
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.7
0.8
V
IOH
High-level output current
1
2.6
mA
IOL
Low-level output current
12
24
mA
TA
Operating free-air temperature
55
125
0
70
C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LS125A
SN54LS126A
SN74LS125A
SN74LS126A
UNIT
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
VIK
VCC = MIN,
II = 18 mA
1.5
1.5
V
VOH
VCC = MIN,
VIL = 0.7 V,
IOH = 1 mA
2.4
V
VOH
VIH = 2 V
VIL = 0.8 V
IOH = 2.6 mA
2.4
V
V
MIN
VIL = 0.7 V,
IOL = 12 mA
0.25
0.4
VOL
VCC = MIN,
VIH = 2 V
VIL = 0.8 V,
IOL = 12 mA
0.25
0.4
V
VIH = 2 V
VIL = 0.8 V,
IOL = 24 mA
0.35
0.5
VIL = 0 7 V
VO = 2.4 V
20
I
VCC = MAX,
VIL = 0.7 V
VO = 0.4 V
20
A
IOZ
CC
,
VIH = 2 V,
VIL = 0 8 V
VO = 2.4 V
20
A
VIL = 0.8 V
VO = 0.4 V
20
II
VCC = MAX,
VI = 7 V
0.1
0.1
mA
IIH
VCC = MAX,
VI = 2.7 V
20
20
A
IIL
VCC = MAX,
'LS125A-G inputs
0.2
0.2
mA
IIL
VI = 0.4 V
'LS125A-A inputs; 'LS126A All inputs
0.4
0.4
mA
IOS
VCC = MAX
40
225
40
225
mA
ICC
VCC = MAX
'LS125A
11
20
11
20
mA
ICC
CC
(see Note 4)
'LS126A
12
22
12
22
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25
C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 4: Data inputs = 0 V; output control = 4.5 V for 'LS125A and 0 V for 'LS126A.
switching characteristics, V
CC
= 5 V, T
A
= 25
C (see Figure 1)
PARAMETER
TEST CONDITIONS
SN54LS125A
SN74LS125A
SN54LS126A
SN74LS126A
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
tPLH
RL = 667
CL = 45 pF
9
15
9
15
ns
tPHL
RL = 667
,
CL = 45 F
7
18
8
18
ns
tPZH
RL = 667
CL = 45 pF
12
20
16
25
ns
tPZL
RL = 667
,
CL = 45 F
15
25
21
35
ns
tPHZ
RL = 667
CL = 5 pF
20
25
ns
tPLZ
RL = 667
,
CL = 5 F
20
25
ns
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A DECEMBER 1983 REVISED MARCH 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 DEVICES
tPHL
tPLH
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
1 k
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO
50
; tr and tf
7 ns for Series
54/74 devices and tr and tf
2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D)
1.5 V
VOH 0.5 V
VOL + 0.5 V
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
tw
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
VOH
VOL
Figure 1. Load Circuits and Voltage Waveforms
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
SN54125, SN54126, SN54LS125A, SN54LS126A,
SN74125, SN74126, SN74LS125A, SN74LS126A
QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SDLS044A DECEMBER 1983 REVISED MARCH 2002
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
tPHL
tPLH
tPLH
tPHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
High-Level
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note D)
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC
RL
Test
Point
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
(see Note B)
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
5 k
NOTES: A. CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR
1 MHz, ZO
50
, tr
1.5 ns, tf
2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.
S1
S2
tPHZ
tPLZ
tPZL
tPZH
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
3 V
0 V
Output
Control
(low-level
enabling)
Waveform 1
(see Notes C
and D)
Waveform 2
(see Notes C
and D)
1.5 V
VOH 0.5 V
VOL + 0.5 V
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
tw
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
VOL
VOH
Figure 2. Load Circuits and Voltage Waveforms
The SN54125, SN54126, SN74125,
SN74126, and SN54LS126A are
obsolete and are no longer supplied.
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
JM38510/32301B2A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
JM38510/32301BCA
ACTIVE
CDIP
J
14
1
TBD
Call TI
Level-NC-NC-NC
JM38510/32301BDA
ACTIVE
CFP
W
14
1
TBD
Call TI
Level-NC-NC-NC
JM38510/32301SCA
ACTIVE
CDIP
J
14
1
TBD
Call TI
Level-NC-NC-NC
JM38510/32301SDA
ACTIVE
CFP
W
14
1
TBD
Call TI
Level-NC-NC-NC
SN54126J
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
SN54LS125AJ
ACTIVE
CDIP
J
14
1
TBD
Call TI
Level-NC-NC-NC
SN74125N
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
SN74125N3
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
SN74126N
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
SN74LS125AD
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS125ADBR
ACTIVE
SSOP
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS125ADBRE4
ACTIVE
SSOP
DB
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS125ADE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS125ADR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS125ADRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS125AN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74LS125AN3
OBSOLETE
PDIP
N
14
TBD
Call TI
Call TI
SN74LS125ANE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74LS125ANSR
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS125ANSRE4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS125ANSRG4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS126AD
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS126ADE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS126ADR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS126ADRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LS126AJ
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
SN74LS126AN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74LS126ANE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74LS126ANSR
ACTIVE
SO
NS
14
2000 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
Addendum-Page 1
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
no Sb/Br)
SN74LS126ANSRE4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54126J
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
SNJ54126W
OBSOLETE
CFP
W
14
TBD
Call TI
Call TI
SNJ54LS125AFK
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54LS125AJ
ACTIVE
CDIP
J
14
1
TBD
Call TI
Level-NC-NC-NC
SNJ54LS125AW
ACTIVE
CFP
W
14
1
TBD
Call TI
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
Addendum-Page 2
MECHANICAL DATA
MLCC006B OCTOBER 1996
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,90
7,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
20
16
6,50
6,50
14
0,05 MIN
5,90
5,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65
M
0,15
0
8
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
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Use of such information may require a license from a third party under the patents or other intellectual property
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2005, Texas Instruments Incorporated
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