SN74LVC161284
19 BIT BUS INTERFACE
SCAS583J - NOVEMBER 1996 - REVISED FEBRUARY 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
1.4-k
Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Designed for the IEEE Std 1284-I (Level 1
Type) and IEEE Std 1284-II (Level 2 Type)
Electrical Specifications
D
Flow-Through Architecture Optimizes PCB
Layout
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin-Shrink
Small-Outline (DGG) Packages
description/ordering information
The SN74LVC161284 is designed for 3-V to 3.6-V
V
CC
operation. This device provides
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
This device has eight bidirectional bits; data can
flow in the A-to-B direction when DIR is high and
in the B-to-A direction when DIR is low. This
device also has five drivers, which drive the cable
side, and four receivers. The SN74LVC161284
has one receiver dedicated to the HOST LOGIC
line and a driver to drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in
a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive
requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel
peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have
a 1.4-k
integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low
state or if the output voltage is above V
CC
CABLE. If V
CC
CABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. V
CC
is designed for 3-V to 3.6-V operation. V
CC
CABLE supplies the inputs
and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even
when V
CC
CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.
The SN74LVC161284 is characterized for operation from 0
C to 70
C.
Copyright
2005 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
HD
A9
A10
A11
A12
A13
V
CC
A1
A2
GND
A3
A4
A5
A6
GND
A7
A8
V
CC
PERI LOGIC IN
A14
A15
A16
A17
HOST LOGIC OUT
DIR
Y9
Y10
Y11
Y12
Y13
V
CC
CABLE
B1
B2
GND
B3
B4
B5
B6
GND
B7
B8
V
CC
CABLE
PERI LOGIC OUT
C14
C15
C16
C17
HOST LOGIC IN
PACKAGE PREVIEW
PACKAGE PREVIEW
SN74LVC161284
19 BIT BUS INTERFACE
SCAS583J - NOVEMBER 1996 - REVISED FEBRUARY 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP DGG
Tape and reel
SN74LVC161284DGGR
SSOP DL
Tape
SN74LVC161284DL
LVC161284
0
C to 70
C
SSOP DL
Tape and reel
SN74LVC161284DLR
LVC161284
0
C to 70
C
TSSOP DGG
Tape and reel
74LVC161284DGGRG4
SSOP DL
Tape
74LVC161284DLRE4
LVC161284
SSOP DL
Tape and reel
74LVC161284DLRG4
LVC161284
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUT
MODE
DIR
HD
OUTPUT
MODE
L
L
Open drain
A9-A13 to Y9-Y13 and PERI LOGIC IN to PERI LOGIC OUT
L
L
Totem pole
B1-B8 to A1-A8 and C14-C17 to A14-A17
L
H
Totem pole
B1-B8 to A1-A8, A9-A13 to Y9-Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14-C17 to A14-A17
H
L
Open drain
A1-A8 to B1-B8, A9-A13 to Y9-Y13, and PERI LOGIC IN to PERI LOGIC OUT
H
L
Totem pole
C14-C17 to A14-A17
H
H
Totem pole
A1-A8 to B1-B8, A9-A13 to Y9-Y13, C14-C17 to A14-A17, and PERI LOGIC IN to PERI LOGIC OUT
SN74LVC161284
19 BIT BUS INTERFACE
SCAS583J - NOVEMBER 1996 - REVISED FEBRUARY 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram
See Note B
See Note B
See Note A
B1-B8
Y9-Y13
PERI LOGIC OUT
C14-C17
HOST LOGIC IN
VCC CABLE
DIR
HD
A1-A8
A9-A13
PERI LOGIC IN
A14-A17
HOST LOGIC OUT
42
48
1
19
24
30
25
NOTES: A. The PMOS transistor prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND.
B. The PMOS transistors prevent backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The
PMOS transistor is turned off when the associated driver is in the low state.
SN74LVC161284
19 BIT BUS INTERFACE
SCAS583J - NOVEMBER 1996 - REVISED FEBRUARY 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range: V
CC
CABLE
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
CC
-0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input and output voltage range, V
I
and V
O
: Cable side (see Notes 1 and 2)
-2 V to 7 V
. . . . . . . . . . . . . . . . . .
Peripheral side (see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
: Except PERI LOGIC OUT
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PERI LOGIC OUT
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output high sink current, I
SK
(V
O
= 5.5 V and V
CC
CABLE = 3 V)
65 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGG package
89
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
94
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The ac input voltage pulse duration is limited to 40 ns if the amplitude is greater than -0.5 V.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
VCC CABLE
Supply voltage for the cable side, VCC CABLE
VCC
3
5.5
V
VCC
Supply voltage
3
3.6
V
A, B, DIR, and HD
2
VIH
High-level input voltage
C14-C17
2.3
V
VIH
High-level input voltage
HOST LOGIC IN
2.6
V
PERI LOGIC IN
2
A, B, DIR, and HD
0.8
VIL
Low-level input voltage
C14-C17
0.8
V
VIL
Low-level input voltage
HOST LOGIC IN
1.6
V
PERI LOGIC IN
0.8
VI
Input voltage
Peripheral side
0
VCC
V
VI
Input voltage
Cable side
0
5.5
V
VO
Open-drain output voltage
HD low
0
5.5
V
HD high, B and Y outputs
-14
IOH
High-level output current
A outputs and HOST LOGIC OUT
-4
mA
IOH
High-level output current
PERI LOGIC OUT
-0.5
mA
B and Y outputs
14
IOL
Low-level output current
A outputs and HOST LOGIC OUT
4
mA
IOL
Low-level output current
PERI LOGIC OUT
84
mA
TA
Operating free-air temperature
0
70
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74LVC161284
19 BIT BUS INTERFACE
SCAS583J - NOVEMBER 1996 - REVISED FEBRUARY 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
V
CC
CABLE = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Vt
Input hysteresis
VthH - VthL for all inputs except the
C inputs and HOST LOGIC IN
3.3 V
0.4
V
Vt
Input hysteresis
VthH - VthL for the HOST LOGIC IN
3.3 V
0.2
V
VthH - VthL for the C inputs
3.3 V
0.8
HD high, B and Y outputs
IOH = -14 mA
3 V
2.23
HD high, B and Y outputs
IOH = -14 mA
3.3 V
2.4
VOH
HD high, A outputs, and
IOH = -4 mA
3 V
2.4
V
VOH
HD high, A outputs, and
HOST LOGIC OUT
IOH = -50
A
3 V
2.8
V
PERI LOGIC OUT
IOH = -0.5 mA
3.15 V
3.1
PERI LOGIC OUT
IOH = -0.5 mA
3.3 V
4.5
B and Y outputs
IOL = 14 mA
3 V
0.77
VOL
A outputs and HOST LOGIC OUT
IOL = 50
A
3 V
0.2
V
VOL
A outputs and HOST LOGIC OUT
IOL = 4 mA
3 V
0 4
V
PERI LOGIC OUT
IOL = 84 mA
3 V
0.8
C inputs
VI = VCC
3.6 V
w
50
A
II
C inputs
VI = GND (pullup resistors)
3.6 V
w
-3.5
mA
II
All inputs except the B or C inputs
VI = VCC or GND
3.6 V
1
A
B outputs
VO = VCC
3.6 V
20
A
IOZ
B outputs
VO = GND (pullup resistors)
3.6 V
w
-3.5
mA
IOZ
A1-A8
VO = VCC or GND
3.6 V
20
A
Open-drain Y outputs
VO = GND (pullup resistors)
3.6 V
w
-3.5
mA
Ioff
Leakage to GND, B and Y outputs
VI or VO = 0 to 7 V
0 V
100
A
Ioff
Leakage to VCC, B and Y outputs
VI or VO = 0 to 7 V
0 V
10
A
ICC
VI = VCC,
IO = 0
3.6 V
0.8
mA
ICC
VI = GND (12
pullup)
3.6 V
45
mA
Ci
Control inputs
VI = VCC or GND
3.3 V
3
4
pF
Cio
All inputs
VO = VCC or GND
3.3 V
7
15
pF
ZO
Cable side
IOH = -35 mA
3.3 V
45
R pullup
Cable side
VO = 0 V (in Hi Z)
3.3 V
1.15
1.65
k
Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25
C.
VCC CABLE = 4.7 V
VCC CABLE = 3.6 V
A maximum current of 170
A per pin is added to ICC if the pullup resistor pin is above VCC.
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