SN54LVTH162373, SN74LVTH162373
3.3 V ABT 16 BIT TRANSPARENT D TYPE LATCHES
WITH 3 STATE OUTPUTS
SCBS261L - JULY 1993 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
Output Ports Have Equivalent 22-
Series
Resistors, So No External Resistors Are
Required
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
CC
)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
description/ordering information
The 'LVTH162373 devices are16-bit transparent D-type latches with 3-state outputs designed for low-voltage
(3.3-V) V
CC
operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices
are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP - DL
Tube
SN74LVTH162373DL
LVTH162373
SSOP - DL
Tape and reel
SN74LVTH162373DLR
LVTH162373
-40
C to 85
C
TSSOP - DGG
Tape and reel
SN74LVTH162373DGGR
LVTH162373
-40 C to 85 C
VFBGA - GQL
Tape and reel
SN74LVTH162373KR
LL2373
VFBGA - ZQL (Pb-free)
Tape and reel
74LVTH162373ZQLR
LL2373
-55
C to 125
C
CFP - WD
Tape and reel
SNJ54LVTH162373WD
SNJ54LVTH162373WD
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Widebus is a trademark of Texas Instruments.
SN54LVTH162373 . . . WD PACKAGE
SN74LVTH162373 . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVTH162373, SN74LVTH162373
3.3 V ABT 16 BIT TRANSPARENT D TYPE LATCHES
WITH 3 STATE OUTPUTS
SCBS261L - JULY 1993 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without
interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the
outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-
series resistors to reduce
overshoot and undershoot.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V
CC
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which
prevents driver conflict.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D
inputs.
terminal assignments
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1LE
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
VCC
VCC
1D3
1D4
D
1Q6
1Q5
GND
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
VCC
VCC
2D6
2D5
J
2Q7
2Q8
GND
GND
2D8
2D7
K
2OE
NC
NC
NC
NC
2LE
NC - No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
2
1
3
4
6
5
K
SN54LVTH162373, SN74LVTH162373
3.3 V ABT 16 BIT TRANSPARENT D TYPE LATCHES
WITH 3 STATE OUTPUTS
SCBS261L - JULY 1993 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1LE
1D1
To Seven Other Channels
1Q1
2OE
2LE
2D1
2Q1
To Seven Other Channels
1
48
47
24
25
36
C1
1D
13
2
C1
1D
Pin numbers shown are for the DGG, DL, and WD packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
(see Note 1)
-0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . .
Current into any output in the low state, I
O
30
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2)
30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGG package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
63
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL/ZQL package
42
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54LVTH162373
SN74LVTH162373
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2.7
3.6
2.7
3.6
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
-12
-12
mA
IOL
Low-level output current
12
12
mA
t/
v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54LVTH162373, SN74LVTH162373
3.3 V ABT 16 BIT TRANSPARENT D TYPE LATCHES
WITH 3 STATE OUTPUTS
SCBS261L - JULY 1993 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
SN54LVTH162373
SN74LVTH162373
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
VIK
VCC = 2.7 V,
II = -18 mA
-1.2
-1.2
V
VOH
VCC = 3 V,
IOH = -12 mA
2
2
V
VOL
VCC = 3 V,
IOL = 12 mA
0.8
0.8
V
VCC = 0 or 3.6 V,
VI = 5.5 V
10
10
II
Control inputs
VCC = 3.6 V,
VI = VCC or GND
1
1
A
II
Data inputs
VCC = 3.6 V
VI = VCC
1
1
A
Data inputs
VCC = 3.6 V
VI = 0
-5
-5
Ioff
VCC = 0,
VI or VO = 0 to 4.5 V
100
A
VCC = 3 V
VI = 0.8 V
75
75
II(hold)
Data inputs
VCC = 3 V
VI = 2 V
-75
-75
A
II(hold)
Data inputs
VCC = 3.6 V,
VI = 0 to 3.6 V
500
-750
A
IOZH
VCC = 3.6 V,
VO = 3 V
5
5
A
IOZL
VCC = 3.6 V,
VO = 0.5 V
-5
-5
A
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
100*
100
A
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don't care
100*
100
A
VCC = 3.6 V,
Outputs high
0.19
0.19
ICC
VCC = 3.6 V,
IO = 0,
V = V
or GND
Outputs low
5
5
mA
ICC
IO = 0,
VI = VCC or GND
Outputs disabled
0.19
0.19
mA
ICC
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V,
Other inputs at VCC or GND
0.2
0.2
mA
Ci
VI = 3 V or 0
3
3
pF
Co
VO = 3 V or 0
9
9
pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
All typical values are at VCC = 3.3 V, TA = 25
C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH162373
SN74LVTH162373
VCC = 3.3 V
0.3 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tw
Pulse duration, LE high
3
3
3
3
ns
tsu
Setup time, data before LE
1.3
0.6
1
0.6
ns
th
Hold time, data after LE
1
1.1
1
1.1
ns
SN54LVTH162373, SN74LVTH162373
3.3 V ABT 16 BIT TRANSPARENT D TYPE LATCHES
WITH 3 STATE OUTPUTS
SCBS261L - JULY 1993 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF (unless
otherwise noted) (see Figure 1)
SN54LVTH162373
SN74LVTH162373
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
0.3 V
VCC = 2.7 V
VCC = 3.3 V
0.3 V
VCC = 2.7 V
UNIT
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
TYP
MAX
MIN
MAX
tPLH
D
Q
1.8
5
5.7
1.9
3.1
4.6
5.1
ns
tPHL
D
Q
1.8
4.4
4.8
1.9
2.8
4
4.3
ns
tPLH
LE
Q
2.1
5.4
6.2
2.2
3.4
5.1
5.8
ns
tPHL
LE
Q
2.1
4.9
4.7
2.2
3.2
4.6
4.3
ns
tPZH
OE
Q
1.7
5.6
7
1.8
3.2
5.4
6.6
ns
tPZL
OE
Q
1.7
5.3
5.9
1.8
3.2
4.9
5.5
ns
tPHZ
OE
Q
2.3
6.3
6.6
2.4
3.8
5.4
5.7
ns
tPLZ
OE
Q
1
7.4
6.4
2.2
3.5
5.1
5
ns
tsk(o)
0.5
ns
All typical values are at VCC = 3.3 V, TA = 25
C.
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