SN54LVTH16543, SN74LVTH16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS699D JULY 1997 REVISED APRIL 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
TM
Family
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
CC
)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
C
D
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The 'LVTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) V
CC
operation, but
with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two
8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB
or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA
inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Copyright
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
SN54LVTH16543 . . . WD PACKAGE
SN74LVTH16543 . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEAB
1LEAB
1CEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
SN54LVTH16543, SN74LVTH16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS699D JULY 1997 REVISED APRIL 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
When V
CC
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH16543 is characterized for operation over the full military temperature range of 55
C to 125
C.
The SN74LVTH16543 is characterized for operation from 40
C to 85
C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
CEAB
LEAB
OEAB
A
B
H
X
X
X
Z
X
X
H
X
Z
L
H
L
X
B0
L
L
L
L
L
L
L
L
H
H
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
Output level before the indicated steady-state
input conditions were established
SN54LVTH16543, SN74LVTH16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS699D JULY 1997 REVISED APRIL 1999
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic symbol
1A2
6
1A3
8
1A4
9
1A5
10
1A6
12
1A7
13
1A8
14
2A2
16
2A3
17
2A4
19
2A5
20
2A6
21
2A7
23
2A8
24
15
2A1
8C12
27
5
1A1
6D
1B6
45
1B7
44
1B8
43
1B2
51
1B3
49
1B4
48
1B5
47
1B1
52
5D
3
4
G8
26
8EN10
28
7C11
30
G7
31
7EN9
29
2C6
2
G2
3
2EN4
1
1C5
55
G1
54
1EN3
56
12D
2B6
36
2B7
34
2B8
33
2B2
41
2B3
40
2B4
38
2B5
37
2B1
42
11D
9
10
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54LVTH16543, SN74LVTH16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS699D JULY 1997 REVISED APRIL 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
1B1
To Seven Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A1
2B1
To Seven Other Channels
56
54
55
1
3
2
5
29
31
30
28
26
27
15
C1
1D
C1
1D
C1
1D
C1
1D
42
52
SN54LVTH16543, SN74LVTH16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS699D JULY 1997 REVISED APRIL 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1)
0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
(see Note 1)
0.5 V to V
CC
+ 0.5 V
. . . . . . . . . . . . .
Current into any output in the low state, I
O
: SN54LVTH16543 96
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH16543 128
mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2): SN54LVTH16543
48 mA
. . . . . . . . . . . . . . . . . . . . .
SN74LVTH16543 64
mA
. . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0)
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 3): DGG package
81
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
74
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH16543
SN74LVTH16543
UNIT
MIN
MAX
MIN
MAX
UNIT
VCC
Supply voltage
2.7
3.6
2.7
3.6
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
24
32
mA
IOL
Low-level output current
48
64
mA
t/
v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
t/
VCC
Power-up ramp rate
200
200
s/V
TA
Operating free-air temperature
55
125
40
85
C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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