SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G - APRIL 1999 - REVISED APRIL 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
Designed to Be Used in Voltage-Limiting
Applications
D
6.5-
On-State Connection Between Ports
A and B
D
Flow-Through Pinout for Ease of Printed
Circuit Board Trace Routing
D
Direct Interface With GTL+ Levels
D
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
description/ordering information
The SN74TVC16222A provides 23 parallel
NMOS pass transistors with a common gate. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device can be used as a 22-bit switch, with the
gates cascaded together to a reference transistor.
The low-voltage side of each pass transistor is
limited to a voltage set by the reference transistor.
This is done to protect components with inputs
that are sensitive to high-state voltage-level
overshoots. (See Application Information in this
data sheet.)
All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can
be used as the reference transistor. Because, within the device, the characteristics from transistor to transistor
are equal, the maximum output high-state voltage (V
OH
) is approximately the reference voltage (V
REF
), with
minimal deviation from one output to another. This is a benefit of the TVC solution over discrete devices.
Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the
low-voltage side, and the I/O signals are bidirectional through each FET.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP - DL
Tube
SN74TVC16222DL
TVC16222A
-40
C to 85
C
SSOP - DL
Tape and reel
SN74TVC16222DLR
TVC16222A
-40
C to 85
C
TSSOP - DGG
Tape and reel
SN74TVC16222DGGR
TVC16222A
TVSOP - DGV
Tape and reel
SN74TVC16222DGVR
TW222A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright
2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and TI are trademarks of Texas Instruments.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
GATE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G - APRIL 1999 - REVISED APRIL 2005
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
simplified schematic
48
47
46
45
44
25
1
2
3
4
5
24
GND
A1
A2
A3
A4
A23
GATE
B1
B2
B3
B4
B23
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range, V
I
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/output voltage range, V
I/O
(see Note 1)
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current
128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0)
-50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): DGG package
70
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
58
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package
63
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are
observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
TYP
MAX
UNIT
VI/O
Input/output voltage
0
5.5
V
VGATE
GATE voltage
0
5.5
V
IPASS
Pass-transistor current
20
64
mA
TA
Operating free-air temperature
-40
85
C
application operating conditions (see Figure 3)
MIN
TYP
MAX
UNIT
VBIAS
BIAS voltage
VREF + 0.6
2.1
5
V
VGATE
GATE voltage
VREF + 0.6
2.1
5
V
VREF
Reference voltage
0
1.5
4.4
V
VDPU
Drain pullup voltage
2.36
2.5
2.64
V
IPASS
Pass-transistor current
14
20
mA
IREF
Reference-transistor current
5
A
TA
Operating free-air temperature
-40
85
C
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G - APRIL 1999 - REVISED APRIL 2005
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIK
VBIAS = 0,
II = -18 mA
-1.2
V
VOL
IREF = 5
m
A,
VDPU = 2.625 V,
VREF = 1.365 V,
RDPU = 150
VS = 0.175 V,
See Figure 2
350
mV
Ci(GATE)
VI = 3 V or 0
73
pF
Cio(off)
VO = 3 V or 0
4
12
pF
Cio(on)
VO = 3 V or 0
12
25
pF
ron
IREF = 5
m
A,
VDPU = 2.625 V,
VREF = 1.365 V,
RDPU = 150
VS = 0.175 V,
See Figure 2
12.5
All typical values are at TA = 25
C.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower voltage of the two (A or B) terminals.
electrical characteristics from -40
C to 75
C
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
ron
IREF = 5
m
A,
VDPU = 2.625 V,
VREF = 1.552 V,
RDPU = 150
VS = 0.175 V,
See Figure 2
10
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range,
V
DPU
= 2.36 V to 2.64 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
tPLH
A or B
B or A
0
4
ns
tPHL
A or B
B or A
0
4
ns
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G - APRIL 1999 - REVISED APRIL 2005
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tPLHREF
tPHLREF
2.5 V
0 V
2.5 V
VOL
Input
Tester
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Reference
TESTER CALIBRATION SETUP (see Note C)
VOL
Output
Device
Under Test
tPLHDUT
tPLH
(see Note D)
tPHLDUT
tPHL
(see Note E)
2.5 V
200 k
3.3 V
RDPU =
150
Open-Drain
Test Interface
Motherboard
Interface
2
A1 (VREF)
1
GATE
48
B1 (VBIAS)
47
VDPU
TVC16222A
NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR
10 MHz, ZO = 50
, tr
2 ns, tf
2 ns.
B. The outputs are measured one at a time, with one transition per measurement.
C. Test procedure: tPLHREF and tPHLREF are obtained by measuring the propagation delay of a reference measuring point.
tPLHDUT and tPHLDUT are obtained by measuring the propagation delay of the device under test.
D. tPLH = tPLHDUT - tPLHREF
E. tPHL = tPHLDUT - tPHLREF
B2
46
RDPU =
150
RDPU =
150
RDPU =
150
B3
45
B4
44
B23
25
3
A2 (VS)
4
A3 (VS)
5
A4 (VS)
24
A23 (VS)
1.25 V
1.25 V
1.25 V
1.25 V
1.25 V
1.25 V
Output tested
Output reference
Input tested
DEFINITION
SYMBOL
GATE
Figure 1. Tester Calibration Setup and Voltage Waveforms
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G - APRIL 1999 - REVISED APRIL 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
TVC background information
In personal computer (PC) architecture, there are industry-accepted bus standards. These standards define,
among other things, the I/O voltage levels at which the bus communicates. Examples include the GTL+ host
bus, the AGP graphics port, and the PCI local bus. In new designs, the system components must communicate
with existing bus infrastructure. Providing an evolutionary upgrade path is important in the design of PC
architecture, but the existing bus standards must be preserved.
To achieve the ever-present need for smaller, faster, lighter devices that draw less power, yet have faster
performance, most new high-performance digital integrated circuits are designed and produced with advanced
submicron semiconductor process technologies. These devices have thin gate-oxide or short channel lengths
and very low absolute-maximum voltages that can be tolerated at the inputs/outputs (I/Os) without causing
damage. In many cases, the I/Os of these devices are not tolerant of the high-state voltage levels on the
preexisting buses with which they must communicate. Therefore, it became necessary to protect the I/Os of
devices by limiting the I/O voltages.
The Texas Instruments (TI
) translation voltage-clamp (TVC) family is designed specifically for protecting
sensitive I/Os (see Figure 2). The information in this data sheet describes the I/O-protection application of the
TVC family and should enable the design engineer to successfully implement an I/O-protection circuit utilizing
the TI TVC solution.
Low-Voltage
I/O Device
TVC Family
Voltage-Clamp
Device
Standard-Voltage
I/O Bus
Figure 2. Thin Gate-Oxide Protection Application
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G - APRIL 1999 - REVISED APRIL 2005
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
TVC voltage-limiting application
For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any
one of the transistors (see Figure 3). This connection determines the V
BIAS
input of the reference transistor. The
V
BIAS
input is connected through a pullup resistor (typically 200 k
) to the V
DD
supply. A filter capacitor on V
BIAS
is recommended. The opposite side of the reference transistor is used as the reference voltage (V
REF
)
connection. The V
REF
input must be less than V
DDREF
- 1 V to bias the reference transistor into conduction.
The reference transistor regulates the gate voltage (V
GATE
) of all the pass transistors. V
GATE
is determined by
the characteristic gate-to-source voltage difference (V
GS
) because V
GATE
= V
REF
+ V
GS
. The low-voltage side
of the pass transistors has a high-level voltage limited to a maximum of V
GATE
- V
GS
, or V
REF
.
200 k
VDDREF = 3.3 V
150
150
150
150
Open-Drain
CPU Interface
Motherboard
Interface
3
A2
4
A3
5
A4
24
A23
1
VDPU
TVC16222A
GATE
48
B1 (VBIAS)
47
2
A1 (VREF)
VREF and VBIAS can be applied to any one of the pass transistors. GATE must be connected externally to VBIAS.
B2
46
B3
45
B4
44
B23
25
Figure 3. Typical Application Circuit
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G - APRIL 1999 - REVISED APRIL 2005
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
electrical characteristics
The electrical characteristics of the NMOS transistors used in the TVC devices are illustrated by TI SPICE
simulations. Figure 4 shows the test configuration for the TI SPICE simulations. The results, shown in
Figures 5 and 6, show the current through a pass transistor versus the voltage at the source for different
reference voltages. The plots of the dc characteristics clearly reveal that the device clamps at the desired
reference voltage for the varying device environments.
Figure 5 shows the V-I characteristics with low reference voltages and a reference-transistor drain-supply
voltage of 3.3 V. To further investigate the spread of the V-I characteristic curves, V
REF
was held at 2.5 V and
I
REF
was increased by raising V
DDREF
(see Figure 6). The result was a tighter grouping of the V-I curves.
VDPASS
VREF
RDREF
GATE
VBIAS
VDDREF
RDPASS
VDDPASS
VSPASS
Figure 4. TI SPICE-Simulation Schematic and Voltage-Node Names
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G - APRIL 1999 - REVISED APRIL 2005
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
VSPASS - Low Reference Voltage - V
- Pass Current - mA
P
ASS
I
- Pass Current - mA
P
ASS
I
- Pass Current - mA
P
ASS
I
Weak
Nominal
Strong
VREF = 1 V
VDDREF = 3.3 V
RDREF = 200 k
RDPASS = 150
VDDPASS = 3.3 V
Weak
Nominal
Strong
Weak
Nominal
Strong
VSPASS - Low Reference Voltage - V
VSPASS - Low Reference Voltage - V
VREF = 1.5 V
VDDREF = 3.3 V
RDREF = 200 k
RDPASS = 150
VDDPASS = 3.3 V
VREF = 2 V
VDDREF = 3.3 V
RDREF = 200 k
RDPASS = 150
VDDPASS = 3.3 V
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
Figure 5. V-I Electrical Characteristics at Low V
REF
Voltages
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G - APRIL 1999 - REVISED APRIL 2005
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
- Pass Current - mA
P
ASS
I
- Pass Current - mA
P
ASS
I
- Pass Current - mA
P
ASS
I
VSPASS - Low Reference Voltage - V
VSPASS - Low Reference Voltage - V
VSPASS - Low Reference Voltage - V
Weak
Nominal
Strong
VREF = 2.5 V
VDDREF = 3.3 V
RDREF = 200 k
RDPASS = 150
VDDPASS = 3.3 V
Weak
Nominal
Strong
VREF = 2.5 V
VDDREF = 4 V
RDREF = 200 k
RDPASS = 150
VDDPASS = 3.3 V
Weak
Nominal
Strong
VREF = 2.5 V
VDDREF = 5 V
RDREF = 200 k
RDPASS = 150
VDDPASS = 3.3 V
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
Figure 6. V-I Electrical Characteristics at V
REF
= 2.5 V
SN74TVC16222A
22 BIT VOLTAGE CLAMP
SCDS087G - APRIL 1999 - REVISED APRIL 2005
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
features and benefits
The TVC family has several features that benefit a system designer when implementing a
sensitive-I/O-protection solution. Table 1 lists these features and their associated benefits.
Table 1. Features and Benefits
FEATURES
BENEFITS
Any FET can be used as the reference transistor.
Ease of layout
All FETs on one die, tight process control
Very low spread of VO relative to VREF
No active control logic (passive device)
No logic power supply (VCC) required
Flow-through pinout
Ease of trace routing
Devices offered in different bit widths and packages
Optimizes design and cost effectiveness
Designer flexibility with VREF input
Allows migration to lower-voltage I/Os without board redesign
conclusion
The TI TVC family provides the designer with a solution for protection of circuits with I/Os that are sensitive to
high-state voltage-level overshoots. The flexibility of TVC enables a low-voltage migration path for advanced
designs to align with industry standards.
frequently asked questions (FAQs)
1.
Q: Can any of the transistors in the array be used as the reference transistor?
A: Yes, any transistor can be used as long as its V
BIAS
pin is connected to the GATE pin.
2.
Q: In the recommended operating conditions table of the data sheet, the typical V
BIAS
is 3.3 V.
Should V
BIAS
be equal to or greater than V
REF
on the reference transistor?
A: V
BIAS
is a variable that is determined by V
REF
. V
BIAS
is connected to V
DD
through a resistor to allow the
bias voltage to be controlled by V
REF
. V
DD
can be as high as 5.5 V. V
REF
needs to be at least 1 V less
than V
DDREF
on the reference transistor.
3.
Q: Do both A and B ports have 5-V I/O tolerance or is 5-V I/O tolerance provided only on the low-voltage
side?
A: Both ports are 5-V tolerant.
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
74TVC16222ADGGRE4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74TVC16222ADGVRE4
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74TVC16222ADGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74TVC16222ADGVR
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74TVC16222ADL
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74TVC16222ADLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
Addendum-Page 1
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50
4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
1
12
24
13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
38
24
16
4,90
5,10
3,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins MO-153
14/16/20/56 Pins MO-194
MECHANICAL DATA
MSSO001C JANUARY 1995 REVISED DECEMBER 2001
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040048 / E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
48
28
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0
8
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D JANUARY 1995 REVISED JANUARY 1998
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
4040078 / F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0
8
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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