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SN54HCT138, SN74HCT138
3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS171E - MARCH 1984 - REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D
Operating Voltage Range of 4.5 V to 5.5 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 80-
A Max I
CC
D
Typical t
pd
= 17 ns
D
4-mA Output Drive at 5 V
D
Low Input Current of 1
A Max
D
Inputs Are TTL-Voltage Compatible
D
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
D
Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
3
2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
Y1
Y2
NC
Y3
Y4
C
G2A
NC
G2B
G1
B
A
NC
Y6
Y5
V
Y0
Y7
GND
NC
SN54HCT138 . . . FK PACKAGE
(TOP VIEW)
CC
NC - No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G2A
G2B
G1
Y7
GND
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
SN54HCT138 . . . J OR W PACKAGE
SN74HCT138 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
The 'HCT138 devices are designed for high-performance memory-decoding or data-routing applications
requiring very short propagation delay times. In high-performance memory systems, these decoders can
minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable
circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical
access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP - N
Tube of 25
SN74HCT138N
SN74HCT138N
Tube of 40
SN74HCT138D
SOIC - D
Reel of 2500
SN74HCT138DR
HCT138
-40
C to 85
C
SOIC - D
Reel of 250
SN74HCT138DT
HCT138
-40
C to 85
C
SOP - NS
Reel of 2000
SN74HCT138NSR
HCT138
Tube of 90
SN74HCT138PW
TSSOP - PW
Reel of 2000
SN74HCT138PWR
HT138
TSSOP - PW
Reel of 250
SN74HCT138PWT
HT138
CDIP - J
Tube of 25
SNJ54HCT138J
SNJ54HCT138J
-55
C to 125
C
CFP - W
Tube of 150
SNJ54HCT138W
SNJ54HCT138W
-55 C to 125 C
LCCC - FK
Tube of 55
SNJ54HCT138FK
SNJ54HCT138FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HCT138, SN74HCT138
3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS171E - MARCH 1984 - REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low (G) and one active-high (G) enable inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires
only one inverter. An enable input can be used as a data input for demultiplexing applications.
FUNCTION TABLE
INPUTS
OUTPUTS
ENABLE
SELECT
OUTPUTS
G1
G2A
G2B
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
SN54HCT138, SN74HCT138
3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS171E - MARCH 1984 - REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
logic diagram (positive logic)
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
B
C
G1
G2A
G2B
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
1
2
3
6
4
5
15
14
13
12
11
10
9
7
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
-0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1)
20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to V
CC
)
25 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
CC
or GND
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
JA
(see Note 2): D package
73
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
67
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package
64
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
108
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
-65
C to 150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HCT138, SN74HCT138
3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS171E - MARCH 1984 - REVISED SEPTEMBER 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HCT138
SN74HCT138
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
4.5
5
5.5
V
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
2
2
V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
0.8
0.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
t/
v
Input transition rise/fall time
500
500
ns
TA
Operating free-air temperature
-55
125
-40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
C
SN54HCT138
SN74HCT138
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
VOH
VI = VIH or VIL
IOH = -20
A
4.5 V
4.4
4.499
4.4
4.4
V
VOH
VI = VIH or VIL
IOH = -4 mA
4.5 V
3.98
4.3
3.7
3.84
V
VOL
VI = VIH or VIL
IOL = 20
A
4.5 V
0.001
0.1
0.1
0.1
V
VOL
VI = VIH or VIL
IOL = 4 mA
4.5 V
0.17
0.26
0.4
0.33
V
II
VI = VCC or 0
5.5 V
0.1
100
1000
1000
nA
ICC
VI = VCC or 0,
IO = 0
5.5 V
8
160
80
A
ICC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
5.5 V
1.4
2.4
3
2.9
mA
Ci
4.5 V
to 5.5 V
3
10
10
10
pF
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25
C
SN54HCT138
SN74HCT138
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
A, B, or C
Any Y
4.5 V
23
36
54
45
tpd
A, B, or C
Any Y
5.5 V
17
32
49
34
ns
tpd
Enable
Any Y
4.5 V
22
33
50
42
ns
Enable
Any Y
5.5 V
18
30
45
38
tt
Y
4.5 V
12
15
22
19
ns
tt
Y
5.5 V
11
14
20
17
ns
operating characteristics, T
A
= 25
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
No load
85
pF
SN54HCT138, SN74HCT138
3 LINE TO 8 LINE DECODERS/DEMULTIPLEXERS
SCLS171E - MARCH 1984 - REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
1.3 V
1.3 V
0.3 V
0.3 V
2.7 V
2.7 V
3 V
0 V
tr
tf
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V
1.3 V
10%
10%
90%
90%
3 V
VOH
VOL
0 V
tr
tf
Input
In-Phase
Output
1.3 V
tPLH
tPHL
1.3 V
1.3 V
10%
10%
90%
90%
VOH
VOL
tr
tf
tPHL
tPLH
Out-of-Phase
Output
Test
Point
From Output
Under Test
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
1 MHz, ZO = 50
, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
CL = 50 pF
(see Note A)
Figure 1. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MCFP004A JANUARY 1995 REVISED FEBRUARY 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
W (R-GDFP-F16)
CERAMIC DUAL FLATPACK
0.360 (9,14)
0.250 (6,35)
9
8
16
1
0.245 (6,22)
0.004 (0,10)
0.026 (0,66)
4 Places
0.015 (0,38)
0.055 (1,40)
0.370 (9,40)
0.006 (0,15)
0.045 (1,14)
Base and Seating Plane
0.005 (0,13) MIN
0.019 (0,48)
0.430 (10,92)
0.285 (7,24)
0.080 (2,03)
4040180-3 / C 02/02
0.305 (7,75) MAX
0.050 (1,27)
0.360 (9,14)
0.250 (6,35)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP-1F16 and JEDEC MO-092AC
MECHANICAL DATA

MLCC006B OCTOBER 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
4040140 / D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MIN
MAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)
(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
13
14
15
16
18
17
11
10
8
9
7
5
4
3
2
0.020 (0,51)
0.010 (0,25)
6
1
28
26
27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
BB
AC
AD
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
Gauge Plane
0.015 (0,38)
0.430 (10,92) MAX
20
1.060
(26,92)
0.940
(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775
(19,69)
(18,92)
0.745
A MIN
DIM
A MAX
PINS **
(23,37)
(21,59)
Seating Plane
14/18 PIN ONLY
20 pin vendor option
4040049/E 12/2002
9
8
0.070 (1,78)
A
0.045 (1,14)
0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
M
0.010 (0,25)
0.100 (2,54)
16 PINS SHOWN
MS-100
VARIATION
AA
C
D
D
D
0.030 (0,76)
0.045 (1,14)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
MECHANICAL DATA

MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
MECHANICAL DATA

MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
20
16
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0
8
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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Copyright
2003, Texas Instruments Incorporated