Burr Brown Products
from Texas Instruments
FEATURES
APPLICATIONS
DESCRIPTION
_
+
CDAC
SAR
Conversion
and
Control
Logic
Comparator
12/10/8 BIT ADC
VIN
REF/V
DD
CS
SCLK
SDO
GND
S/H
ADS7866
ADS7867
ADS7868
SLAS465 JUNE 2005
1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE
ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE
The sampling, conversion, and activation of digital
output SDO are initiated on the falling edge of CS.
Single 1.2-V to 3.6-V Supply Operation
The serial clock SCLK is used for controlling the
High Throughput
conversion rate and shifting data out of the converter.
Furthermore, SCLK provides a mechanism to allow
200/240/280KSPS for 12/10/8-Bit V
DD
1.6 V
digital host processors to synchronize with the con-
100/120/140KSPS for 12/10/8-Bit V
DD
1.2 V
verter.
These
converters
interface
with
1.5LSB INL, 12-Bit NMC (ADS7866)
micro-processors or DSPs through a high-speed SPI
71 dB SNR, 83 dB THD at f
IN
= 30 kHz
compatible serial interface. There are no pipeline
delays associated with the device.
(ADS7866)
Synchronized Conversion with SCLK
The minimum conversion time is determined by the
frequency of the serial clock input, SCLK, while the
SPI Compatible Serial Interface
maximum frequency of SCLK is determined by the
No Pipeline Delays
minimum sampling time required to charge the input
Low Power
capacitance
to
12/10/8-bit
accuracy
for
the
ADS7866/67/68,
respectively.
The
maximum
1.39 mW Typ at 200 KSPS, V
DD
= 3.6 V
throughput is determined by how often a conversion
0.39 mW Typ at 200 KSPS, V
DD
= 1.6 V
is initiated when the minimum sampling time is met
0.22 mW Typ at 100 KSPS, V
DD
= 1.2 V
and the maximum SCLK frequency is used. Each
Auto Power-Down: 8 nA Typ, 300 nA Max
device automatically powers down after each conver-
sion, which allows each device to save power when
0 V to V
DD
Unipolar Input Range
the throughput is reduced while using the maximum
6-Pin SOT-23 Package
SCLK frequency.
The converter reference is taken internally from the
supply. Hence, the analog input range for these
Battery Powered Systems
devices is 0 V to V
DD
.
Isolated Data Acquisition
These devices are available in a 6-pin SOT-23
Medical Instruments
package and are characterized over the industrial
Portable Communication
40
C to 85
C temperature range.
Portable Data Acquisition Systems
Automatic Test Equipment
The
ADS7866/67/68
are
low
power,
miniature,
12/10/8-bit A/D converters each with a unipolar,
single-ended input. These devices can operate from a
single 1.6 V to 3.6 V supply with a 200-KSPS
throughput for ADS7866. In addition, these devices
can maintain at least a 100-KSPS throughput with a
supply as low as 1.2 V.
Micro-Power Miniature SAR Converter Family
RESOLUTION/SPEED
< 200 KSPS
1 MSPS 1.25 MSPS
12-Bit
ADS7866 (1.2 V
DD
to 3.6 V
DD
)
ADS7886 (2.35 V
DD
to 5.25 V
DD
)
10-Bit
ADS7867 (1.2 V
DD
to 3.6 V
DD
)
ADS7887 (2.35 V
DD
to 5.25 V
DD
)
8-Bit
ADS7868 (1.2 V
DD
to 3.6 V
DD
)
ADS7888 (2.35 V
DD
to 5.25 V
DD
)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
ADS7866
ADS7867
ADS7868
SLAS465 JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
MAXIMUM
MAXIMUM
NO MISSING
PACKAGE
SPECIFIED
TRANSPORT
INTEGRAL
DIFFERENTIAL
CODES
PACKAGE
PACKAGE
ORDERING
MODEL
MARKING
TEMPERATURE
MEDIA,
LINEARITY
LINEARITY
RESOLULTION
TYPE
DESIGNATOR
NUMBER
(SYMBOL)
RANGE
QUANTITY
(LSB)
(LSB)
(BIT)
ADS7866I
1.5
1/+1.5
12
SOT23-6
A66Y
DBV
40
C to 85
C
ADS7866IDBVT
Small tape and reel, 250
ADS7866I
1.5
1/+1.5
12
SOT23-6
A66Y
DBV
40
C to 85
C
ADS7866IDBVR
Tape and reel, 3000
ADS7867I
0.5
0.5
10
SOT23-6
A67Y
DBV
40
C to 85
C
ADS7867IDBVT
Small tape and reel, 250
ADS7867I
0.5
0.5
10
SOT23-6
A67Y
DBV
40
C to 85
C
ADS7867IDBVR
Tape and reel, 3000
ADS7868I
0.5
0.5
8
SOT23-6
A68Y
DBV
40
C to 85
C
ADS7868IDBVT
Small tape and reel, 250
ADS7868I
0.5
0.5
8
SOT23-6
A68Y
DBV
40
C to 85
C
ADS7868IDBVR
Tape and reel, 3000
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
over operating free-air temperature range (unless otherwise noted)
RATING
V
DD
to GND
0.3 V to 4.0 V
Analog input voltage to GND
0.3 V to V
DD
+ 0.3 V
Digital input voltage to GND
0.3 V to 4.0 V
Digital output voltage to GND
0.3 V to V
DD
+ 0.3 V
T
A
Operating free-air temperature range
40
C to 85
C
T
STORAGE
Storage temperature range
65
C to 150
C
T
J
Junction temperature
150
C
JA
Thermal impedance
110.9
C/W
SOT-23 Package
JC
Thermal impedance
22.31
C/W
Vapor phase (1040 sec)
250
C
Lead temperature,
soldering
Infrared (1030 sec)
260
C
ESD
3 kV
2
www.ti.com
SPECIFICATIONS, ADS7866
ADS7866
ADS7867
ADS7868
SLAS465 JUNE 2005
At 40
C to 85
C, f
SAMPLE
= 200 KSPS and f
SCLK
= 3.4 MHz if 1.6 V
V
DD
3.6 V; f
SAMPLE
= 100 KSPS and f
SCLK
= 1.7 MHz if
1.2 V
V
DD
< 1.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
Resolution
12
Bits
No missing codes
12
Bits
Integral linearity
1.5
1.5
LSB
(1)
Differential linearity
1
1.5
LSB
1.2 V
V
DD
< 1.6 V
2
2
Offset error
(2)
LSB
1.6 V
V
DD
3.6 V
3
3
1.2 V
V
DD
< 1.6 V
2
2
Gain error
(3)
LSB
1.6 V
V
DD
3.6 V
2
2
1.2 V
V
DD
< 1.6 V
2.5
2.5
Total unadjusted error
(4)
LSB
1.6 V
V
DD
3.6 V
3.5
3.5
SAMPLING DYNAMICS (See Timing Characteristics Section)
t
CONVERT
Conversion time
f
SCLK
= 3.4 MHz, 13 SCLK cycles
3.82
s
t
SAMPLE
Acquisition time
f
SCLK
= 3.4 MHz, 1.6 V
V
DD
3.6 V
0.64
s
f
SAMPLE
Throughput rate
f
SCLK
= 3.4 MHz, 1.6 V
V
DD
3.6 V
200
KSPS
Aperture delay
10
ns
Aperture jitter
40
ps
DYNAMIC CHARACTERISTICS
f
IN
= 30 kHz, 1.2 V
V
DD
< 1.6 V
68
Signal-to-noise
SINAD
dB
and distortion
f
IN
= 30 kHz, 1.6 V
V
DD
3.6 V
69
70
f
IN
= 30 kHz, 1.2 V
V
DD
< 1.6 V
70
SNR
Signal-to-noise ratio
dB
f
IN
= 30 kHz, 1.6 V
V
DD
3.6 V
70
71
f
IN
= 30 kHz, 1.2 V
V
DD
< 1.6 V
70
THD
Total harmonic distortion
(5)
dB
f
IN
= 30 kHz, 1.6 V
V
DD
3.6 V
83
f
IN
= 30 kHz, 1.2 V
V
DD
< 1.6 V
75
Spurious free dynamic
SFDR
dB
range
f
IN
= 30 kHz, 1.6 V
V
DD
3.6 V
85
At 0.1 dB, 1.2 V
V
DD
< 1.6 V
2
At 0.1 dB, 1.6 V
V
DD
3.6 V
4
Full-power bandwidth
(6)
MHz
At 3 dB, 1.2 V
V
DD
< 1.6 V
3
At 3 dB, 1.6 V
V
DD
3.6 V
8
ANALOG INPUT
Full-scale input span
(7)
VIN GND
0
V
DD
V
C
S
Input capacitance
12
pF
Input leakage current
1
1
A
DIGITAL INPUT
Logic family , CMOS
1.2 V
V
DD
< 1.6 V
0.7
V
DD
3.6
1.6 V
V
DD
< 1.8 V
0.7
V
DD
3.6
V
IH
Input logic high level
V
1.8 V
V
DD
< 2.5 V
0.7
V
DD
3.6
2.5 V
V
DD
3.6 V
2
3.6
(1)
LSB = Least Significant BIt
(2)
The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
(3)
The difference in the last code transition 011...111 to 111...111 from the ideal value of V
DD
- 1 LSB with the offset error removed.
(4)
The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
offset error and gain error are included.
(5)
The 2nd through 10th harmonics are used to determine THD.
(6)
Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
(7)
Ideal input span which does not include gain or offset errors.
3
www.ti.com
SPECIFICATIONS, ADS7867
ADS7866
ADS7867
ADS7868
SLAS465 JUNE 2005
At 40
C to 85
C, f
SAMPLE
= 240 KSPS and f
SCLK
= 3.4 MHz if 1.6 V
V
DD
3.6 V; f
SAMPLE
= 120 KSPS and f
SCLK
= 1.7 MHz if
1.2 V
V
DD
< 1.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
Resolution
10
Bits
No missing codes
10
Bits
Integral linearity
0.5
0.5
LSB
(1)
Differential linearity
0.5
0.5
LSB
1.2 V
V
DD
< 1.6 V
0.75
0.75
Offset error
(2)
LSB
1.6 V
V
DD
3.6 V
1
1
1.2 V
V
DD
< 1.6 V
0.5
0.5
Gain error
(3)
LSB
1.6 V
V
DD
3.6 V
0.5
0.5
1.2 V
V
DD
< 1.6 V
2
2
Total unadjusted error
(4)
LSB
1.6 V
V
DD
3.6 V
2
2
SAMPLING DYNAMICS (See Timing Characteristics Section)
t
CONVERT
Conversion time
f
SCLK
= 3.4 MHz, 11 SCLK cycles
3.235
s
t
SAMPLE
Acquisition time
f
SCLK
= 3.4 MHz, 1.6 V
V
DD
3.6 V
0.64
s
f
SAMPLE
Throughput rate
f
SCLK
= 3.4 MHz, 1.6 V
V
DD
3.6 V
240
KSPS
Aperture delay
10
ns
Aperture jitter
40
ps
DYNAMIC CHARACTERISTICS
f
SAMPLE
= 100 KSPS, f
IN
= 30 kHz, 1.2 V
V
DD
< 1.6 V
61
Signal-to-noise
SINAD
dB
and distortion
f
SAMPLE
= 200 KSPS, f
IN
= 30 kHz, 1.6 V
V
DD
3.6 V
61
61.7
f
SAMPLE
= 100 KSPS, f
IN
= 30 kHz, 1.2 V
V
DD
< 1.6 V
61.5
SNR
Signal-to-noise ratio
dB
f
SAMPLE
= 200 KSPS, f
IN
= 30 kHz, 1.6 V
V
DD
3.6 V
61.8
f
SAMPLE
= 100 KSPS, f
IN
= 30 kHz, 1.2 V
V
DD
< 1.6 V
-68
THD
Total harmonic distortion
(5)
dB
f
SAMPLE
= 200 KSPS, f
IN
= 30 kHz, 1.6 V
V
DD
3.6 V
-78
-72
f
SAMPLE
= 100 KSPS, f
IN
= 30 kHz, 1.2 V
V
DD
< 1.6 V
73
SFDR
Spurious free dynamic range
dB
f
SAMPLE
= 200 KSPS, f
IN
= 30 kHz, 1.6 V
V
DD
3.6 V
74
80
At 0.1 dB, 1.2 V
V
DD
< 1.6 V
2
At 0.1 dB, 1.6 V
V
DD
3.6 V
4
Full-power bandwidth
(6)
MHz
At 3 dB, 1.2 V
V
DD
< 1.6 V
3
At 3 dB, 1.6 V
V
DD
3.6 V
8
ANALOG INPUT
Full-scale input span
(7)
VIN GND
0
V
DD
V
C
S
Input capacitance
12
pF
Input leakage current
1
1
A
DIGITAL INPUT
Logic family, CMOS
1.2 V
V
DD
< 1.6 V
0.7
V
DD
3.6
1.6 V
V
DD
< 1.8 V
0.7
V
DD
3.6
V
IH
Input logic high level
V
1.8 V
V
DD
< 2.5 V
0.7
V
DD
3.6
2.5 V
V
DD
3.6 V
2
3.6
(1)
LSB = Least Significant BIt
(2)
The difference in the first code transition 000...000 to 000...001 from the ideal value of GND + 1 LSB.
(3)
The difference in the last code transition 011...111 to 111...111 from the ideal value of V
DD
- 1 LSB with the offset error removed.
(4)
The absolute difference from the ideal transfer function of the converter. This specification is similar to INL error except the effects of
offset error and gain error are included.
(5)
The 2nd through 10th harmonics are used to determine THD.
(6)
Input frequency where the amplitude of the digitized signal has decreased by 0.1 dB or 3 dB.
(7)
Ideal input span which does not include gain or offset errors.
5
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