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Электронный компонент: ONET1191PRGTR

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FEATURES
APPLICATIONS
DESCRIPTION
ONET1191P
SLLS754 SEPTEMBER 2006
11.3-Gbps Limiting Amplifier
10 Gigabit Ethernet Optical Transmitters
Up to 11.3-Gbps Operation
8
and 10
Fibre Channel Optical
Loss-of-Signal Detection (LOS)
Transmitters
Adjustable Output Voltage
SONET OC-192/SDH-64 Optical Transmitters
Low Power Consumption
XFP and SFP+ Transceiver Modules
Input Offset Cancellation
XENPAK, XPAK, X2 and 300-Pin MSA
CML Data Outputs With On-Chip, 50-
Transponder Modules
Back-Termination to VCC
Cable Driver and Receiver
Single 3.3 V Supply
Surface-Mount, Small-Footprint, 3-mm
3-mm, 16-Pin QFN Package
The ONET1191P is a high-speed, 3.3-V limiting amplifier for copper-cable and fiber-optic applications with data
rates up to 11.3 Gbps.
This device provides a gain of about 40 dB which ensures a fully differential output swing for input signals as low
as 5 mV
pp
. The output amplitude can be adjusted from 400 mV
pp
to 700 mV
pp
. Loss-of-signal detection and
output disable are also provided.
The part is available in a small-footprint, 3-mm
3-mm, 16-pin QFN package, typically dissipates less than 110
mW, and is characterized for operation from 40
C to 85
C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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BLOCK DIAGRAM
DIN+
DIN
COC+
COC
50 W
50 W
DC Feedback Stage
Loss of Signal Detection
VCC
GND
DOUT+
DISABLE
DOUT
VAR
LOS
+
+
TH
+
+
B0067-02
Bandgap Voltage
Reference and
Bias Current Generation
8 dB
Gain Stage
20 dB
Gain Stage
12 dB
Gain Stage
Peak
Detector
Peak
Detector
HIGH-SPEED DATA PATH
LOSS-OF-SIGNAL DETECTION
ONET1191P
SLLS754 SEPTEMBER 2006
A simplified block diagram of the ONET1191P is shown in
Figure 1
.
This compact, low-power, 11.3-Gbps limiting amplifier consists of a high-speed data path with offset cancellation
(dc feedback), a loss-of-signal detection block using two peak detectors, and a band-gap voltage reference and
bias current generation block.
Figure 1. Simplified Block Diagram of the ONET1191P
The high-speed data signal is applied to the data path by means of the input signal pins, DIN+/DIN. The data
path consists of a 12-dB input gain stage with 2
50-
on-chip line-termination resistors, a second gain stage
with 20 dB of gain, and a variable-gain output stage which provides another 8 dB of gain. The amplified data
output signal is available at the output pins DOUT+/DOUT, which include on-chip 2
50-
back-termination to
VCC. The output amplitude can be adjusted between 400 mV
pp
and 700 mV
pp
by connecting an external resistor
between the VAR pin and ground (GND).
A dc feedback stage compensates for internal offset voltages and thus ensures proper operation even for very
small input data signals. This stage is driven by the output signal of the second gain stage. The signal is
low-pass filtered, amplified, and fed back to the input of the first gain stage via the on-chip, 50-
termination
resistors. The required low-frequency cutoff is determined by an external 0.1
F capacitor, which must be
differentially connected to the COC+/COC pins.
The peak values of the input signal and output signal of the first gain stage are monitored by two peak detectors.
The peak values are compared to a predefined loss-of-signal threshold voltage inside the loss-of-signal
detection block. As a result of the comparison, the LOS signal, which indicates that the input signal amplitude is
below the defined threshold level, is generated.
The threshold voltage can be set within a certain range by means of an external resistor connected between the
TH pin and ground.
2
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BAND-GAP VOLTAGE AND BIAS GENERATION
PACKAGE
1
2
3
4
VCC
COC
VCC
COC+
GND
DIN+
GND
DIN
12
11
10
9
16
VAR
GND
DISABLE
DOUT+
LOS
DOUT
TH
GND
15
14
13
5
6
7
8
P0019-05
EP
RGT PACKAGE
(TOP VIEW)
ONET1191P
SLLS754 SEPTEMBER 2006
The ONET1191P limiting amplifier is supplied by a single 3.3-V supply voltage connected to the VCC pins. This
voltage is referred to ground (GND).
On-chip band-gap voltage circuitry generates a reference voltage, independent of supply voltage, from which all
other internally required voltages and bias currents are derived.
For the ONET1191P, a small-footprint, 3-mm
3-mm, 16-pin QFN package, with a lead pitch of 0,5 mm, is
used. The pinout is shown in
Figure 2
.
Figure 2. Pinout of ONET1191P in a 3-mm
3-mm, 16-Pin QFN Package
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
Offset cancellation filter capacitor plus terminal. An external 0.1
F filter capacitor must be
COC+
6
Analog
connected between this pin and COC (pin 5).
Offset cancellation filter capacitor minus terminal. An external 0.1
F filter capacitor must be
COC
5
Analog
connected between this pin and COC+ (pin 6).
Noninverted data input. On-chip, 50-
terminated to COC+. Differentially 100-
terminated
DIN+
7
Analog input
to DIN.
Inverted data input. On-chip, 50-
terminated to COC. Differentially 100-
terminated to
DIN
8
Analog input
DIN+.
DISABLE
11
CMOS input
Disables the output stage when set to a high level
DOUT+
15
CML out
Noninverted data output. On-chip, 50-
back-terminated to VCC.
DOUT
14
CML out
Inverted data output. On-chip, 50-
back-terminated to VCC.
3, 4, 13, 16,
GND
Supply
Circuit ground. Exposed die pad (EP) must be grounded.
EP
Open-drain
High level indicates that the input signal amplitude is below the programmed threshold level.
LOS
10
MOS
Open-drain output. Requires an external 10-k
pullup resistor to VCC for proper operation.
TH
9
Analog input
LOS threshold adjustment with resistor to GND
Variable output amplitude control. Output amplitude can be reduced to 400 mV
pp
by
VAR
12
Analog input
grounding the VAR pin. Output amplitude can be set from 400 mV
pp
to 700 mV
pp
by
connecting a 0 to 100-k
resistor to GND or leaving the pin open.
VCC
1, 2
Supply
3.3-V
10% supply voltage
3
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
ONET1191P
SLLS754 SEPTEMBER 2006
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
V
CC
Supply voltage
(2)
0.3 to 4
V
V
DIN+
, V
DIN
Voltage at DIN+, DIN
(2)
0.5 to 4
V
V
LOS
, V
COC+
, V
COC
, V
TH
, V
DOUT+
,
Voltage at LOS, COC+, COC, TH, DOUT+, DOUT
(2)
0.3 to 4
V
V
DOUT
V
DIN,DIFF
Differential voltage between DIN+ and DIN
1.25
V
I
LOS
Current into LOS
1
mA
I
DIN+
, I
DIN
, I
DOUT+
, I
DOUT
Continuous current at inputs and outputs
20
mA
ESD
ESD rating at all pins
1.5
kV (HBM)
T
J,max
Maximum junction temperature
125
C
T
STG
Storage temperature range
65 to 85
C
T
A
Characterized free-air operating temperature range
40 to 85
C
T
LEAD
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values are with respect to network ground terminal.
MIN
TYP
MAX
UNIT
V
CC
Supply voltage
2.9
3.3
3.6
V
T
A
Operating free-air temperature
40
85
C
Disable input high voltage
2
V
Disable input low voltage
0.25
V
Optimum LOS threshold resistor
32
62
k
R
VAR
range
0
open
k
over recommended operating conditions, outputs connected to a 50-
load, R
VAR
= open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
CC
Supply voltage
2.9
3.3
3.6
V
I
VCC
Supply current
DISABLE = LOW
33
49
mA
R
IN
Data input resistance
Single-ended to COC pins
50
R
OUT
Data output resistance
Single-ended, referenced to V
CC
50
Voltage at TH pin
1.25
V
LOS HIGH voltage
10-k
pullup to V
CC
, I
SOURCE
= 50
A
2.4
LOS LOW voltage
10-k
pullup to V
CC
, I
SINK
= 200
A
0.5
V
4
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AC ELECTRICAL CHARACTERISTICS
ONET1191P
SLLS754 SEPTEMBER 2006
over recommended operating conditions, outputs connected to a 50-
load, R
VAR
= open (unless otherwise noted). Typical
operating condition is at V
CC
= 3.3 V and T
A
= 25
C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
3dB-H
High-frequency 3-dB bandwidth
8
11
15
GHz
f
3dB-L
Low-frequency 3-dB bandwidth
C
OC
= 0.1
F, ac coupling capacitors = 0.1
F
30
kHz
K28.5 at 11.3 Gbps, BER < 10
12
2.5
5
v
IN,MIN
Data input sensitivity
mV
pp
V
OD-min
0.95
V
OD
(output limited)
10
20
A
Small-signal gain
34
40
44
dB
V
IN,MAX
Data input overload
2000
mV
pp
V
IN
= 5 mV
pp
, K28.5 at 11.3 Gbps
4
7
DJ
Deterministic jitter
ps
pp
V
IN
= 20 mV
pp
, K28.5 at 11.3 Gbps
4
9
Input = 5 mV
pp
1.6
RJ
Random jitter
ps
RMS
Input = 20 mV
pp
0.7
V
IN
20 mV
pp
, DISABLE = LOW
600
700
900
V
OD
Differential data output voltage
mV
pp
DISABLE = HIGH
25
100
t
r
Output rise time
20% to 80%, V
IN
20 mV
PP
25
35
ps
t
f
Output fall time
20% to 80%, V
IN
20 mV
PP
25
35
ps
K28.5 pattern at 10.7 Gbps, R
TH
= 62 k
40
V
TH
LOS assert threshold range
mV
pp
K28.5 pattern at 10.7 Gbps, R
TH
= 32 k
65
Versus temperature
3
dB
LOS threshold variation
Versus supply voltage V
CC
1
dB
LOS hysteresis
K28.5 pattern at 11.3 Gbps
1.5
7
dB
t
LOS_AST
LOS assert time
1300
2000
ns
t
LOS, DEA_
LOS deassert time
120
ns
t
DIS
Disable response time
90
ns
5
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TYPICAL OPERATION CHARACTERISTICS
V
ID
- Differential Input Voltage - mV
pp
0
100
200
300
400
500
600
700
800
0
5
10
15
20
V
O
D
- Differential Output V
oltage - mV
p
p
G002
0
5
10
15
20
25
30
35
40
45
50
SDD21 - Gain - dB
f - Frequency - GHz
G001
0.1
100
1
10
-35
-30
-25
-20
-15
-10
-5
0
SDD22 - Differential Output Return Gain - dB
f - Frequency - GHz
G004
0.1
100
1
10
-35
-30
-25
-20
-15
-10
-5
0
SDD1
1 - Differential Input Return Gain - dB
f - Frequency - GHz
G003
0.1
100
1
10
ONET1191P
SLLS754 SEPTEMBER 2006
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25
C, and R
VAR
= open (unless otherwise noted)
FREQUENCY RESPONSE
TRANSFER FUNCTION
Figure 3.
Figure 4.
DIFFERENTIAL INPUT RETURN GAIN
DIFFERENTIAL OUTPUT RETURN GAIN
vs
vs
FREQUENCY
FREQUENCY
Figure 5.
Figure 6.
6
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V
ID
- Differential Input Voltage - mV
pp
0
1
2
3
4
5
6
7
8
9
10
0
400
800
1200
1600
2000
Deterministic Jitter - ps
G006
V
ID
- Differential Input Voltage - mV
pp
0
1
2
3
4
Bit-Error Ratio
10
-27
10
0
10
-3
10
-6
10
-12
10
-15
10
-18
10
-21
10
-24
G005
10
-9
V
ID
- Differential Input Voltage - mV
pp
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
10
20
30
40
50
60
70
80
90
100
Random Output Jitter - ps
G007
0
50
100
150
200
250
300
350
400
0
10
20
30
40
50
60
70
80
90
100
LOS Assert/Deassert V
oltage - mV
p
p
LOS Deassert Voltage
LOS Assert Voltage
G008
R
TH
- Threshold Resistance - k
ONET1191P
SLLS754 SEPTEMBER 2006
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25
C, and R
VAR
= open (unless otherwise noted)
BIT-ERROR RATIO
DETERMINISTIC JITTER
vs
vs
INPUT AMPLITUDE (11.3 GBPS)
INPUT AMPLITUDE
Figure 7.
Figure 8.
RANDOM JITTER
LOS ASSERT/DEASSERT VOLTAGE
vs
vs
INPUT AMPLITUDE
THRESHOLD RESISTANCE
Figure 9.
Figure 10.
7
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R
VAR
- Variable Resistance - k
0
100
200
300
400
500
600
700
800
0
10
20
30
40
50
60
70
80
90
100
V
I
D
- Differential Output V
oltage - mV
p
p
G010
0
1
2
3
4
5
6
0
10
20
30
40
50
60
70
80
90
100
LOS Hysteresis - dB
G009
R
TH
- Threshold Resistance - k
G012
100 mV/ Div
15 ps / Div
G011
100 mV/ Div
15 ps / Div
ONET1191P
SLLS754 SEPTEMBER 2006
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25
C, and R
VAR
= open (unless otherwise noted)
LOS HYSTERESIS
OUTPUT AMPLITUDE
vs
vs
THRESHOLD RESISTANCE
R
VAR
Figure 11.
Figure 12.
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND MINIMUM INPUT VOLTAGE (5 mV
pp
)
AND MAXIMUM INPUT VOLTAGE (2000 mV
pp
)
Figure 13.
Figure 14.
8
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G014
100 mV/ Div
20 ps / Div
G013
100 mV/ Div
20 ps / Div
ONET1191P
SLLS754 SEPTEMBER 2006
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25
C, and R
VAR
= open (unless otherwise noted)
OUTPUT EYE-DIAGRAM AT 8.5 GBPS
OUTPUT EYE-DIAGRAM AT 8.5 GBPS
AND MINIMUM INPUT VOLTAGE (5 mV
pp
)
AND MAXIMUM INPUT VOLTAGE (2000 mV
pp
)
Figure 15.
Figure 16.
9
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APPLICATION INFORMATION
DIN+
DIN
DISABLE
GND
DOUT+
DOUT
VCC
S0099-03
L
O
S
COC+
DIN+
T
H
DOUT
DOUT+
VCC
G
N
D
G
N
D
COC
GND
GND
V
C
C
V
A
R
D
I
S
A
B
L
E
DIN
LOS
ONET1191P
16-Pin QFN
C1
0.1 F
m
C5
0.1 F
m
C4
0.1 F
m
C3
0.1 F
m
C6
0.1 F
m
R
12 k
62 k
TH
W
W
R
10 k
1
W
R
0
Open
VAR
W
C2
0.1 F
m
L1
BLM11HA102SG
ONET1191P
SLLS754 SEPTEMBER 2006
Figure 17
shows a typical application circuit using the ONET1191P. The output amplitude can be adjusted with
R
VAR
and the LOS assert voltage is adjusted with R
TH
.
Figure 17. Basic Application Circuit
10
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
ONET1191PRGTR
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU
Level-2-260C-1 YEAR
ONET1191PRGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2006
Addendum-Page 1
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