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Электронный компонент: ONET1191VRGPTG4

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FEATURES
APPLICATIONS
DESCRIPTION
ONET1191V
SLLS750 AUGUST 2006
11.3-GBPS DIFFERENTIAL VCSEL DRIVER
10-Gigabit Ethernet Optical Transmitters
Up to 11.3-Gbps Operation
8
and 10
Fibre Channel Optical
Two-Wire Digital Interface
Transmitters
Digitally Selectable Modulation Current up to
SONET OC-192/SDH STM-64 Optical
40 mA
Transmitters
Digitally Selectable Bias Current up to 20 mA
XFP and SFP+ Transceiver Modules
Automatic Power Control (APC) Loop
XENPAK, XPAK, X2, and 300-Pin MSA
Supports Transceiver Management System
Transponder Modules
(TMS)
Programmable Input Equalizer
Includes Laser Safety Features
Analog Temperature Sensor Output
Single 3.3-V Supply
Operating Temperature 40
C to 85
C
Surface-Mount, Small-Footprint, 4-mm
4-mm, 20-Pin QFN Package
The ONET1191V is a high-speed, 3.3-V laser driver designed to directly modulate VCSELs at data rates up to
11.3 Gbps.
The device provides a two-wire serial interface which allows digital control of the modulation and bias currents,
eliminating the need for external components. An optional input equalizer can be used for equalization of up to
300 mm (12 inches) of microstrip or stripline transmission line on FR4 printed-circuit boards.
The ONET1191V includes an integrated automatic power-control (APC) loop as well as circuitry to support laser
safety and transceiver management systems.
The VCSEL driver is characterized for operation from 40
C to 85
C ambient temperatures and is available in a
small-footprint, 4-mm
4-mm, 20-pin QFN package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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BLOCK DIAGRAM
DIN+
DIN
GND
MOD+
MOD
Power-On Reset
GND
VCC
RESET
Equalizer
EQENB
EQENB
EQADJ
EQADJ
RESET
MODC
IMOD
MODR
ENA
MODC
MODR
ENA
FLT
VCC
SCK
SDA
DIS
SCK
SDA
DIS
FLT
BIAS
MONB
MONP
BIAS
MONB
MONP
PD
COMP
PD
COMP
AnalogReference
RZTC
BGV
TS
RZTC
BGV
TS
2-Wire Interface and Control Logic Clock
FAULT
PDP
BIASC
OLE
ENA
2
2
100 W
8
8
8
55 W
55 W
8
FAULT
PDP
BIASC
OLE
ENA
B0072-02
Bias Current
Generator
and
Automatic Power
Control Loop (APC)
Modulation
Current
Generator
High-Speed
Current
Modulator
Limiting
Gain Stage
ONET1191V
SLLS750 AUGUST 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
A simplified block diagram of the ONET1191V is shown in
Figure 1
.
The VCSEL driver consists of an equalizer, a high-speed current modulator, a modulation current generator,
power-on reset circuitry, a two-wire interface and control logic block, a bias current generator and automatic
power-control loop, and an analog reference block.
Figure 1. Simplified Block Diagram of the ONET1191V
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EQUALIZER
HIGH-SPEED CURRENT MODULATOR
MODULATION CURRENT GENERATOR
TWO-WIRE INTERFACE AND CONTROL LOGIC
ONET1191V
SLLS750 AUGUST 2006
The data signal can be applied to an input equalizer by means of the input signal pins DIN+/DIN, which provide
on-chip differential 100-
line termination. The equalizer is enabled by setting EQENB = 0 (bit 1 of register 0).
Equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line on FR4 printed circuit boards
can be achieved. The amount of equalization is digitally controlled by the two-wire interface and control logic
block and depends on the register settings EQADJ[0..7] (register 3). The equalizer can also be turned off and
bypassed by setting EQENB = 1. For details about the equalizer settings, see
Table 6
.
The output of the equalizer is applied to the high-speed current modulator. The limiting gain stage ensures
sufficient drive amplitude and edge speed for driving the current modulator differential pair.
The modulation current is sunk from the common-emitter node of the named differential pair by means of a
modulation current generator, which is digitally controlled by the two-wire interface and control logic block.
The collector nodes of the differential pair are connected to the output pins MOD+/MOD, which include on-chip
2
55-
back-termination to VCC. The 55-
back-termination helps to suppress signal distortion caused by
double reflections for VCSEL diodes with impedances from 50
through 75
.
The modulation current generator provides the current for the current modulator described previously. The circuit
is digitally controlled by the two-wire interface and control logic block.
An 8-bit-wide control bus, MODC, is used to set the desired modulation current. Furthermore, two modulation
current ranges are selected by means of the MODR signal. The ENA signal enables or disables the modulation
current generator.
The modulation current can be disabled by setting the DIS input pin to a high level. The modulation current is
also disabled in a fault condition if the fault detection enable register flag FLTEN is set.
For more information about the register functionality, see the register mapping description in
Table 6
.
The ONET1191V uses a two-wire serial interface for digital control. A simplified block diagram of this interface is
shown in
Figure 2
. The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serial
clock from a microcontroller, for example. Both inputs include 100-k
pullup resistors to VCC. For driving these
inputs, an open-drain output is recommended.
A write cycle consists of a START command, three address bits with MSB first, 8 data bits with MSB first, and a
STOP command. In idle mode, both the SDA and SCK lines are at a high level.
A START command is initiated by the falling edge of SDA with SCK at a high level, transitioning to a low level.
Bits are clocked into an 11-bit-wide shift register during the high level of the serial clock, SCK.
A STOP command is detected on the rising edge of SDA after SCK has changed from a low to a high level.
At the time of detection of a STOP command, the eight data bits from the shift register are copied to a selected
8-bit register. Register selection occurs according to the three address bits in the shift register, which are
decoded to eight independent select signals using an 3-to-8 decoder block.
In the ONET1191V, addresses 0 (000b) through 3 (011b) are used.
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111
110
101
100
011
010
001
000
Start
Stop
SDA
SCK
8
8
8
11-Bit Shift Register
8 Bits Data
3 Bits Addr
3
B0068-03
8
8
8-Bit Register
Control Functions (7 Bits)
Unused (1 Bit)
8-Bit Register
Modulation Current (8 Bits)
8-Bit Register
Bias Current (8 Bits)
8-Bit Register
Equalizer Setting (8 Bits)
Start/Stop
Detector
Logic
3-to-8Decoder
ONET1191V
SLLS750 AUGUST 2006
Figure 2. Simplified Two-Wire Interface Block Diagram
The timing definition for the serial data signal SDA and the serial clock signal SCK is shown in
Figure 3
. The
corresponding timing requirements are listed in
Table 1
.
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START
STOP
1
0
1
0
1
1
SDA
SCK
DTA
R
DTA
F
STRT
HLD
CLK
R
CLK
F
CLK
HI
DTA
HI
DTA
STP
DTA
WT
DTA
HLD
STOP
STP
T0077-01
REGISTER MAPPING
ONET1191V
SLLS750 AUGUST 2006
Figure 3. Two-Wire Interface Timing Diagram
Table 1. Two-Wire Interface Timing
PARAMETER
DESCRIPTION
MIN MAX
UNIT
STRT
HLD
START hold time
Time required from data falling edge to clock falling edge at START
10
ns
CLK
R
, DTA
R
Clock and data rise time
Clock and data rise time
10
ns
CLK
F
, DTA
F
Clock and data fall time
Clock and data fall time
10
ns
CLK
HI
Clock high time
Minimum clock high period
50
ns
DTA
HI
Data high time
Minimum data high period
100
ns
DTA
STP
Data setup time
Minimum time from data rising edge to clock rising edge
10
ns
DTA
WT
Data wait time
Minimum time from data falling edge to data rising edge
50
ns
DTA
HLD
Data hold time
Minimum time from clock falling edge to data falling edge
10
ns
STOP
STP
STOP setup time
Minimum time from clock rising edge to data rising edge at STOP
10
ns
The register mapping for the register addresses 0 (000b) through 3 (011b) are shown in
Table 2
through
Table 5
.
Table 6
describes the circuit functionality based on the register settings.
Table 2. Register 0 (000b) Mapping
address 0 (000b)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ENA
PDP
PDR
OLE
FLTEN
MODR
EQENB
Table 3. Register 1 (001b) Mapping
address 1 (001b)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MODC7
MODC6
MODC5
MODC4
MODC3
MODC2
MODC1
MODC0
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ONET1191V
SLLS750 AUGUST 2006
Table 4. Register 2 (010b) Mapping
address 2 (010b)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BIASC7
BIASC6
BIASC5
BIASC4
BIASC3
BIASC2
BIASC1
BIASC0
Table 5. Register 3 (011b) Mapping
address 3 (011b)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EQADJ7
EQADJ6
EQADJ5
EQADJ4
EQADJ3
EQADJ2
EQADJ1
EQADJ0
Table 6. Register Functionality
SYMBOL
REGISTER
FUNCTION
ENA
Enable
Enables chip when set to 1. Can be toggled low to reset a fault condition.
PDP
Photodiode polarity
Photodiode polarity bit:
1 = photodiode cathode connected to V
CC
0 = photodiode anode connected to GND
PDR
Photodiode current range
Photodiode current range bit:
With coupling ratio CR between VCSEL bias current and photodiode current = 30
1 = 12
A640
A with 2.5
A resolution
0 = 2.5
A12 8
A with 0.5
A resolution
OLE
Open loop enable
Open-loop enable bit:
1 = open-loop bias current control
0 = closed-loop bias current control
FLTEN
Fault detection enable
Fault detection enable bit:
1 = fault detection on
0 = fault detection off
MODR
Modulation tail current range
Laser modulation tail current range:
1 = 0 mA40 mA
0 = 0 mA20 mA
EQENB
Equalizer enable
Equalizer enable bit
1 = equalizer disabled
0 = equalizer enabled
MODC7
Modulation current bit 7 (MSB)
Modulation current setting:
MODC6
Modulation current bit 6
MODC5
Modulation current bit 5
MODR = 1:
MODC4
Modulation current bit 4
Modulation current up to 40 mA in 156-
A steps
MODC3
Modulation current bit 3
MODC2
Modulation current bit 2
MODR = 0:
MODC1
Modulation current bit 1
Modulation current up to 20 mA in 78-
A steps
MODC0
Modulation current bit 0 (LSB)
BIASC7
Bias current bit 7 (MSB)
Closed loop (APC):
BIASC6
Bias current bit 6
Coupling ratio CR = I
BIAS-VCSEL
/I
PD
BIASC5
Bias current bit 5
PDR = 0, BIASC = 0..255, I
BIAS-VCSEL
20 mA:
BIASC4
Bias current bit 4
I
BIAS-VCSEL
= 0.5
A
CR
BIASC
BIASC3
Bias current bit 3
PDR = 1, BIASC = 0..255, I
BIAS-VCSEL
20 mA:
BIASC2
Bias current bit 2
I
BIAS-VCSEL
= 2.5
A
CR
BIASC
BIASC1
Bias current bit 1
BIASC0
Bias current bit 0 (LSB)
Open loop: I
BIAS-VCSEL
= 75
A
BIASC
EQADJ7
Equalizer adjustment bit 7 (MSB)
Equalizer adjustment setting
EQADJ6
Equalizer adjustment bit 6
EQADJ5
Equalizer adjustment bit 5
EQENB = 1
EQADJ4
Equalizer adjustment bit 4
Equalizer is turned off and bypassed
EQADJ3
Equalizer adjustment bit 3
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BIAS CURRENT GENERATION AND APC LOOP
ANALOG REFERENCE
POWER-ON RESET AND REGISTER LOADING SEQUENCE
ONET1191V
SLLS750 AUGUST 2006
Table 6. Register Functionality (continued)
SYMBOL
REGISTER
FUNCTION
EQADJ2
Equalizer adjustment bit 2
EQENB = 0
EQADJ1
Equalizer adjustment bit 1
Maximum equalization for 0000 0000
EQADJ0
Equalizer adjustment bit 0 (LSB)
Minimum equalization for 1111 1111
The bias current generation and APC loop are controlled by means of the two-wire interface. In open-loop
operation, selected by setting OLE = 1 (bit 4 of register 0), the bias current is set directly by the 8-bit-wide
control word BIASC[0..7] (register 2). In automatic power-control mode, selected by setting OLE = 0, the bias
current depends on the register settings BIASC[0..7] and the coupling ratio (CR) between the VCSEL bias
current and the photodiode current. CR = I
BIAS-VCSEL
/I
PD
.
Two photodiode current ranges can be selected by means of the PDR register (bit 5 of register 0). The
photodiode range should be chosen to keep the laser bias control DAC close to the center of its range. This
keeps the laser bias current setpoint resolution high and the loop settling time constant within specification.
For details regarding the bias current setting in open- as well as in closed-loop mode, see
Table 6
.
In closed-loop mode, the photodiode polarity bit, PDP, must be set for common-anode or common-cathode
configuration to ensure proper operation. In open-loop mode, if a photodiode is present, the photodiode polarity
bit must be set to the opposite setting.
The ONET1191V VCSEL driver is supplied by a single 3.3-V
10% supply voltage connected to the VCC pins.
This voltage is referred to ground (GND).
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which
all other internally required voltages and bias currents are derived.
An external zero-temperature-coefficient resistor must be connected from the RZTC pin of the device to ground
(GND). This resistor is used to generate a precise, zero-TC current, which is required as a reference current for
the on-chip DACs.
In order to minimize the module component count, the ONET1191V provides an on-chip temperature sensor.
The output voltage of the temperature sensor is available at the TS pin.
The voltage is V
TS
= (8.2 mV/
C
TEMP) + 1140 mV, with TEMP given in
C.
Note that the voltage at TS is not buffered. As a result, TS can only drive capacitive loads.
The ONET1191V has power-on-reset circuitry, which ensures that all registers are reset to zero during startup.
After the power-on to initialize time (t
INIT1
), the internal registers are ready to be loaded. It is important that the
registers are loaded in the following order:
1. Bias current register (register 2, 010b)
2. Modulation current register (register 1, 001b)
3. Control register (register 0, 000b)
4. Loading of equalizer register (register 3, 011b) is not required.
The part is ready to transmit data after the initialize to transmit time t
INIT2
, assuming that the control register
enable bit ENA is set to 1 and the disable pin DIS is low.
The ONET1191V can be disabled using either the ENA control register bit or the disable pin DIS. In both cases,
the internal registers are not reset. After the disable pin DIS is set low and/or the enable bit ENA is set back
to 1, the part returns to its prior output settings.
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LASER SAFETY FEATURES AND FAULT RECOVERY PROCEDURE
PACKAGE
DIS
GND
RZTC
DIN+
TS
DIN
SCK
GND
SDA
FL
T
PD
VCC
COMP
MOD
MONP
MOD+
MONB
VCC
BGV
BIAS
RGP PACKAGE
(TOP VIEW)
1
2
3
4
5
15
14
EP
13
12
11
P0031-04
6
7
8
9
10
16
19
20
18
17
ONET1191V
SLLS750 AUGUST 2006
The ONET1191V provides built-in laser safety features. The following fault conditions are detected:
Voltage at MONB exceeds the voltage at RZTC (1.15V).
Photodiode current exceeds 150% of its set value.
Bias control DAC drops in value by more than 50% in one step.
If one or more fault conditions occur and the fault enable bit FLTEN is set to 1, the ONET1191V responds by:
Setting the VCSEL bias current to zero
Setting the modulation current to zero
Asserting and latching the FLT pin
Fault recovery is performed by the following procedure:
1. The disable pin DIS and/or the enable control bit ENA are toggled for at least the fault latch reset time
t
RESET
.
2. The FLT pin deasserts while the disable pin DIS is asserted or the enable bit ENA is deasserted.
3. If the fault condition is no longer present, the part returns to normal operation with its prior output settings
after the disable negate time t
ON
.
4. If the fault condition is still present, FLT reasserts once DIS is set to a low level, and the part does not return
to normal operation.
The ONET1191V is packaged in a small-footprint, 4-mm
4-mm, 20-pin QFN package with a lead pitch of
0,5 mm. The pinout is shown in
Figure 4
.
Figure 4. Pinout of ONET1191V in a 4-mm
4-mm, 20-Pin QFN Package
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ABSOLUTE MAXIMUM RATINGS
(1)
ONET1191V
SLLS750 AUGUST 2006
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Buffered bandgap voltage with open emitter output. This is a replica of the bandgap voltage at
BGV
11
Anolog-out
RZTC. For best matching, use the same 28.7-k
resistor to GND as used at RZTC.
Sinks average bias current for VCSEL in both APC and open-loop modes. Connect to laser cathode
BIAS
16
Analog
through an inductor. BLM15HG102SN1D recommended.
Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01-
F capacitor to
COMP
14
Analog
ground.
DIN+
7
Analog-in
Noninverted data input. On-chip differentially 100-
terminated to DIN. Must be ac-coupled.
DIN
8
Analog-in
Inverted data input. On-chip differentially 100-
terminated to DIN+. Must be ac-coupled.
DIS
1
Digital-in
Disables both bias and modulation currents when set to high state. Toggle to reset a fault condition.
FLT
10
Digital-out
Fault detection flag.
GND
6, 9, EP
Supply
Circuit ground. Exposed die pad (EP) must be grounded.
Noninverted modulation current output. AC-coupled to anode of common cathode VCSEL. On-chip,
MOD+
18
CML-out
55-
back-terminated to VCC.
Inverted modulation current output. AC-coupled through VCSEL matching resistor to ground (GND).
MOD
19
CML-out
On-chip, 55-
back-terminated to VCC.
Bias current monitor. Sources a 3.3% replica of the bias current. Connect an external resistor to
MONB
12
Analog-out
ground (GND). If the voltage at this pin exceeds 1.15 V, a fault is triggered. Typically, choose a
resistor to give MONB voltage of 0.8 V at the maximum desired bias current.
Photodiode current monitor. Sources a 50% replica of the photodiode current when PDR = 1 and a
MONP
13
Analog-out
250% replica when PDR = 0. Connect an external resistor (5 k
typical) to ground (GND).
Photodiode input. Pin can source or sink current dependent on PDP register setting. PDP = 0:
PD
15
Analog
source; PDP = 1: sink. Pin supplies >1.5-V reverse bias.
Connect external zero-TC, 28.7-k
resistor to ground (GND). Used to generate a defined zero-TC
RZTC
2
Analog
reference current for internal DACs.
SCK
4
Digital-in
Two-wire interface serial clock. Includes a 100-k
pullup resistor to VCC.
SDA
5
Digital-in
Two-wire interface serial data input. Includes a 100-k
pullup resistor to VCC.
TS
3
Analog-out
Temperature sensor output. Not buffered, capacitive load only.
VCC
17, 20
Supply
3.3-V
10% supply voltage
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
V
CC
Supply voltage
(2)
0.3 to 4
V
V
DIS
, V
RZTC
, V
TS
, V
SCK
, V
SDA
,
Voltage at DIS, RZTC, TS, SCK, SDA, DIN+, DIN, FLT, BGV, MONB,
0.3 to 4
V
V
DIN+
, V
DIN
, V
FLT
, V
BGV
, V
MONB
,
MONP, CAPC, PD, BIAS, MOD+, MOD
(2)
V
MONP
, V
CAPC
, V
PD
, V
BIAS
, V
MOD+
,
V
MOD
ESD
ESD rating at all pins
2
kV (HBM)
T
J,max
Maximum junction temperature
125
C
T
stg
Storage temperature range
65 to 85
C
T
A
Characterized free-air operating temperature range
40 to 85
C
T
LEAD
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions
is not implied. Exposure to absolutemaximumrated conditions for extended periods may affect device reliability.
(2)
All voltage values are with respect to network ground terminal.
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RECOMMENDED OPERATING CONDITIONS
ONET1191V
SLLS750 AUGUST 2006
MIN
NOM
MAX
UNIT
V
CC
Supply voltage
2.9
3.3
3.6
V
V
IH
Digital input high voltage
DIS, SCK, SDA
2
V
V
IL
Digital input low voltage
DIS, SCK, SDA
0.8
V
Bias output headroom voltage
V
BIAS
GND
300
mV
Control bit PDR = 1, step size = 2.5
A
12
640
Photodiode current range
A
Control bit PDR = 0 step size = 0.5
A
2.5
128
R
RZTC
Zero-TC resistor value
(1)
1.15-V bandgap bias across resistor
28.4
28.7
29
k
Control bit EQENA = 1
200
1200
V
IN
Differential input voltage swing
mVp-p
Control bit EQENA = 0
500
1200
t
R-IN
Input rise time
20%80%
30
55
ps
t
F-IN
Input fall time
20%80%
30
55
ps
T
A
Operating free-air temperature
40
85
C
(1)
Changing the value alters the DAC ranges.
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DC ELECTRICAL CHARACTERISTICS
ONET1191V
SLLS750 AUGUST 2006
Over recommended operating conditions; all values are for open-loop operation, I
MODC
= 12 mA, I
BIASC
= 6 mA, and
R
RZTC
= 28.7 k
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
CC
Supply voltage
2.9
3.3
3.6
V
I
MODC
= 24mA, I
BIASC
= 6 mA, including I
MODC
and I
BIASC
,
62
71
EQENB = 1
I
MODC
= 24mA, I
BIASC
= 6mA, including I
MODC
and I
BIASC
,
I
VCC
Supply current
70
mA
EQENB = 0
Disabled, DIS = high and/or control bit ENA = low,
35
42
EQENB = 1
R
IN
Data input resistance
Differential between DIN+/DIN
85
100
125
R
OUT
Data output resistance
Single-ended to V
CC
45
55
65
SCK, SDA, 100-k
pullup to V
CC
(1)
50
10
A
Digital input current
DIS
(1)
10
10
A
V
OH
Digital output high voltage
FLT, I
SOURCE
= 500
A
2.4
V
V
OL
Digital output low voltage
FLT, I
SINK
= 500
A
0.4
V
I
BIAS-DIS
Bias current during disable
100
A
I
BIAS-MIN
Minimum bias current
See
(2)
0.2
mA
I
BIAS-MAX
Maximum bias current
DAC set to maximum, open- and closed-loop
14
20
mA
Photodiode reverse bias
V
PD
APC active, I
PD
= max
1.5
2.3
V
voltage
Photodiode fault current
150%
level, percent of target I
PD
(1)
Temperature sensor voltage
40
C to 120
C junction temperature, capacitive load
V
TS
0.5
2.5
V
range
only, with midscale calibration.
(1)
Temperature sensor
With midscale calibration
(1)
3
C
accuracy
Temperature sensor drive
I
TS
Source or sink
(1)
1
1
A
current
I
MONP
/I
PD
with control bit PDR = 1
40%
50%
60%
Photodiode current monitor
ratio
I
MONP
/I
PD
with control bit PDR = 0
200%
265%
300%
Bias current monitor ratio
I
MONB
/I
BIAS
(nominal 1/30 = 3.3%). 1.2-k
sense resistor
2.7%
3.3%
4%
V
CC-RST
V
CC
reset threshold voltage
V
CC
voltage level which triggers power-on reset
(1)
2.4
2.5
2.8
V
V
CC
reset threshold voltage
V
CC-RSTHYS
100
(1)
mV
hysteresis
V
MONB-FLT
Fault voltage at MONB
Fault occurs if voltage at MONB exceeds value
1.05
1.15
1.25
V
(1)
Assured by simulation over process, supply, and temperature variation
(2)
The bias current can be set below the specified minimum according to the corresponding register setting described in the register
mapping section. However, in closed-loop operation, settings below the specified value may trigger a fault.
11
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AC ELECTRICAL CHARACTERISTICS
TYPICAL CHARACTERISTICS
T
A
- Free-Air Temperature -
C
0
2
4
6
8
-40
-20
0
20
40
60
80
100
Deterministic Jitter - ps
P
P
G002
Modulation Current - mA
0
2
4
6
8
5
10
15
20
Deterministic Jitter - ps
P
P
G001
ONET1191V
SLLS750 AUGUST 2006
Over recommended operating conditions with 50-
output load, open-loop operation, I
MODC
= 12 mA, I
BIASC
= 6 mA, and
R
RZTC
= 28.7 k
, unless otherwise noted. Typical operating condition is at V
CC
= 3.3 V and T
A
= 25
C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
r-OUT
Output rise time
20%80%, t
r-IN
< 40 ps, 50-
load
20
30
ps
t
f-OUT
Output fall time
20%80%, t
f-IN
< 40 ps, 50-
load
25
30
ps
Control bit MODR = 1, 50-
load
36
45
I
MOD-MAX
Maximum modulation current
mA
Control bit MODR = 0, 50-
load
18
27
Control bit MODR = 1, 50-
load
175
I
MOD-STEP
Modulation current step size
A
Control bit MODR = 0, 50-
load
100
Control bit EQENB = 1, K28.5 pattern at 11.3 Gbps
4
12
DJ
Deterministic output jitter
ps
p-p
Control bit EQENB = 0, K28.5 pattern at 11.3 Gbps,
10
20
maximum equalization with 300-mm FR4 trace
RJ
Random output jitter
50-
load
0.5
0.8
ps
RMS
APC
APC time constant
C
APC
= 0.01
F, I
PD
= 100
A, PD coupling ratio CR = 40
(1)
200
s
t
OFF
Transmitter disable time
Rising edge of DIS to I
BIAS
0.1
I
BIAS-NOMINAL
(1)
1
5
s
t
ON
Disable negate time
Falling edge of DIS to I
BIAS
0.9
I
BIAS-NOMINAL
(1)
1
ms
t
INIT1
Power-on to initialize
Power-on to registers ready to be loaded
1
10
ms
Register load STOP command to part ready to transmit valid
t
INIT2
Initialize to transmit
2
ms
data
(1)
t
RESET
DIS pulse duration
Time DIS must held high to reset part
(1)
100
ns
t
FAULT
Fault assert time
Time from fault condition to FLT high
(1)
50
s
(1)
Assured by simulation over process, supply, and temperature variation
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25
C, I
BIASC
= 6 mA, I
MODC
= 12 mA, MODR = 0 (unless otherwise noted).
DETERMINISTIC JITTER
DETERMINISTIC JITTER
vs
vs
MODULATION CURRENT
TEMPERATURE
Figure 5.
Figure 6.
12
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T
A
- Free-Air Temperature -
C
0.0
0.1
0.2
0.3
0.4
0.5
-40
-20
0
20
40
60
80
100
Random Jitter - ps
r
m
s
G004
Modulation Current - mA
0.0
0.1
0.2
0.3
0.4
0.5
5
10
15
20
25
30
Random Jitter - ps
r
m
s
G003
Modulation Current - mA
0
5
10
15
20
25
30
35
5
10
15
20
25
30
t
t
- T
ransition T
ime - ps
G005
Fall Time
Rise Time
Bias Current Register Setting - mA
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
16
Open Loop Bias Current - mA
G006
ONET1191V
SLLS750 AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25
C, I
BIASC
= 6 mA, I
MODC
= 12 mA, MODR = 0 (unless otherwise noted).
RANDOM JITTER
RANDOM JITTER
vs
vs
MODULATION CURRENT
TEMPERATURE
Figure 7.
Figure 8.
RISE TIME AND FALL TIME
BIAS CURRENT IN OPEN-LOOP MODE
vs
vs
MODULATION CURRENT
BIASC REGISTER SETTING
Figure 9.
Figure 10.
13
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Bias Current - mA
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0
2
4
6
8
10
12
14
I
M
O
N
B
- Bias-Monitor Current - mA
G016
Modulation Current Register Setting - mA
0
5
10
15
20
25
30
35
40
45
50
5
10
15
20
25
30
35
40
Modulation Current - mA
G007
G009
150 mV/ Div
14.7 ps / Div
K28.5 Pattern
I
MOD
= 6 mA
MODR = 0
EQENB = 1
T
A
- Free-Air Temperature -
C
50
55
60
65
70
75
80
-40
-20
0
20
40
60
80
100
Supply Current - mA
G008
ONET1191V
SLLS750 AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25
C, I
BIASC
= 6 mA, I
MODC
= 12 mA, MODR = 0 (unless otherwise noted).
BIAS-MONITOR CURRENT I
MONB
MODULATION CURRENT
vs
vs
BIAS CURRENT
MODC REGISTER SETTING MODR=1
Figure 11.
Figure 12.
SUPPLY CURRENT
vs
TEMPERATURE
EYE DIAGRAM AT 11.3 GBPS
Figure 13.
Figure 14.
14
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G010
320 mV/ Div
14.7 ps / Div
K28.5 Pattern
I
MOD
= 10 mA
MODR = 0
EQENB = 1
G011
740 mV/ Div
14.7 ps / Div
K28.5 Pattern
I
MOD
= 15 mA
MODR = 1
EQENB = 1
G012
320 mV/ Div
20 ps / Div
K28.5 Pattern
I
MOD
= 10 mA
MODR = 0
EQENB = 1
G013
320 mV/ Div
14.7 ps / Div
K28.5 Pattern
I
MOD
= 10 mA
MODR = 0
EQENB = 0
ONET1191V
SLLS750 AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25
C, I
BIASC
= 6 mA, I
MODC
= 12 mA, MODR = 0 (unless otherwise noted).
EYE DIAGRAM AT 11.3 GBPS
EYE DIAGRAM AT 11.3 GBPS
Figure 15.
Figure 16.
EYE DIAGRAM AT 11.3 GBPS
EYE DIAGRAM AT 8.5 GBPS
12" OF FR4 AT INPUTS
Figure 17.
Figure 18.
15
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-40
-35
-30
-25
-20
-15
-10
-5
0
SDD1
1 - Differential Input Return Gain - dB
f - Frequency - MHz
G014
10
100k
100
1k
10k
-35
-30
-25
-20
-15
-10
-5
0
SDD22 - Differential Input Return Gain - dB
f - Frequency - MHz
G015
10
100k
100
1k
10k
ONET1191V
SLLS750 AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25
C, I
BIASC
= 6 mA, I
MODC
= 12 mA, MODR = 0 (unless otherwise noted).
DIFFERENTIAL S
11
DIFFERENTIAL S
22
Figure 19.
Figure 20.
16
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APPLICATION INFORMATION
DIN+
DIN
BGV
DIS
MONB
SDA
TS
MONP
S0212-01
FLT
SDK
M
O
N
P
DIN+
DIN
M
O
N
B
MOD+
MOD
BIAS
DIS
T
S
S
C
K
S
D
A
GND
VCC
VCC
FLT
RZ
T
C
P
D
C
O
M
P
GND
B
G
V
VCSEL
VCC
VCC
ONET1191V
20-Pin QFN
C1
0.01
F
m
C7
0.01
F
m
C6
0.1
F
m
C4
0.01
F
m
C3
0.01
F
m
C5
0.01
F
m
R
1.2 k
MONB
W
R
28.7 k
ZTC
W
100
Diff
W
100
Diff
W
R
5 k
MONP
W
C2
0.01
F
m
L5
BLM15HG102SN1
L4
BLM15HG102SN1
L1
BLM15HG102SN1
L3
100 nH
L2
100 nH
Monitor
Photodiode
NdB
Pad
NdB
Pad
ONET1191V
SLLS750 AUGUST 2006
Figure 21
shows a typical application circuit using the ONET1191V with a common-cathode VCSEL, biased to
V
CC
, and driven differentially. The VCSEL driver is controlled via the two-wire interface SDA/SCK by a
microprocessor. In a typical application, the FLT, MONP, MONB, and TS outputs are also connected to the
microcontroller for transceiver management purposes. The monitor photodiode anode is grounded and the
photodiode polarity bit, PDP, must be set to 0.
The component values in
Figure 21
are typical examples and may be varied according to the intended
application. For best performance, it is recommended to use differential drive. Single-ended VCSEL drive can be
implemented by terminating the unused driver output in a resistance that matches the VCSEL series resistance;
however, the available VCSEL modulation current is halved.
Figure 21. Typical Application Circuit With a Common Cathode VCSEL
In the recommended application circuit, the purpose of the attenuator pads is to improve the signal integrity
between the VCSEL driver and the VCSEL. Because the VCSEL impedance is reactive, the pads attenuate
reflections and provide a better matching impedance for the modulation current outputs. The disadvantage of
using the attenuator pads is that the efficiency is reduced. That is, not all of the modulation current at the outputs
of the VCSEL driver is available to drive the VCSEL.
Table 7
lists the available modulation current at the
VCSEL, I
MOD
, depending on the modulation tail current register setting, I
MODC
, the attenuator value, and the
VCSEL series resistance. If care is taken in matching the output impedance of the ONET1191V to the
impedance of the VCSEL, and if controlled-impedance transmission lines are used, attenuator pads may not be
necessary.
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LAYOUT GUIDELINES
ONET1191V
SLLS750 AUGUST 2006
Table 7. I
MOD
vs I
MODC
for a Given Attenuator Pad and VCSEL
I
MODC
(mA):
50-
PAD
VCSEL SERIES
I
MOD
(mA): MODULATION
REGISTER SETTING
ATTENUATION (dB)
RESISTANCE (
)
CURRENT AT THE VCSEL
40
3
100
14.76
40
6
100
10.52
30
3
100
11.07
30
6
100
7.89
20
3
100
7.38
20
6
100
5.26
40
3
60
18.33
40
6
60
13.12
30
3
60
13.75
30
6
60
9.84
20
3
60
9.17
20
6
60
6.56
For optimum performance, use 50-
transmission lines (100-
differential) for connecting the signal source to
the DIN+ and DIN pins and for connecting the modulation current outputs, MOD+ and MOD, to the VCSEL.
The length of the transmission lines should be kept as short as possible to reduce loss and pattern-dependent
jitter.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
ONET1191VRGPR
ACTIVE
QFN
RGP
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ONET1191VRGPRG4
ACTIVE
QFN
RGP
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ONET1191VRGPT
ACTIVE
QFN
RGP
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ONET1191VRGPTG4
ACTIVE
QFN
RGP
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Aug-2006
Addendum-Page 1
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