OPA2683

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SBOS244C MAY 2002 REVISED JUNE 2003

Very Low-Power, Dual, Current-Feedback

Operational Amplifier

FEATURES

REDUCED BANDWIDTH CHANGE VERSUS GAIN

150MHz BANDWIDTH G = +2

> 80MHz BANDWIDTH TO GAIN > +10

LOW DISTORTION: < 65dBc at 5MHz

HIGH OUTPUT CURRENT: 110mA

SINGLE-SUPPLY OPERATION: +5V to +12V

DUAL-SUPPLY OPERATION:

2.5V to

LOW SUPPLY CURRENT: 1.9mA Total

V+

ERR

(S)

ERR

Low-Power

Amplifier

DESCRIPTION

The OPA2683 provides a new level of performance for dual, very
low-power, wideband, current-feedback amplifiers. This CFB

PLUS

amplifier is among the first to use an internally closed-loop input
buffer stage that significantly enhances performance over earlier
low-power, current-feedback (CFB) amplifiers. This new archi-
tecture provides many of the advantages of a more ideal CFB
amplifier while retaining the benefits of very low-power operation.
The closed-loop input stage buffer gives a very low and linearized
impedance path at the inverting input to sense the feedback error
current. This improved inverting input impedance gives excep-
tional bandwidth retention to much higher gains and improved
harmonic distortion over earlier solutions limited by inverting input
linearity. Beyond simple high gain applications, the OPA2683
CFB

PLUS

amplifier can allow the gain setting element to be set with

APPLICATIONS

LOW-POWER BROADCAST VIDEO DRIVER

POWER ACTIVE FILTERS

SHORT-LOOP ADSL CO DRIVER

MULTICHANNEL SUMMING AMPLIFIERS

PROFESSIONAL CAMERAS

DIFFERENTIAL ADC INPUT DRIVER

considerable freedom from amplifier bandwidth interaction. This
flexibility allows frequency response peaking elements to be
added, multiple input inverting summing circuits to have greater
bandwidth, and low-power differential line drivers to meet the
demanding requirements of DSL.

The output capability for the OPA2683 also sets a new mark in
performance for very low-power, current-feedback amplifiers. De-
livering a full

swing on

5V supplies, the OPA2683 also has

the output current to support this swing into a 100

load. This

minimal output headroom requirement is complemented by a
similar 1.2V input stage headroom, giving exceptional capability for
single +5V operation.

The OPA2683's low 1.9mA total supply current is precisely trimmed
at +25

C. This trim, along with low shift over temperature and supply

voltage, gives a very robust design over a wide range of operating
conditions.

OPA2

683

Patent Pending

Frequency (Hz)

200

100

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (dB)

G = 100

G = 50

G = 10

G = 1

G = 2

= 953

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

All trademarks are the property of their respective owners.

OPA2683

SBOS244C

www.ti.com

ABSOLUTE MAXIMUM RATINGS

(1)

Power Supply ...............................................................................

6.5V

Internal Power Dissipation ................................. See Thermal Information
Differential Input Voltage ..................................................................

1.2V

Input Voltage Range ............................................................................

Storage Temperature Range: ID, IDCN ......................... 40

C to +125

Lead Temperature (soldering, 10s) .............................................. +300

Junction Temperature (T

) ........................................................... +150

ESD Rating: Human Body Model (HBM) ........................................ 2000V

Charged Device Model (CDM) .................................. 1000V

NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

SPECIFIED

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE-LEAD

DESIGNATOR

(1)

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

OPA2683

SO-8

C to +85

OPA2683D

OPA2683ID

Rails,100

OPA2683IDR

Tape and Reel, 2500

OPA2683

SOT23-8

DCN

C to +85

B83

OPA2683IDCNT

Tape and Reel, 250

OPA2683IDCNR

Tape and Reel, 3000

PACKAGE/ORDERING INFORMATION

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.

PIN CONFIGURATION

OPA2683 RELATED PRODUCTS

SINGLES

DUALS

TRIPLES

QUADS

FEATURES

OPA683

OPA2684

OPA3684

OPA4684

Low-Power CFB

PLUS

OPA691

OPA2691

OPA3691

High Slew Rate CFB

OPA685

> 500MHz CFB

Top View

SOT23

NOTE: (1) For the most current specifications, and package information, refer to our web site at www.ti.com.

Out B

In B

+In B

Out A

In A

+In A

B83

Pin 1

Out B

In B

+In B

Out A

In A

+In A

OPA2683

SBOS244C

www.ti.com

OPA2683ID, IDCN

TYP

MIN/MAX OVER TEMPERATURE

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (V

= 0.5V

)

G = +1, R

= 953k

200

MHz

typ

G = +2, R

= 953

150

124

121

117

MHz

min

G = +5, R

= 953

121

MHz

typ

G = +10, R

= 953

MHz

typ

G = +20, R

= 953

MHz

typ

Bandwidth for 0.1dB Gain Flatness

G = +2, V

= 0.5V

, R

= 953

MHz

min

Peaking at a Gain of +1

= 953

, V

= 0.5V

1.8

6.5

7.7

8.0

max

Large-Signal Bandwidth

G = +2, V

= 4V

MHz

typ

Slew Rate

G = 1, V

= 4V Step (see Figure 2)

540

450

430

min

G = +2, V

= 4V Step

400

345

338

336

min

Rise-and-Fall Time

G = +2, V

= 0.5V Step

4.6

typ

G = +2, V

= 4V Step

7.8

typ

Harmonic Distortion

G = +2, f = 5MHz, V

= 2V

2nd-Harmonic

= 100

dBc

max

dBc

max

3rd-Harmonic

= 100

dBc

max

dBc

max

Input Voltage Noise

f > 1MHz

4.4

5.0

5.5

5.8

nV/

max

Noninverting Input Current Noise

f > 1MHz

5.1

5.8

6.4

6.7

pA/

max

Inverting Input Current Noise

f > 1MHz

11.6

11.9

12.3

12.4

pA/

max

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.13

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.06

deg

typ

Channel-to-Channel Isolation

f = 5MHz

typ

DC PERFORMANCE

(4)

Open-Loop Transimpedance Gain (Z

)

= 0V, R

= 1k

700

360

270

250

min

Input Offset Voltage

= 0V

1.5

3.5

4.1

4.3

max

Average Offset Voltage Drift

= 0V

max

Noninverting Input Bias Current

= 0V

2.0

4.5

5.1

5.3

max

Average Noninverting Input Bias Current Drift

= 0V

nA/

max

Inverting Input Bias Current

= 0V

3.0

11.5

max

Average Inverting Input Bias Current Drift

= 0V

max

INPUT
Common-Mode Input Range

(5)

(CMIR)

3.75

3.65

3.65

3.60

min

Common-Mode Rejection Ratio (CMRR)

= 0V

min

Noninverting Input Impedance

|| pF

typ

Inverting Input Resistance (R

)

Open-Loop, DC

5.0

typ

OUTPUT
Voltage Output Swing

Load

4.1

4.0

4.0

3.9

min

Current Output, Sourcing

= 0

150

120

115

110

min

Current Output, Sinking

= 0

110

100

min

Closed-Loop Output Impedance

G = +2, f = 100kHz

0.007

typ

POWER SUPPLY
Specified Operating Voltage

typ

Maximum Operating Voltage Range

max

Max Quiescent Current

5V, Both Channels

1.88

2.06

2.08

2.10

max

Min Quiescent Current

5V, Both Channels

1.88

1.70

1.6

1.54

min

Power-Supply Rejection Ratio (PSRR)

Input Referred

typ

TEMPERATURE RANGE
Specification: D, DCN

40 to +85

typ

Thermal Resistance,

Junction-to-Ambient

SO-8

125

C/W

typ

DCN

SOT23-8

150

C/W

typ

NOTES: (1) Junction temperature = ambient for +25

C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient

C at high temperature limit for over-temperature tested specifications. (3) Test levels: (A) 100% tested at +25

C. Over-temperature limits by characterization and

simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V

is the input

common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at

CMIR limits.

ELECTRICAL CHARACTERISTICS: V

Boldface limits are tested at +25

= 953

, R

= 1k

, and G = +2

(see Figure 1 for AC performance only), unless otherwise noted.

OPA2683

SBOS244C

www.ti.com

ELECTRICAL CHARACTERISTICS: V

= +5V

Boldface limits are tested at +25

= 1.2k

, R

= 1k

, and G = +2

(see Figure 3 for AC performance only), unless otherwise noted.

OPA2683ID, IDCN

TYP

MIN/MAX OVER TEMPERATURE

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

AC PERFORMANCE (see Figure 3)
Small-Signal Bandwidth (V

= 0.2V

)

G = +1, R

= 1.2k

145

MHz

typ

G = +2, R

= 1.2k

119

MHz

min

G = +5, R

= 1.2k

MHz

typ

G = +10, R

= 1.2k

MHz

typ

G = +20, R

= 1.2k

MHz

typ

Bandwidth for 0.1dB Gain Flatness

G = +2, V

< 0.5V

, R

= 1.2k

MHz

min

Peaking at a Gain of +1

= 1.2k

, V

< 0.5V

max

Large-Signal Bandwidth

G = +2, V

= 2V

MHz

typ

Slew Rate

G = +2, V

= 2V Step

210

180

175

170

min

Rise-and-Fall Time

G = +2, V

= 0.5V Step

5.9

typ

G = +2, V

= 2V Step

7.8

typ

Harmonic Distortion

G = 2, f = 5MHz, V

= 2V

2nd-Harmonic

= 100

to V

dBc

max

to V

dBc

max

3rd-Harmonic

= 100

to V

dBc

max

to V

dBc

max

Input Voltage Noise

f > 1MHz

4.4

5.0

5.5

5.8

nV/

max

Noninverting Input Current Noise

f > 1MHz

5.1

5.8

6.4

6.7

pA/

max

Inverting Input Current Noise

f > 1MHz

11.6

11.9

12.3

12.4

pA/

max

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.24

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.19

deg

typ

Channel-to-Channel Crosstalk

f = 5MHz

type

DC PERFORMANCE

(4)

Open-Loop Transimpedance Gain (Z

)

= V

/2, R

= 1k

to V

700

300

270

250

min

Input Offset Voltage

= V

1.0

3.0

3.6

3.8

max

Average Offset Voltage Drift

= V

max

Noninverting Input Bias Current

= V

4.5

5.1

5.3

max

Average Noninverting Input Bias Current Drift

= V

nA/

max

Inverting Input Bias Current

= V

8.7

8.9

max

Average Inverting Input Bias Current Drift

= V

max

INPUT
Least Positive Input Voltage

(5)

1.1

1.25

1.29

1.34

max

Most Positive Input Voltage

(5)

3.9

3.75

3.73

3.67

min

Common-Mode Refection Ratio (CMRR)

= V

min

Noninverting Input Impedance

|| pF

typ

Inverting Input Resistance (R

)

Open-Loop, DC

5.6

typ

OUTPUT
Most Positive Output Voltage

= 1k

to V

4.2

4.1

4.1

4.0

min

Least Positive Output Voltage

= 1k

to V

0.8

0.9

0.9

1.00

min

Current Output, Sourcing

= V

min

Current Output, Sinking

= V

min

Closed-Loop Output Impedance

G = +2, f = 100kHz

0.009

typ

POWER SUPPLY
Specified Single-Supply Operating Voltage

typ

Max Single-Supply Operating Voltage

max

Max Quiescent Current

= +5V, Both Channels

1.58

1.76

1.76

max

Min Quiescent Current

= +5V, Both Channels

1.58

1.36

1.32

1.28

min

Power-Supply Rejection Ratio (+PSRR)

Input Referred

typ

TEMPERATURE RANGE
Specification: D, DCN

40 to +85

typ

Thermal Resistance,

Junction-to-Ambient

SO-8

125

C/W

typ

DCN

SOT23-8

150

C/W

typ

NOTES: (1) Junction temperature = ambient for +25

C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient

C at high temperature limit for over-temperature tested specifications. (3) Test levels: (A) 100% tested at +25

C. Over-temperature limits by characterization and

simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V

is the input

common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at

CMIR limits.

OPA2683

SBOS244C

www.ti.com

TYPICAL CHARACTERISTICS: V

= +25

C, G = +2, R

= 953

, and R

= 1k

, unless otherwise noted.

NONINVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (200mV/div)

Output V

oltage (800mV/div)

0.8

0.6

0.4

0.2

0.4

0.6

0.8

3.2

2.4

1.6

0.8

1.6

2.4

3.2

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 1

G = +2

INVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (200mV/div)

Output V

oltage (800mV/div)

0.8

0.6

0.4

0.2

0.4

0.6

0.8

3.2

2.4

1.6

0.8

1.6

2.4

3.2

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 2

G = 1

Frequency (MHz)

200

100

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (dB)

G = 100

G = 50

G = 10

G = 1

G = 2

See Figure 1

Frequency (MHz)

200

100

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (dB)

= 0.5V

= 953

See Figure 2

G = 20

G = 10

G = 1

G = 2

G = 5

Frequency (MHz)

200

100

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (dB)

= 953

G = +2

0.5V

See Figure 1

Frequency (MHz)

200

100

INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (dB)

0.5V

= 953

G = 2

See Figure 2

OPA2683

SBOS244C

www.ti.com

TYPICAL CHARACTERISTICS: V

(Cont.)

= +25

C, G = +2, R

= 953

, and R

= 1k

, unless otherwise noted.

Gain (V/V)

HARMONIC DISTORTION vs NONINVERTING GAIN

Harmonic Distortion (dBc)

2nd-Harmonic

3rd-Harmonic

See Figure 1

= 2V

= 1k

Gain |(V/V)|

HARMONIC DISTORTION vs INVERTING GAIN

Harmonic Distortion (dBc)

2nd-Harmonic

3rd-Harmonic

See Figure 2

= 2V

= 1k

Load Resistance (

)

100

HARMONIC DISTORTION vs LOAD RESISTANCE

Harmonic Distortion (dBc)

= 2V

f = 5MHz

G = +2

2nd-Harmonic

3rd-Harmonic

See Figure 1

Frequency (MHz)

0.1

HARMONIC DISTORTION vs FREQUENCY

Normalized Distortion (dB)

2nd-Harmonic

= 2V

= 1k

3rd-Harmonic

See Figure 1

Output Voltage (V

)

0.1

HARMONIC DISTORTION vs OUTPUT VOLTAGE

Harmonic Distortion (dBc)

= 5MHz

= 1k

3rd-Harmonic

See Figure 1

2nd-Harmonic

Supply Voltage (

2.5

3.0

3.5

4.0

4.5

6.0

5.0

5.5

5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE

Harmonic Distortion (dBc)

= 2V

= 1k

2nd-Harmonic

See Figure 1

3rd-Harmonic

OPA2683

SBOS244C

www.ti.com

TYPICAL CHARACTERISTICS: V

(Cont.)

= +25

C, G = +2, R

= 953

, and R

= 1k

, unless otherwise noted.

100

Frequency (Hz)

100

10M

10k

100k

INPUT VOLTAGE AND CURRENT NOISE DENSITY

Voltage Noise (nV/

Hz)

Current Noise (pA/

Hz)

Noninverting Current Noise

5.2pA/

Voltage Noise

4.4nV/

Inverting Current Noise

11.6pA/

OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE

10k

100k

10M

100M

Frequency (Hz)

Open-Loop

ransimpedance Gain (dB

) 120

100

Open-Loop Phase (

)

120

150

180

20log (Z

)

Vp-p at 1k

Load (Each tone)

0.1

= 20MHz

= 10MHz

= 5MHz

= 1MHz

2-TONE, 3RD-ORDER

INTERMODULATION DISTORTION

3rd-Order Spurious Level (dBc)

+5V

953

OPA2683

LOAD

(pF)

100

vs C

LOAD

(

)

0.5dB Peaking

CMRR AND PSRR vs FREQUENCY

100

10k

100k

10M

100M

Frequency (Hz)

Common-Mode Rejection Ratio (dB)

Power-Supply Rejection Ratio (dB)

CMRR

+PSRR

PSRR

Frequency (Hz)

100k

10M

100M

SMALL-SIGNAL BANDWIDTH vs C

LOAD

Normalized Gain (dBc)

10pF

953

OPA2683

+5V

953

22pF

100pF

47pF

Adjusted to C

LOAD

OPA2683

SBOS244C

www.ti.com

TYPICAL CHARACTERISTICS: V

(Cont.)

= +25

C, G = +2, R

= 953

, and R

= 1k

, unless otherwise noted.

TYPICAL DC DRIFT OVER TEMPERATURE

100

125

Ambient Temperature (

Input Bias Currents (

and Of

fset V

oltage (mV)

Input Offset Voltage

Noninverting Input Bias Current

Inverting Input Bias Current

CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY

Frequency (Hz)

100k

10k

100

10M

100M

Output Impedance (

)

100

0.01

0.001

953

1/2

OPA2683

0.20

0.15

0.10

0.05

Number of 150

Video Loads

COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE

Differential Gain (%)

Differential Phase (

)

Gain = +2
NTSC, Positive Video

SETTLING TIME

Time (ns)

% Error to Final V

alue

0.05

0.04

0.03

0.02

0.01

0.02

0.03

0.04

0.05

2V Step
See Figure 1

SUPPLY AND OUTPUT CURRENT

vs TEMPERATURE

100

125

Ambient Temperature (

Output Current (mA)

200

175

150

125

100

2.0

1.9

1.8

1.7

1.6

Supply Current (mA)

Sourcing Output Current

Sinking Output Current

Supply Current

Right Scale

OUTPUT CURRENT AND VOLTAGE LIMITATIONS

150

100

150

(mA)

(V)

1W Power

Limit

= 100

= 500

1W Power

Limit

Each Channel

OPA2683

SBOS244C

www.ti.com

TYPICAL CHARACTERISTICS: V

= +5V

= +25

C, V

= 5V, G = +2, R

= 1.2k

, and R

= 1k

, unless otherwise noted.

Frequency (MHz)

100

200

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (dB)

G = 100

G = 50

G = 5

G = 10

G = 20

G = 2

G = 1

See Figure 3

Frequency (MHz)

100

200

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (dB)

G = 10

G = 20

G = 2

G = 5

G = 1

See Figure 4

Frequency (MHz)

100

200

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Gain (dB)

0.2V

0.5V

See Figure 3

Frequency (MHz)

200

100

INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Gain (dB)

0.5V

0.2V

See Figure 4

NONINVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (100mV/div)

Output V

oltage (400mV/div)

0.4

0.3

0.2

0.1

0.2

0.3

0.4

1.6

1.2

0.8

0.4

0.8

1.2

1.6

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 3

INVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (100mV/div)

Output V

oltage (400mV/div)

0.4

0.3

0.2

0.1

0.2

0.3

0.4

1.6

1.2

0.8

0.4

0.8

1.2

1.6

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 4

OPA2683

SBOS244C

www.ti.com

TYPICAL CHARACTERISTICS: V

= +5V

(Cont.)

= +25

C, V

= 5V, G = +2, R

= 1.2k

, and R

= 1k

, unless otherwise noted.

Load Resistance (

)

100

HARMONIC DISTORTION vs LOAD RESISTANCE

Harmonic Distortion (dBc)

2nd-Harmonic

3rd-Harmonic

See Figure 3

f = 5MHz

= 2V

Frequency (MHz)

0.1

HARMONIC DISTORTION vs FREQUENCY

Harmonic Distortion (dBc)

2nd-Harmonic

3rd-Harmonic

= 2V

= 1k

See Figure 3

Output Voltage (V

)

0.1

HARMONIC DISTORTION vs OUTPUT VOLTAGE

Harmonic Distortion (dBc)

3rd-Harmonic

2nd-Harmonic

See Figure 3

at 1k

Load (each tone)

0.1

5MHz

See Figure 3

10MHz

20MHz

2-TONE, 3RD-ORDER

INTERMODULATION DISTORTION

Harmonic Distortion (dBc)

SUPPLY AND OUTPUT CURRENT

vs TEMPERATURE

100

125

Ambient Temperature (

Output Current (mA)

100

1.9

1.8

1.7

1.6

1.5

1.4

Supply Current (mA)

Left Scale

Sinking Output Current

Right Scale

Supply Current

Sourcing Output Current

Left Scale

0.30

0.25

0.20

0.15

0.10

0.05

Number of 150

Video Loads

COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE

Differential Gain (%)

Differential Phase (

)

G = +2
NTSC, Positive Video

OPA2683

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FIGURE 1. DC-Coupled, G = +2V/V, Bipolar Supply Speci-

fications and Test Circuit.

FIGURE 2. DC-Coupled, G = 1V/V, Bipolar Supply Specifi-

cations and Test Circuit.

APPLICATIONS INFORMATION

LOW-POWER, CURRENT-FEEDBACK OPERATION

The dual channel OPA2683 gives a new level of perfor-
mance in low-power, current-feedback op amps. Using a
new input stage buffer architecture, the OPA2683 CFB

PLUS

amplifier holds nearly constant AC performance over a wide
gain range. This closed-loop internal buffer gives a very low
and linearized impedance at the inverting node, isolating the
amplifier's AC performance from gain element variations.
This low impedance allows both the bandwidth and distortion
to remain nearly constant over gain, moving closer to the
ideal current- feedback performance of gain bandwidth inde-
pendence. This low-power amplifier also delivers exceptional
output power--its

4V swing on

5V supplies with > 100mA

output drive gives excellent performance into standard video
loads or doubly-terminated 50

cables. This dual-channel

device can provide adequate drive for several emerging
differential driver applications with exceptional power effi-
ciency. Single +5V supply operation is also supported with
similar bandwidths but reduced output power capability. For
higher output power in a dual current-feedback op amp,
consider the OPA2684, OPA2691, or OPA2677.

Figure 1 shows the DC-coupled, gain of +2, dual power-
supply circuit used as the basis of the

5V Electrical and

Typical Characteristics for each channel. For test purposes,
the input impedance is set to 50

with a resistor to ground,

and the output impedance is set to a 1k

load. Voltage

swings reported in the characteristics are taken directly at the
input and output pins. For the circuit of Figure 1, the total
effective load will be 1k

|| 1.9k

= 656

. Gain changes are

most easily accomplished by simply resetting the R

value,

holding R

constant at its recommended value of 953

Figure 2 shows the DC-coupled, gain of 1V/V, dual power-
supply circuit used as the basis of the inverting Typical
Characteristics for each channel. Inverting operation offers
several performance benefits. Since there is no common-
mode signal across the input stage, the slew rate for inverting
operation is typically higher and the distortion performance is
slightly improved. An additional input resistor, R

, is included

in Figure 2 to set the input impedance equal to 50

. The

parallel combination of R

and R

set the input impedance.

As the desired gain increases for the inverting configuration,
R

is adjusted to achieve the desired gain, while R

is also

adjusted to hold a 50

input match. A point will be reached

where R

will equal 50

, R

is removed, and the input match

is set by R

only. With R

fixed to achieve an input match to

, increasing R

will increase the gain. However, this will

reduce the achievable bandwidth as the feedback resistor
increases from its recommended value of 953

. If the source

does not require an input match to 50

, either adjust R

get the desired load, or remove it and let the R

resistor

alone provide the input load.

These circuits show

5V operation. The same circuit can be

applied with bipolar supplies from

2.5V to

6V. Internal

supply independent biasing gives nearly the same perfor-
mance for the OPA2683 over this wide range of supplies.
Generally, the optimum feedback resistor value (for nomi-
nally flat frequency response at G = +2) will increase in value
as the total supply voltage across the OPA2683 is reduced
from

5V.

See Figure 3 for the AC-coupled, single +5V supply, gain of
+2V/V circuit configuration used as a basis only for the +5V
Electrical and Typical Characteristics for each channel. The
key requirement of broadband single-supply operation is to
maintain input and output signal swings within the usable
voltage ranges at both the input and the output. The circuit
of Figure 3 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 10k

resistors) to

the noninverting input. The input signal is then AC-coupled

953

1/2

OPA2683

+5V

953

Source

0.1

6.8

0.1

6.8

953

1/2

OPA2683

+5V

52.3

953

Source

0.1

6.8

0.1

6.8

OPA2683

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FIGURE 3. AC-Coupled, G = +2V/V, Single-Supply Specifi-

cations and Test Circuit.

FIGURE 4. AC-Coupled, G = 1V/V, Single-Supply Specifi-

cations and Test Circuit.

FIGURE 5. Noninverting Differential I/O Amplifier.

into this midpoint voltage bias. The input voltage can swing
to within 1.25V of either supply pin, giving a 2.5V

input

signal range centered between the supply pins. The input
impedance of Figure 3 is set to give a 50

input match. If the

source does not require a 50

match, remove this and drive

directly into the blocking capacitor. The source will then see
the 5k

load of the biasing network. The gain resistor (R

)

is AC-coupled, giving the circuit a DC gain of +1, which puts
the noninverting input DC bias voltage (2.5V) on the output
as well. The feedback resistor value has been adjusted from
the bipolar

5V supply condition to re-optimize for a flat

frequency response in +5V only, gain of +2, operation. On a
single +5V supply, the output voltage can swing to within
0.9V of either supply pin while delivering more than 70mA
output current, giving 3.2V output swing into 100

(8dBm

maximum at a matched 50

load). The circuit of Figure 3

shows a blocking capacitor driving into a 1k

load. Alterna-

tively, the blocking capacitor could be removed if the load is
tied to a supply midpoint or to ground if the DC current
required by the load is acceptable.

Figure 4 shows the AC-coupled, single +5V supply, gain of
1V/V circuit configuration used as a basis for the +5V
Typical Characteristics for each channel. In this case, the
midpoint DC bias on the noninverting input is also decoupled
with an additional 0.1

F decoupling capacitor. This reduces

the source impedance at higher frequencies for the
noninverting input bias current noise. This 2.5V bias on the
noninverting input pin appears on the inverting input pin and,
since R

is DC blocked by the input capacitor, will also

appear at the output pin. One advantage to inverting opera-
tion is that since there is no signal swing across the input
stage, higher slew rates and operation to even lower supply
voltages is possible. To retain a 1V

output capability,

operation down to 3V supply is allowed. At +3V supply, the
input stage is saturated, but for the inverting configuration of

a current-feedback amplifier, wideband operation is retained
even under this condition.

The circuits of Figure 3 and 4 show single-supply operation
at +5V. These same circuits may be used up to single
supplies of +12V with minimal change in the performance of
the OPA2683.

DIFFERENTIAL INTERFACE APPLICATIONS

Dual op amps are particularly suitable to differential input to
differential output applications. Typically, these fall into either
Analog-to-Digital Converter (ADC) input interfaces or line
driver applications. Two basic approaches to differential I/O
are noninverting or inverting configurations. Since the output
is differential, the signal polarity is somewhat meaningless--
the noninverting and inverting terminology applies here to
where the input is brought into the OPA2683. Each has its
advantages and disadvantages. Figure 5 shows a basic
starting point for noninverting differential I/O applications.

1.2k

1/2

OPA2683

+5V

Source

0.1

6.8

10k

1.2k

0.1

1.2k

1/2

OPA2683

+5V

Source

0.1

6.8

1.2k

10k

0.1

52.3

953

1/2

OPA2683

1/2

OPA2683

OPA2683

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FIGURE 6. Inverting Differential I/O Amplifier.

FIGURE 7. Single to Differential Conversion.

This approach provides for a source termination impedance
that is independent of the signal gain. For instance, simple
differential filters may be included in the signal path right up
to the noninverting inputs without interacting with the gain
setting. The differential signal gain for the circuit of Figure 5 is:

= 1 + 2 · R

Since the OPA2683 is a CFB

PLUS

amplifier, its bandwidth is

principally controlled with the feedback resistor value; see
Figure 5 for the recommended value of 953

. The differential

gain, however, may be adjusted with considerable freedom
using just the R

resistor. In fact, R

may be a reactive

network providing a very isolated shaping to the differential
frequency response. Since the inverting inputs of the OPA2683
are very low impedance closed-loop buffer outputs, the R

element does not interact with the amplifier's bandwidth;
wide ranges of resistor values and/or filter elements may be
inserted here with minimal amplifier bandwidth interaction.

Various combinations of single-supply or AC-coupled gain
can also be delivered using the basic circuit of Figure 5.
Common-mode bias voltages on the two noninverting inputs
pass on to the output with a gain of 1 since an equal DC
voltage at each inverting node creates no current through
R

. This circuit does show a common-mode gain of 1 from

input to output. The source connection should either remove
this common-mode signal if undesired (using an input trans-
former can provide this function), or the common-mode
voltage at the inputs can be used to set the output common-
mode bias. If the low common-mode rejection of this circuit
is a concern, the output interface may also be used to reject
that common-mode. For instance, most modern differential
input ADCs reject common-mode signals very well, while a
line driver application through a transformer will also attenu-
ate the common-mode signal through to the line.

Figure 6 shows a differential I/O stage configured as an
inverting amplifier. In this case, the gain resistors (R

)

become part of the input resistance for the source. This
provides a better noise performance than the noninverting
configuration but does limit the flexibility in setting the input
impedance separately from the gain.

The two noninverting inputs provide an easy common-mode
control input. This is particularly simple if the source is
AC-coupled through either blocking caps or a transformer.
In either case, the common-mode input voltages on the two
noninverting inputs again have a gain of 1 to the output pins,
giving particularly easy common-mode control for single-
supply operation. The OPA2683 used in this configuration
does constrain the feedback to the 953

region for best

frequency response. With R

fixed, the input resistors may be

adjusted to the desired gain but will also be changing the
input impedance as well. The high-frequency common-mode
gain for this circuit from input to output will be the same as
for the signal gain. Again, if the source might include an
undesired common-mode signal, that signal could be re-
jected at the input using blocking caps (for low frequency and
DC common-mode) or a transformer coupling.

DC-COUPLED SINGLE TO DIFFERENTIAL CONVERSION

The previous differential output circuits were also set up to
receive a differential input. A simple way to provide a DC-
coupled single to differential conversion using a dual op amp
is shown in Figure 7. Here, the output of the first stage is
simply inverted by the second to provide an inverting version
of a single amplifier design. This approach works well for
lower frequencies but will start to depart from ideal differential
outputs as the propagation delay and distortion of the invert-
ing stage adds significantly to that present at the noninverting
output pin.

953

1/2

OPA2683

1/2

OPA2683

The circuit of Figure 7 is set up for a single-ended gain of 6
to the output of the first amplifier, then an inverting gain of
1 through the second stage to provide a total differential
gain of 12. See Figure 8 for the 75MHz small-signal band-
width delivered by the circuit of Figure 7. Large-signal distor-
tion at 12V

output at 1MHz into the 1k

differential load is

76dBc.

953

12V

Differential

953

1/2

OPA2683

+5V

953

191

1/2

OPA2683

(1)

OPA2683

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FIGURE 8. Small-Signal Bandwidth for Figure 7.

FIGURE 9. Low-Power, Differential I/O, 4th-Order Butterworth Active Filter.

DIFFERENTIAL ACTIVE FILTER

The OPA2683 can provide a very capable gain block for low-
power active filters. The dual design lends itself very well to
differential active filters. Where the filter topology is looking
for a simple gain function to implement the filter, the
noninverting configuration is preferred to isolate the filter
elements from the gain elements in the design. Figure 9
shows an example of a very low-power, 10MHz, 3rd-order
Butterworth low-pass Sallen-Key filter. Often, these filters are
designed at an amplifier gain of 1 to minimize amplifier
bandwidth interaction with the desired filter shape. Since the
OPA2683 shows minimal bandwidth change with gain, this
feature would not be a constraint in this design. The example

of Figure 9 designs the filter for a differential gain of 5 using
the OPA2683. The resistor values have been adjusted slightly
to account for the amplifier bandwidth effects.

While this circuit is bipolar, using

5V supplies, it can easily

be adapted to single-supply operation. This is typically done
by providing a supply midpoint reference at the noninverting
inputs, then adding DC blocking caps at each input and in
series with the amplifier gain resistor, R

. This will add two

real zeroes in the response, transforming the circuit into a
bandpass. Figure 10 shows the frequency response for the
filter of Figure 9.

FIGURE 10. Frequency Response for 10MHz, 3rd-Order

Butterworth Low-Pass Filter.

Frequency (MHz)

200

100

SINGLE TO DIFFERENTIAL CONVERSION

Gain (dB)

1/2

OPA2683

1/2

OPA2683

183

75pF

22pF

100pF

183

100pF

953

+5V

357

475

Frequency (MHz)

10MHz, 3RD-ORDER BUTTERWORTH LOW PASS

FREQUENCY RESPONSE

Differential Gain (dB)

OPA2683

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BOARD

LITERATURE

PART

REQUEST

PRODUCT

PACKAGE

NUMBER

OPA2683ID

SO-8

DEM-OPA26xU

SBOU003

OPA2683IDCN

SOT23-8

DEM-OPA2652E

SBOU001

TABLE I. Evaluation Module Ordering Information.

FIGURE 11. Single-Supply Differential ADC Driver.

SINGLE-SUPPLY, HIGH GAIN DIFFERENTIAL
ADC DRIVER

Where a very low-power differential I/O interface to a moder-
ate performance ADC is required, the circuit of Figure 11 may
be considered. The circuit builds on the inverting differential
I/O configuration of Figure 6 by adding the input transformer
and the output low-pass filter. The input transformer provides
a single-to-differential conversion where the input signal is
still very low power--it also provides a gain of 2 and removes
any common-mode signal from the inputs. This single +5V
design sets a midpoint bias from the supply at each of the
noninverting inputs.

This circuit also includes optional 500

pull-down resistors at

the output. With a 2.5V DC common-mode operating point
(set by V

), this will add 5mA to ground in the output stage.

This essentially powers up the NPN side of the output stage
significantly reducing distortion. It is important for good 2nd-
order distortion to connect the grounds of these two resistors
at the same point to minimize ground plane current for the
differential output signal.

1/2

OPA2683

1/2

OPA2683

0.1

800

+5V

200

500

(Optional)

ADC

10k

Source

15.3dB

Noise Figure

Gain = 8V/V

18.1dB

1:2

500

(Optional)

MACROMODELS

Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for higher speed
designs where parasitic capacitance and inductance can
have a major effect on circuit performance. A SPICE model
for the OPA683 is available in the product folder on the TI
web site (www.ti.com). This is the single channel model for

DESIGN-IN TOOLS

DEMONSTRATION BOARDS

Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA2683 in its two package
styles. Both of these are available, free, as an unpopulated
PC board delivered with descriptive documentation. The
summary information for these boards is shown in Table I.

OPA2683

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the OPA2683--simply use two of these to implement an
OPA2683 simulation. These models do a good job of predict-
ing small-signal AC and transient performance under a wide
variety of operating conditions. However, they are less accu-
rate in predicting the harmonic distortion or dG/dP character-
istics. These models do not attempt to distinguish between
the package types in their small-signal AC performance.

OPERATING SUGGESTIONS

SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH

Any current-feedback op amp like the OPA2683 can hold
high bandwidth over signal-gain settings with the proper
adjustment of the external resistor values. A low-power part
like the OPA2683 typically shows a larger change in band-
width due to the significant contribution of the inverting input
impedance to loop-gain changes as the signal gain is changed.
Figure 12 shows a simplified analysis circuit for any current-
feedback amplifier.

The key elements of this current-feedback op amp model are:

Buffer gain from the noninverting input to the inverting input

Buffer output impedance

ERR

Feedback error current signal

Z(s)

Frequency dependent open-loop transimpedance

gain from i

ERR

to V

The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however, set
the CMRR for a single op amp differential amplifier configura-
tion. For the buffer gain

< 1.0, the CMRR = 20 · log(1

The closed-loop input stage buffer used in the OPA2683 gives
a buffer gain more closely approaching 1.00 and this shows up
in a slightly higher CMRR than previous current-feedback op
amps.

FIGURE 12. Current-Feedback Transfer Function Analysis

Circuit.

(S)

ERR

, the buffer output impedance, is a critical portion of the

bandwidth control equation. The OPA2683 reduces this
element to approximately 5.0

using the loop gain of the

closed-loop input buffer stage. This significant reduction in
output impedance, on very low power, contributes signifi-
cantly to extending the bandwidth at higher gains.

A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error volt-
age for a voltage-feedback op amp) and passes this on to
the output through an internal frequency dependent
transimpedance gain. The Typical Characteristics show this
open-loop transimpedance response. This is analogous to
the open-loop voltage gain curve for a voltage-feedback op
amp. Developing the transfer function for the circuit of Figure
12 gives Equation 2:

R NG

( )

This is written in a loop-gain analysis format where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z

(S)

were infinite over all frequencies, the

denominator of Equation 2 would reduce to 1 and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 2 determines the
frequency response. Equation 3 shows this as the loop-gain
equation.

R NG

Loop Gain

( )

If 20 · log(R

+ NG · R

) were drawn on top of the open-loop

transimpedance plot, the difference between the two would
be the loop gain at a given frequency. Eventually, Z

(S)

rolls off

to equal the denominator of Equation 3, at which point the
loop gain has reduced to 1 (and the curves have intersected).
This point of equality is where the amplifier's closed-loop
frequency response given by Equation 2 will start to roll off,
and is exactly analogous to the frequency at which the noise
gain equals the open-loop voltage gain for a voltage-feed-
back op amp. The difference here is that the total impedance
in the denominator of Equation 3 may be controlled some-
what separately from the desired signal gain (or NG).

The OPA2683 is internally compensated to give a maximally
flat frequency response for R

= 953

at NG = 2 on

supplies. That optimum value goes to 1.2k

on a single +5V

supply. Normally, with a current-feedback amplifier, it is
possible to adjust the feedback resistor to hold this band-
width up as the gain is increased. The CFB

PLUS

architecture

has reduced the contribution of the inverting input impedance
to provide exceptional bandwidth to higher gains without

(2)

(3)

OPA2683

SBOS244C

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adjusting the feedback resistor value. The Typical Character-
istics show the small-signal bandwidth over gain with a fixed
feedback resistor.

Putting a closed-loop buffer between the noninverting and
inverting inputs does bring some added considerations. Since
the voltage at the inverting output node is now the output of
a locally closed-loop buffer, parasitic external capacitance on
this node can cause frequency response peaking for the
transfer function from the noninverting input voltage to the
inverting node voltage. While it is always important to keep
the inverting node capacitance low for any current-feedback
op amp, it is critically important for the OPA2683. External
layout capacitance in excess of 2pF will start to peak the
frequency response. This peaking can be easily reduced by
then increasing the feedback resistor value--but it is prefer-
able, from a noise and dynamic range standpoint, to keep
that capacitance low, allowing a close to nominal 953

feedback resistor for flat frequency response. Very high
parasitic capacitance values on the inverting node (> 5pF)
can possibly cause input stage oscillation that cannot be
filtered by a feedback element adjustment.

An added consideration is that at very high gains, 2nd-order
effects in the inverting output impedance cause the overall
response to peak up. If desired, it is possible to retain a flat
frequency response at higher gains by adjusting the feed-
back resistor to higher values as the gain is increased. Since
the exact value of feedback that will give a flat frequency
response at high gains depends strongly in inverting and
output node parasitic capacitance values, it is best to experi-
ment in the specific board with increasing values until the
desired flatness (or pulse response shape) is obtained. In
general, increasing R

(and then adjusting R

to the desired

gain) will move towards flattening the response, while de-
creasing it will extend the bandwidth at the cost of some
peaking. The OPA683 data sheet gives an example of this
optimization of R

versus gain.

OUTPUT CURRENT AND VOLTAGE

The OPA2683 provides output voltage and current capabili-
ties that can support the needs of driving doubly-terminated
50

lines. If the 1k

load of Figure 1 is changed to a 100

load, the total load is the parallel combination of the 100

load, and the 1.9k

total feedback network impedance. This

load will require no more than 42mA output current to

support the

4.0V minimum output voltage swing specified

for 1k

loads. This is well below the specified minimum

+120/90mA specifications over the full temperature range.

The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage · current, or V-I product,
which is more relevant to circuit operation. Refer to the
"Output Voltage and Current Limitations" plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA2683's output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.

The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
electrical characteristic tables. As the output transistors de-
liver power, their junction temperatures will increase, de-
creasing their V

s (increasing the available output voltage

swing) and increasing their current gains (increasing the
available output current). In steady-state operation, the avail-
able output voltage and current will always be greater than
that shown in the over-temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.

To maintain maximum output stage linearity, no output short-
circuit protection is provided. This will not normally be a
problem, since most applications include a series matching
resistor at the output that will limit the internal power dissipa-
tion if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to the adjacent
positive power-supply pin can destroy the amplifier. If addi-
tional short-circuit protection is required, consider a small
series resistor in the power-supply leads. This resistor will,
under heavy output loads, reduce the available output volt-
age swing. A 5

series resistor in each power-supply lead

will limit the internal power dissipation to less than 1W for an
output short-circuit, while decreasing the available output
voltage swing only 0.25V for up to 50mA desired load
currents. Always place the 0.1

F power-supply decoupling

capacitors after these supply current limiting resistors directly
on the supply pins.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC, including additional
external capacitance which may be recommended to im-
prove ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA2683 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier's open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.

The Typical Characteristics show the recommended R

LOAD

and the resulting frequency response at the load. The

resistor shown in parallel with the load capacitor is a

measurement path and may be omitted. The required series
resistor value may be reduced by increasing the feedback

OPA2683

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resistor value from its nominal recommended value. This will
increase the phase margin for the loop gain, allowing a lower
series resistor to be effective in reducing the peaking due to
capacitive load. SPICE simulation can be effectively used to
optimize this approach. Parasitic capacitive loads greater
than 5pF can begin to degrade the performance of the
OPA2683. Long PC board traces, unmatched cables, and
connections to multiple devices can easily cause this value
to be exceeded. Always consider this effect carefully, and
add the recommended series resistor as close as possible to
the OPA2683 output pin (see Board Layout Guidelines).

DISTORTION PERFORMANCE

The OPA2683 provides very low distortion in a low-power
part. The CFB

PLUS

architecture also gives two significant

areas of distortion improvement. First, in operating regions
where the 2nd-harmonic distortion due to output stage
nonlinearities is very low (frequencies < 1MHz, low output
swings into light loads) the linearization at the inverting node
provided by the CFB

PLUS

design gives 2nd-harmonic distor-

tions that extend into the 90dBc region. Previous current-
feedback amplifiers have been limited to approximately
85dBc due to the nonlinearities at the inverting input. The
second area of distortion improvement comes in a distortion
performance that is largely gain independent. To the extent
that the distortion at a specific output power is output stage
dependent, 3rd-harmonics particularly, and to a lesser ex-
tend 2nd-harmonic distortion, remains constant as the gain
increases. This is due to the constant loop gain versus signal
gain provided by the CFB

PLUS

design. As shown in the

Typical Characteristics, while the 3rd-harmonic is constant
with gain, the 2nd-harmonic degrades at higher gains. This
is largely due to board parasitic issues. Slightly imbalanced
load return currents will couple into the gain resistor to cause
a portion of the 2nd-harmonic distortion. At high gains, this
imbalance has more gain to the output giving increased
2nd-harmonic distortion.

Relative to alternative amplifiers with < 2mA supply current,
the OPA2683 holds much lower distortion at higher frequen-
cies (> 5MHz) and to higher gains. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with a
lower 3rd-harmonic component. Focusing then on the 2nd-
harmonic, increasing the load impedance improves distortion
directly. Remember that the total load includes the feedback
network--in the noninverting configuration (see Figure 1) this
is the sum of R

+ R

, while in the inverting configuration it

is just R

. Also, providing an additional supply decoupling

capacitor (0.1

F) between the supply pins (for bipolar opera-

tion) improves the 2nd-order distortion slightly (3dB to 6dB).

In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. A low-power part like
the OPA2683 includes quiescent boost circuits to provide the
full-power bandwidth shown in the Typical Characteristics.
These act to increase the bias in a very linear fashion only
when high slew rate or output power are required. This also
acts to actually reduce the distortion slightly at higher output
power levels. The Typical Characteristics show the 2nd-

harmonic holding constant from 500mV

to 5V

outputs

while the 3rd-harmonics actually decrease with increasing
output power.

The OPA2683 has an extremely low 3rd-order harmonic
distortion, particularly for light loads and at lower frequen-
cies. This also gives low 2-tone, 3rd-order intermodulation
distortion as shown in the Typical Characteristics. Since the
OPA2683 includes internal power boost circuits to retain
good full-power performance at high frequencies and out-
puts, it does not show a classical 2-tone, 3rd-order
intermodulation intercept characteristic. Instead, it holds rela-
tively low and constant 3rd-order intermodulation spurious
levels over power. The Typical Characteristics show this
spurious level as a dBc below the carrier at fixed center
frequencies swept over single-tone power at a matched 50

load. These spurious levels drop significantly (> 12dB) for
lighter loads than the 100

used in that plot. Converter

inputs, for instance, will see

82dBc 3rd-order spurious to

10MHz for full-scale inputs. For even lower 3rd-order
intermodulation distortion to much higher frequencies, con-
sider the OPA2691.

NOISE PERFORMANCE

Wideband current-feedback op amps generally have a higher
output noise than comparable voltage-feedback op amps.
The OPA2683 offers an excellent balance between voltage
and current noise terms to achieve low output noise in a low-
power amplifier. The inverting current noise (11.6pA/

Hz) is

lower than most other current-feedback op amps while the
input voltage noise (4.4nV/

Hz) is lower than any unity-gain

stable, comparable slew rate, < 5mA/ch voltage-feedback op
amp. This low input voltage noise was achieved at the price
of higher noninverting input current noise (5.1pA/

Hz). As

long as the AC source impedance looking out of the
noninverting node is less than 200

, this current noise will

not contribute significantly to the total output noise. The op
amp input voltage noise and the two input current noise
terms combine to give low output noise under a wide variety
of operating conditions. Figure 13 shows the op amp noise
analysis model with all the noise terms included. In this
model, all noise terms are taken to be noise voltage or
current density terms in either nV/

Hz or pA/

Hz.

FIGURE 13. Op Amp Noise Analysis Model.

4kT

1/2

OPA2683

4kT = 1.6E 20J

at 290

kTR

4kTR

OPA2683

SBOS244C

www.ti.com

The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 4 shows the general form for the
output noise voltage using the terms presented in Figure 13.

(4)

kTR

I R

kTR NG

BN S

BI F

(

)

(

)

Dividing this expression by the noise gain (NG = (1 + R

))

will give the equivalent input referred spot noise voltage at
the noninverting input, as shown in Equation 5.

(5)

kTR

I R

kTR

BN S

BI F

(

)

Evaluating these two equations for the OPA2683 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 15.2nV/

Hz and a total equivalent input spot

noise voltage of 7.6nV/

Hz. This total input referred spot

noise voltage is higher than the 4.4nV/

Hz specification for

the op amp voltage noise alone. This reflects the noise
added to the output by the inverting current noise times the
feedback resistor. As the gain is increased, this fixed output
noise power term contributes less to the total output noise
and the total input referred voltage noise given by Equation 5
will approach just the 4.4nV/

Hz of the op amp itself. For

example, going to a gain of +20 in the circuit of Figure 1,
adjusting only the gain resistor to 50

, will give a total input

referred noise of 4.6nV/

Hz. A more complete description of

op amp noise analysis can be found in TI application note
AB-103,

Noise Analysis for High-Speed Op Amps (SBOA066),

located at www.ti.com.

DC ACCURACY AND OFFSET CONTROL

A current-feedback op amp like the OPA2683 provides
exceptional bandwidth in high gains, giving fast pulse settling
but only moderate DC accuracy. The Electrical Characteris-
tics show an input offset voltage comparable to high slew
rate voltage-feedback amplifiers. The two input bias currents,
however, are somewhat higher and are unmatched. Whereas
bias current cancellation techniques are very effective with
most voltage-feedback op amps, they do not generally re-
duce the output DC offset for wideband current-feedback op
amps. Since the two input bias currents are unrelated in both
magnitude and polarity, matching the source impedance
looking out of each input to reduce their error contribution to
the output is ineffective. Evaluating the configuration of
Figure 1, using worst-case +25

C input offset voltage and the

two input bias currents, gives a worst-case output offset
range equal to:

(NG · V

) + (I

· R

/ 2 · NG)

· R

)

where NG = noninverting signal gain

(2 · 3.5mV)

(4.5

A · 25

· 2)

(953

· 10mA)

7.0mV + 0.23mV

9.5mV

16.73mV

While the last term, the inverting bias current error, is
dominant in this low-gain circuit, the input offset voltage will
become the dominant DC error term as the gain exceeds
5V/V. Where improved DC precision is required in a high-
speed amplifier, consider the OPA656 single and OPA2822
dual voltage-feedback amplifiers.

THERMAL ANALYSIS

The OPA2683 will not require external heatsinking for most
applications. Maximum desired junction temperature will set
the maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 150

Operating junction temperature (T

) is given by T

+ P

The total internal power dissipation (P

) is the sum of

quiescent power (P

) and additional power dissipated in the

output stage (P

) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total
supply voltage across the part. P

will depend on the

required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition P

= V

/(4 · R

)

where R

includes feedback network loading.

Note that it is the power in the output stage and not into the
load that determines internal power dissipation.

As an absolute worst-case example, compute the maximum
T

using an OPA2683IDCN (SOT23-8 package) in the circuit

of Figure 1 operating at the maximum specified ambient
temperature of +85

C with both outputs driving a grounded

100

load to 2.5V

= 10V · 2.1mA + 2 · (5

/(4 · (100

|| 1.9k

))) = 153mW

Maximum T

= +85

C + (0.153W · 150

C/W) = 108

This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
than this since an absolute worst-case output stage power in
both channels simultaneously was assumed in this calculation.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency am-
plifier like the OPA2683 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:

Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on
the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To re-
duce unwanted capacitance, a window around the sig-
nal I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.

Minimize the distance (< 0.25") from the power-sup-
ply pins to high-frequency 0.1

F decoupling capaci-

tors. At the device pins, the ground and power-plane

OPA2683

SBOS244C

www.ti.com

layout should not be in close proximity to the signal I/O
pins. Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling capaci-
tors. The power-supply connections should always be
decoupled with these capacitors. An optional supply
decoupling capacitor (0.01

F) across the two power

supplies (for bipolar operation) will improve 2nd-har-
monic distortion performance. Larger (2.2

F to 6.8

decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may
be placed somewhat farther from the device and may be
shared among several devices in the same area of the
PC board.

Careful selection and placement of external compo-
nents will preserve the high-frequency performance
of the OPA2683. Resistors should be a very low reac-
tance type. Surface-mount resistors work best and allow
a tighter overall layout. Metal film and carbon composi-
tion axially-leaded resistors can also provide good high-
frequency performance. Again, keep their leads and PC-
board trace length as short as possible. Never use
wirewound type resistors in a high-frequency applica-
tion. Since the output pin and inverting input pin are the
most sensitive to parasitic capacitance, always position
the feedback and series output resistor, if any, as close
as possible to the output pin. Other network compo-
nents, such as noninverting input termination resistors,
should also be placed close to the package. The fre-
quency response is primarily determined by the feed-
back resistor value as described previously. Increasing
its value will reduce the peaking at higher gains, while
decreasing it will give a more peaked frequency re-
sponse at lower gains. The 800

feedback resistor used

in the Electrical Characteristics at a gain of +2 on

supplies is a good starting point for design. Note that a
953

feedback resistor, rather than a direct short, is

required for the unity-gain follower application. A cur-
rent-feedback op amp requires a feedback resistor even
in the unity-gain follower configuration to control stability.

Connections to other wideband devices on the board
may be made with short direct traces or through on-
board transmission lines. For short connections, con-
sider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the
total capacitive load and set R

from the plot of recom-

mended Rs vs C

LOAD

. Low parasitic capacitive loads

(< 5pF) may not need an R

since the OPA2683 is

nominally compensated to operate with a 2pF parasitic
load. If a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is ac-
ceptable, implement a matched impedance transmis-
sion line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline
layout techniques). A 50

environment is normally not

necessary onboard, and in fact a higher impedance
environment will improve distortion, as shown in the

distortion versus load plots. With a characteristic board
trace impedance defined based on board material and
trace dimensions, a matching series resistor into the
trace from the output of the OPA2683 is used, as well as
a terminating shunt resistor at the input of the destina-
tion device. Remember also that the terminating imped-
ance will be the parallel combination of the shunt resistor
and the input impedance of the destination device; this
total effective impedance should be set to match the
trace impedance. The high output voltage and current
capability of the OPA2683 allows multiple destination
devices to be handled as separate transmission lines,
each with their own series and shunt terminations. If the
6dB attenuation of a doubly-terminated transmission line
is unacceptable, a long trace can be series-terminated
at the source end only. Treat the trace as a capacitive
load in this case and set the series resistor value as
shown in the plot of Rs vs C

LOAD

. This will not preserve

signal integrity as well as a doubly-terminated line. If the
input impedance of the destination device is low, there
will be some signal attenuation due to the voltage divider
formed by the series output into the terminating imped-
ance.

Socketing a high-speed part like the OPA2683 is not
recommended. The additional lead length and pin-to-
pin capacitance introduced by the socket can create an
extremely troublesome parasitic network which can make
it almost impossible to achieve a smooth, stable fre-
quency response. Best results are obtained by soldering
the OPA2683 onto the board.

INPUT AND ESD PROTECTION

The OPA2683 is built using a very high-speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry de-
vices. These breakdowns are reflected in the Absolute Maxi-
mum Ratings table where an absolute maximum 13V across
the supply pins is reported. All device pins have limited ESD
protection using internal diodes to the power supplies, as
shown in Figure 14.

These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with

15V supply parts

driving into the OPA2683), current-limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.

FIGURE 14. Internal ESD Protection.

External

Internal
Circuitry

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