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Электронный компонент: OPA2691I-14DR

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Dual Wideband, Current-Feedback
OPERATIONAL AMPLIFIER With Disable
DESCRIPTION
The OPA2691 sets a new level of performance for broadband dual
current-feedback op amps. Operating on a very low 5.1mA/ch
supply current, the OPA2691 offers a slew rate and output power
normally associated with a much higher supply current. A new
output stage architecture delivers a high output current with minimal
voltage headroom and crossover distortion. This gives exceptional
single-supply operation. Using a single +5V supply, the OPA2691
can deliver a 1V to 4V output swing with over 150mA drive current
and 190MHz bandwidth. This combination of features makes the
OPA2691 an ideal RGB line driver or single-supply Analog-to-Digital
Converter (ADC) input driver.
FEATURES
q
FLEXIBLE SUPPLY RANGE:
+5V to +12V Single Supply
2.5V to
6V Dual Supply
q
WIDEBAND +5V OPERATION: 190MHz (G = +2)
q
UNITY-GAIN STABLE: 280MHz (G = 1)
q
HIGH OUTPUT CURRENT: 190mA
q
OUTPUT VOLTAGE SWING:
4.0V
q
HIGH SLEW RATE: 2100V/
s
q
LOW SUPPLY CURRENT: 5.1mA/ch
q
LOW DISABLED CURRENT: 150
A/ch
APPLICATIONS
q
xDSL LINE DRIVER / RECEIVER
q
MATCHED I/Q CHANNEL AMPLIFIER
q
BROADBAND VIDEO BUFFERS
q
HIGH-SPEED IMAGING CHANNELS
q
PORTABLE INSTRUMENTS
q
DIFFERENTIAL ADC DRIVERS
q
ACTIVE FILTERS
q
WIDEBAND INVERTING SUMMING
The OPA2691's low 5.1mA/ch supply current is precisely trimmed at
25
C. This trim, along with low drift over temperature, ensures lower
maximum supply current than competing products. System power
may be further reduced by using the optional disable control pin
(SO-14 only). Leaving this disable pin open, or holding it HIGH,
gives normal operation. If pulled LOW, the OPA2691 supply current
drops to less than 150
A/ch while the output goes into a high
impedance state. This feature may be used for power savings.
Single-Supply ADSL Upstream Driver
100
2k
2k
1
F
12.4
100
2Vp-p
324
324
1/2
OPA2691
1/2
OPA2691
+12V
1:2
15Vp-p
12.4
+6.0V
OPA2691 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
Voltage-Feedback
OPA690
OPA2690
OPA3690
Current-Feedback
OPA691
OPA2681
OPA3691
Fixed Gain
OPA692
--
OPA3692
OPA2
691
OPA2
691
OPA2691
SBOS224A DECEMBER 2001 REVISED OCTOBER 2002
www.ti.com
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
18
17
16
15
14
13
12
Frequency (MHz)
0.1
1
10
100 200
SINGLE-SUPPLY ADSL UPSTREAM DRIVER
SMALL-SIGNAL FREQUENCY RESPONSE
Gain (dB)
OPA2691
2
SBOS224A
www.ti.com
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
OPA2691
SO-8
D
40
C to +85
C
OPA2691
OPA2691ID
Rails, 100
"
"
"
"
"
OPA2691IDR
Tape and Reel, 2500
OPA2691
SO-14
D
40
C to +85
C
OPA2691
OPA2691I-14D
Rails, 58
"
"
"
"
"
OPA2691I-14DR
Tape and Reel, 2500
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
1
2
3
4
5
6
7
NC = No Connection
14
13
12
11
10
9
8
In A
+In A
DIS A
V
S
DIS B
+In B
In B
Out A
NC
NC
+V
S
NC
NC
Out B
ABSOLUTE MAXIMUM RATINGS
(1)
Power Supply ...............................................................................
6.5V
DC
Internal Power Dissipation
(2)
............................ See Thermal Information
Differential Input Voltage ..................................................................
1.2V
Input Voltage Range ...........................................................................
V
S
Storage Temperature Range: D, 14D ............................ 40
C to +125
C
Lead Temperature (soldering, 10s) .............................................. +300
C
Junction Temperature (T
J
) ........................................................... +175
C
ESD Performance:
HBM .............................................................................................. 2000V
CDM .............................................................................................. 1500V
NOTES:: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability. (2) Packages
must be derated based on specified
JA
. Maximum T
J
must be observed.
PIN CONFIGURATIONS
Top View
SO-8
SO-14
1
2
3
4
8
7
6
5
+V
S
Out B
In B
+In B
Out A
In A
+In A
V
S
PACKAGE/ORDERING INFORMATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
OPA2691
3
SBOS224A
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S
=
5V
Boldface limits are tested at +25
C.
R
F
= 402
, R
L
= 100
, and G = +2
,
(see Figure 1 for AC performance only), unless otherwise noted.
OPA2691ID, I-14D
TYP
MIN/MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
70
C
(2)
+85
C
(2)
UNITS
MAX
LEVEL
(3)
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (V
O
= 0.5Vp-p)
G = +1, R
F
= 453
280
MHz
typ
C
G = +2, R
F
= 402
225
200
190
180
MHz
min
B
G = +5, R
F
= 261
210
MHz
typ
C
G = +10, R
F
= 180
200
MHz
typ
C
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
= 0.5Vp-p
90
40
35
20
MHz
min
B
Peaking at a Gain of +1
R
F
= 453, V
O
= 0.5Vp-p
0.2
1
1.5
2
dB
max
B
Large-Signal Bandwidth
G = +2, V
O
= 5Vp-p
200
MHz
typ
C
Slew Rate
G = +2, 4V Step
2100
1400
1375
1350
V/
s
min
B
Rise-and-Fall Time
G = +2, V
O
= 0.5V Step
1.6
ns
typ
C
G = +2, 5V Step
1.9
ns
typ
C
Settling Time to 0.02%
G = +2, V
O
= 2V Step
12
ns
typ
C
0.1%
G = +2, V
O
= 2V Step
8
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, V
O
= 2Vp-p
2nd-Harmonic
R
L
= 100
70
63
60
58
dBc
max
B
R
L
500
79
70
67
65
dBc
max
B
3rd-Harmonic
R
L
= 100
74
72
70
68
dBc
max
B
R
L
500
93
87
82
78
dBc
max
B
Input Voltage Noise
f > 1MHz
1.7
2.5
2.9
3.1
nV/
Hz
max
B
Noninverting Input Current Noise
f > 1MHz
12
14
15
15
pA/
Hz
max
B
Inverting Input Current Noise
f > 1MHz
15
17
18
19
pA/
Hz
max
B
Differential Gain
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150
0.07
%
typ
C
R
L
= 37.5
0.17
%
typ
C
Differential Phase
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150
0.02
deg
typ
C
R
L
= 37.5
0.07
deg
typ
C
Channel-to-Channel Crosstalk
f = 5MHz
86
dBc
typ
C
DC PERFORMANCE
(4)
Open-Loop Transimpedance Gain (Z
OL
)
V
O
= 0V, R
L
= 100
225
125
110
100
k
min
A
Input Offset Voltage
V
CM
= 0V
0.8
3
3.7
4.3
mV
max
A
Average Offset Voltage Drift
V
CM
= 0V
12
20
V/
C
max
B
Noninverting Input Bias Current
V
CM
= 0V
+15
+35
+43
+45
A
max
A
Average Noninverting Input Bias Current Drift
V
CM
= 0V
300
300
nA/
C
max
B
Inverting Input Bias Current
V
CM
= 0V
5
25
30
40
A
max
A
Average Inverting Input Bias Current Drift
V
CM
= 0V
90
200
nA
/C
max
B
INPUT
Common-Mode Input Range (CMIR)
(5)
3.5
3.4
3.3
3.2
V
min
A
Common-Mode Rejection (CMRR)
V
CM
= 0V
56
52
51
50
dB
min
A
Noninverting Input Impedance
100 || 2
k
|| pF
typ
C
Inverting Input Resistance (R
I
)
Open-Loop
37
typ
C
OUTPUT
Voltage Output Swing
No Load
4.0
3.8
3.7
3.6
V
min
A
100
Load
3.9
3.7
3.6
3.3
V
min
A
Current Output, Sourcing
V
O
= 0
+190
+160
+140
+100
mA
min
A
Current Output, Sinking
V
O
= 0
190
160
140
100
mA
min
A
Short-Circuit Current
250
mA
typ
C
Closed-Loop Output Impedance
G = +2, f = 100kHz
0.03
typ
C
DISABLE (Disabled LOW) (SO-14 only)
Power-Down Supply Current (+V
S
)
V
DIS
= 0, Both Channels
300
600
700
800
A
max
A
Disable Time
V
IN
= 1V
DC
400
ns
typ
C
Enable Time
V
IN
= 1V
DC
25
ns
typ
C
Off Isolation
G = +2, 5MHz
70
dB
typ
C
Output Capacitance in Disable
4
pF
typ
C
Turn-On Glitch
G = +2, R
L
= 150
, V
IN
= 0
50
mV
typ
C
Turn-Off Glitch
G = +2, R
L
= 150
, V
IN
= 0
20
mV
typ
C
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
Control Pin Input Bias Current (DIS )
V
DIS
= 0, Each Channel
75
130
150
160
A
max
A
POWER SUPPLY
Specified Operating Voltage
5
V
typ
C
Maximum Operating Voltage Range
6
6
6
V
max
A
Max Quiescent Current
V
S
=
5V, Both Channels
10.2
10.6
11.2
11.5
mA
max
A
Min Quiescent Current
V
S
=
5V, Both Channels
10.2
9.8
9.2
8.9
mA
min
A
Power-Supply Rejection Ratio (PSRR)
Input Referred
58
52
50
49
dB
min
A
TEMPERATURE RANGE
Specification: D, 14D
40 to +85
C
typ
C
Thermal Resistance,
JA
Junction-to-Ambient
D
SO-8
125
C/W
typ
C
14D
SO-14
100
C/W
typ
C
NOTES: (1) Junction temperature = ambient for +25
C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +15
C
at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25
C. Over-temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. V
CM
is the input common-mode
voltage. (5) Tested < 3dB below minimum specified CMRR at
CMIR limits.
OPA2691
4
SBOS224A
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S
= +5V
Boldface limits are tested at +25
C.
R
F
= 453
, R
L
= 100
to V
S
/2, and G = +2
,
(see Figure 1 for AC performance only), unless otherwise noted.
OPA2691ID, I-14D
TYP
MIN / MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(1)
70
C
(2)
+85
C
(2)
UNITS
MAX
LEVEL
(3)
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth (V
O
= 0.5Vp-p)
G = +1, R
F
= 499
210
MHz
typ
C
G = +2, R
F
= 453
190
168
160
140
MHz
min
B
G = +5, R
F
= 340
180
MHz
typ
C
G = +10, R
F
= 180
155
MHz
typ
C
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
< 0.5Vp-p
90
40
30
25
MHz
min
B
Peaking at a Gain of +1
R
F
= 649
, V
O
< 0.5Vp-p
0.2
1
2.5
3.0
dB
max
B
Large-Signal Bandwidth
G = +2, V
O
= 2Vp-p
210
MHz
typ
C
Slew Rate
G = +2, 2V Step
850
600
575
550
V/
s
min
B
Rise-and-Fall Time
G = +2, V
O
= 0.5V Step
2.0
ns
typ
C
G = +2, V
O
= 2V Step
2.3
ns
typ
C
Settling Time to 0.02%
G = +2, V
O
= 2V Step
14
ns
typ
C
0.1%
G = +2, V
O
= 2V Step
10
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, V
O
= 2Vp-p
2nd-Harmonic
R
L
= 100
to V
S
/ 2
66
58
57
56
dBc
max
B
R
L
500
to V
S
/2
73
65
63
62
dBc
max
B
3rd-Harmonic
R
L
= 100
to V
S
/ 2
71
68
67
65
dBc
max
B
R
L
500
to V
S
/2
77
72
70
69
dBc
max
B
Input Voltage Noise
f > 1MHz
1.7
2.5
2.9
3.1
nV/
Hz
max
B
Noninverting Input Current Noise
f > 1MHz
12
14
15
15
pA/
Hz
max
B
Inverting Input Current Noise
f > 1MHz
15
17
18
19
pA/
Hz
max
B
DC PERFORMANCE
(4)
Open-Loop Transimpedance Gain (Z
OL
)
V
O
= V
S
/2, R
L
= 100
to V
S
/2
200
100
90
80
k
min
A
Input Offset Voltage
V
CM
= 2.5V
0.8
3.5
4.1
4.8
mV
max
A
Average Offset Voltage Drift
V
CM
= 2.5V
12
20
V/
C
max
B
Noninverting Input Bias Current
V
CM
= 2.5V
+20
+40
+48
+56
A
max
A
Average Noninverting Input Bias Current Drift
V
CM
= 2.5V
250
250
nA/
C
max
B
Inverting Input Bias Current
V
CM
= 2.5V
5
20
25
35
A
max
A
Average Inverting Input Bias Current Drift
V
CM
= 2.5V
112
250
nA /
C
max
B
INPUT
Least Positive Input Voltage
(5)
1.5
1.6
1.7
1.8
V
max
A
Most Positive Input Voltage
(5)
3.5
3.4
3.3
3.2
V
min
A
Common-Mode Rejection (CMRR)
V
CM
= 2.5V
54
50
49
48
dB
min
A
Noninverting Input Impedance
100 || 2
k
|| pF
typ
C
Inverting Input Resistance (R
I
)
Open-Loop
40
typ
C
OUTPUT
Most Positive Output Voltage
No Load
4
3.8
3.7
3.5
V
min
A
R
L
= 100
, 2.5V
3.9
3.7
3.6
3.4
V
min
A
Least Positive Output Voltage
No Load
1
1.2
1.3
1.5
V
max
A
R
L
= 100
, 2.5V
1.1
1.3
1.4
1.6
V
max
A
Current Output, Sourcing
V
O
= V
S
/2
+160
+120
+100
+80
mA
min
A
Current Output, Sinking
V
O
= V
S
/2
160
120
100
80
mA
min
A
Closed-Loop Output Impedance
G = +2, f = 100kHz
0.03
typ
C
DISABLE (Disabled LOW) (SO-14 only)
Power-Down Supply Current (+V
S
)
V
DIS
= 0, Both Channels
300
600
700
800
A
max
A
Off Isolation
G = +2, 5MHz
65
dB
typ
C
Output Capacitance in Disable
4
pF
typ
C
Turn-On Glitch
G = +2, R
L
= 150
, V
IN
= V
S
/2
50
mV
typ
C
Turn-Off Glitch
G = +2, R
L
= 150
, V
IN
= V
S
/2
20
mV
typ
C
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
Control Pin Input Bias Current (DIS )
V
DIS
= 0, Each Channel
75
130
150
160
A
typ
C
POWER SUPPLY
Specified Single-Supply Operating Voltage
5
V
typ
C
Maximum Single-Supply Operating Voltage
12
12
12
V
max
A
Max Quiescent Current
V
S
= +5V, Both Channels
9
9.6
10
10.4
mA
max
A
Min Quiescent Current
V
S
= +5V, Both Channels
9
8.2
8.0
7.8
mA
min
A
Power-Supply Rejection Ratio (+PSRR)
Input Referred
55
dB
typ
C
TEMPERATURE RANGE
Specification: D, 14D
40 to +85
C
typ
C
Thermal Resistance,
JA
D
SO-8
125
C/W
typ
C
14D
SO-14
100
C/W
typ
C
NOTES: (1) Junction temperature = ambient for +25
C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +15
C
at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25
C. Over-temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out of node. V
CM
is the input common-mode
voltage. (5) Tested < 3dB below minimum specified CMRR at
CMIR limits.
OPA2691
5
SBOS224A
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
G = +2, R
F
= 402
, R
L
= 100
, unless otherwise noted (see Figure 1 for AC performance only).
1
0
1
2
3
4
5
6
7
8
Frequency (25MHz/div)
0
250MHz
125MHz
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
G = +10, R
F
= 180
G = +5, R
F
= 261
G = +1, R
F
= 453
G = +2,
R
F
= 402
V
O
= 0.5Vp-p
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Frequency (25MHz/div)
0
250MHz
125MHz
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (0.5dB/div)
G = +2, R
L
= 100
4Vp-p
7Vp-p
1Vp-p
2Vp-p
+400
+300
+200
+100
0
100
200
300
400
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
G = +2
V
O
= 0.5Vp-p
+4
+3
+2
+1
0
1
2
3
4
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (1V/div)
G = +2
V
O
= 5Vp-p
0.2
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
Number of 150
Loads
1
2
dG
dG
dP
dP
3
4
COMPOSITE VIDEO dG/dP
dG/dP (%/
)
1/2
OPA2691
402
+5
5
402
Video
Loads
Video
In
Optional 1.3k
Pull-Down
No Pull-Down
With 1.3k
Pull-Down
55
60
65
70
75
80
85
90
95
100
Frequency (MHz)
1
10
100
CHANNEL-TO-CHANNEL CROSSTALK
Crosstalk (5dB/div)
OPA2691
6
SBOS224A
www.ti.com
TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
G = +2, R
F
= 402
, R
L
= 100
, unless otherwise noted (see Figure 1 for AC performance only).
60
65
70
75
80
85
90
95
100
HARMONIC DISTORTION vs LOAD RESISTANCE
Load Resistance (
)
100
1000
Harmonic Distortion (dBc)
V
O
= 2Vp-p
f = 5MHz
3rd-Harmonic
2nd-Harmonic
60
65
70
75
80
85
HARMONIC DISTORTION vs SUPPLY VOLTAGE
Supply Voltage (V)
2.5
3
3.5
4
4.5
6
5.5
5
Harmonic Distortion (dBc)
V
O
= 2Vp-p
R
L
= 100
f = 5MHz
3rd-Harmonic
2nd-Harmonic
50
60
70
80
90
100
HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1
1
10
20
Harmonic Distortion (dBc)
dBc = dB Below Carrier
V
O
= 2Vp-p
R
L
= 100
3rd-Harmonic
2nd-Harmonic
65
70
75
80
85
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1
1
5
Harmonic Distortion (dBc)
R
L
= 100
f = 5MHz
3rd-Harmonic
2nd-Harmonic
50
60
70
80
90
HARMONIC DISTORTION vs NONINVERTING GAIN
Gain (V/V)
1
10
Harmonic Distortion (dBc)
V
O
= 2Vp-p
R
L
= 100
f = 5MHz
2nd-Harmonic
3rd-Harmonic
50
60
70
80
90
HARMONIC DISTORTION vs INVERTING GAIN
Inverting Gain (V/V)
1
10
Harmonic Distortion (dBc)
V
O
= 2Vp-p
R
L
= 100
f = 5MHz
R
F
= 402
3rd-Harmonic
2nd-Harmonic
OPA2691
7
SBOS224A
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TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
G = +2, R
F
= 402
, R
L
= 100
, unless otherwise noted (see Figure 1 for AC performance only).
100
10
1
INPUT VOLTAGE AND CURRENT NOISE DENSITY
Frequency (Hz)
100
1k
10k
100k
1M
10M
Current Noise (pA/
Hz)
Voltage Noise (nV/
Hz)
Noninverting Input Current Noise (12pA/
Hz)
Inverting Input Current Noise (15pA/
Hz)
Voltage Noise (1.7nV/
Hz)
30
40
50
60
70
80
90
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
Single-Tone Load Power (dBm)
8
6
4
2
0
2
4
6
8
10
3rd-Order Spurious Level (dBc)
dBc = dB below carriers
50MHz
20MHz
10MHz
Load Power at Matched 50
Load
70
60
50
40
30
20
10
0
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1
10
100
1k
R
S
(
)
9
6
3
0
3
6
9
Frequency (25MHz/div)
0
250MHz
125MHz
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
1/2
OPA2691
R
S
V
IN
V
O
C
L
1k
402
402
1k
is optional.
C
L
= 22pF
C
L
= 10pF
C
L
= 47pF
C
L
= 100pF
2.0
1.6
1.2
0.8
0.4
0
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
Time (200ns/div)
Output Voltage (400mV/div)
6.0
4.0
2.0
0
V
DIS
(2V/div)
V
DIS
Output Voltage
V
IN
= +1V
DISABLED FEEDTHROUGH vs FREQUENCY
45
50
55
60
65
70
75
80
85
90
95
100
Frequency (MHz)
1
0.3
10
100
Feedthrough (5dB/div)
Forward
V
DIS
= 0
Reverse
OPA2691
8
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TYPICAL CHARACTERISTICS: V
S
=
5V
(Cont.)
G = +2, R
F
= 402
, R
L
= 100
, unless otherwise noted (see Figure 1 for AC performance only).
5
4
3
2
1
0
1
2
3
4
5
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
I
O
(mA)
150
200
250
300
50
100
0
+100
+50
+200
+150
+250 +300
V
O
(V)
100
Load Line
50
Load Line
25
Load Line
Output Current Limit
1W Internal
Power Limit
Single Channel
1W Internal
Power Limit
Single Channel
Output Current Limit
65
60
55
50
45
40
35
30
25
20
CMRR AND PSRR vs FREQUENCY
Frequency (Hz)
1k
10k
100k
1M
10M
100M
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
+PSRR
CMRR
PSRR
10
1
0.1
0.01
CLOSED-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
Frequency (Hz)
10k
100M
100k
1M
10M
Output Impedance (
)
1/2
OPA2691
402
+5
5
402
50
Z
O
120
100
80
60
40
20
0
OPEN-LOOP TRANSIMPEDANCE GAIN/PHASE
Frequency (Hz)
10k
100k
1M
10M
100M
1G
Transimpedance Gain (20dB/div)
0
40
80
120
160
200
240
Transimpedance Phase (40
/div)
| Z
OL
|
Z
OL
2
1.5
1
0.5
0
0.5
1
1.5
2
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (
C)
50
25
0
25
50
75
100
125
Input Offset Voltage (mV)
40
30
20
10
0
10
20
30
40
Input Bias Currents (
A)
Noninverting Input Bias Current (I
B+
)
Inverting Input
Bias Current (I
B
)
Input Offset
Voltage (V
OS
)
16
14
12
10
8
6
250
200
150
100
50
0
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (
C)
50
25
0
25
50
75
100
125
Supply Current (2mA/div)
Output Current (50mA/div)
Quiescent Supply Current
Both Channels
Sourcing Output Current
Sinking Output Current
OPA2691
9
SBOS224A
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TYPICAL CHARACTERISTICS: V
S
= +5V
G = +2, R
F
= 499
, R
L
= 100
to +2.5V, unless otherwise noted (see Figure 2 for AC performance only).
1
0
1
2
3
4
5
6
7
8
Frequency (25MHz/div)
0
250MHz
125MHz
SMALL-SIGNAL FREQUENCY RESPONSE
Normalized Gain (1dB/div)
G = +2,
R
F
= 453
G = +10,
R
F
= 180
G = +5,
R
F
= 340
G = +1,
R
F
= 499
V
O
= 0.5Vp-p
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Frequency (25MHz/div)
0
250MHz
125MHz
LARGE-SIGNAL FREQUENCY RESPONSE
Gain (0.5dB/div)
V
O
= 0.5Vp-p
V
O
= 2Vp-p
G = +2
R
L
= 100
to 2.5V
V
O
= 1Vp-p
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
G = +2
V
O
= 0.5Vp-p
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (400mV/div)
G = +2
V
O
= 2Vp-p
60
50
40
30
20
10
0
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1
10
100
R
S
(
)
9
6
3
0
3
6
9
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (25MHz/div)
0
250MHz
125MHz
Normalized Gain to Capacitive Load (dB)
C
L
= 22pF
C
L
= 10pF
C
L
= 47pF
C
L
= 100pF
1/2
OPA2691
453
453
57.6
806
806
1k
VI
+5V
0.1
F
VO
RS
CL
0.1
F
1k
is optional.
OPA2691
10
SBOS224A
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= +5V
(Cont.)
G = +2, R
F
= 499
, R
L
= 100
to +2.5V, unless otherwise noted (see Figure 2 for AC performance only).
60
65
70
75
80
HARMONIC DISTORTION vs LOAD RESISTANCE
Resistance (
)
100
1000
Harmonic Distortion (dBc)
V
O
= 2Vp-p
f
= 5MHz
2nd-Harmonic
3rd-Harmonic
HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
0.1
1
10
20
Harmonic Distortion (dBc)
50
60
70
80
90
V
O
= 2Vp-p
R
L
= 100
to 2.5V
2nd-Harmonic
3rd-Harmonic
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Output Voltage Swing (Vp-p)
0.1
1
3
Harmonic Distortion (dBc)
60
65
70
75
80
R
L
= 100
to 2.5V
f = 5MHz
2nd-Harmonic
3rd-Harmonic
30
40
50
60
70
80
90
100
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
Single-Tone Load Power (dBm)
14
12
10
8
6
4
2
0
2
3rd-Order Spurious Level (dBc)
dBc = dB below carriers
50MHz
20MHz
10MHz
Load Power at Matched 50
Load
OPA2691
11
SBOS224A
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APPLICATIONS INFORMATION
WIDEBAND CURRENT-FEEDBACK OPERATION
The OPA2691 gives the exceptional AC performance of a
wideband current-feedback op amp with a highly linear, high-
power output stage. Requiring only 5.1mA/ch quiescent cur-
rent, the OPA2691 will swing to within 1V of either supply rail
and deliver in excess of 160mA tested at room temperature.
This low output headroom requirement, along with supply
voltage independent biasing, gives remarkable single (+5V)
supply operation. The OPA2691 will deliver greater than 200MHz
bandwidth driving a 2Vp-p output into 100
on a single +5V
supply. Previous boosted output stage amplifiers have typically
suffered from very poor crossover distortion as the output
current goes through zero. The OPA2691 achieves a compa-
rable power gain with much better linearity. The primary
advantage of a current-feedback op amp over a voltage-
feedback op amp is that AC performance (bandwidth and
distortion) is relatively independent of signal gain. For similar
AC performance with improved DC accuracy, consider the high
slew rate, unity-gain stable, voltage-feedback OPA2690.
Figure 1 shows the DC-coupled, gain of +2, dual power-
supply circuit configuration used as the basis of the
5V
Electrical Characteristics and Typical Characteristics. For
test purposes, the input impedance is set to 50
with a
resistor to ground and the output impedance is set to 50
with a series output resistor. Voltage swings reported in the
electrical characteristics are taken directly at the input and
output pins while load powers (dBm) are defined at a matched
50
load. For the circuit of Figure 1, the total effective load
will be 100
|| 804
= 89
. The disable control line (DIS) is
typically left open (SO-14 only) to ensure normal amplifier
operation. One optional component is included in Figure 1. In
addition to the usual power-supply decoupling capacitors to
ground, a 0.01
F capacitor is included between the two
power-supply pins. In practical PC board layouts, this op-
tional added capacitor will typically improve the 2nd-har-
monic distortion performance by 3dB to 6dB.
Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration used as the basis of the +5V Electrical
Characteristics and Typical Characteristics. Though not a
"rail-to-rail" design, the OPA2691 requires minimal input and
output voltage headroom compared to other very wideband
current-feedback op amps. It will deliver a 3Vp-p output
swing on a single +5V supply with greater than 150MHz
bandwidth. The key requirement of broadband single-supply
operation is to maintain input and output signal swings within
the usable voltage ranges at both the input and the output.
The circuit of Figure 2 establishes an input midpoint bias
using a simple resistive divider from the +5V supply (two
806
resistors). The input signal is then AC-coupled into this
midpoint voltage bias. The input voltage can swing to within
1.5V of either supply pin, giving a 2Vp-p input signal range
centered between the supply pins. The input impedance
matching resistor (57.6
) used for testing is adjusted to give
a 50
input match when the parallel combination of the
biasing divider network is included. The gain resistor (R
G
) is
AC-coupled, giving the circuit a DC gain of +1--which puts
the input DC bias voltage (2.5V) on the output as well. The
feedback resistor value has been adjusted from the bipolar
supply condition to re-optimize for a flat frequency response
in +5V operation, gain of +2, operation (see the Setting
Resistor Values to Optimize Bandwidth section). Again, on a
single +5V supply, the output voltage can swing to within 1V
of either supply pin while delivering more than 75mA output
current. A demanding 100
load to a midpoint bias is used
in this characterization circuit. The new output stage used in
the OPA2691 can deliver large bipolar output currents into
this midpoint load with minimal crossover distortion, as shown
by the +5V supply, 3rd-harmonic distortion plots.
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifica-
tion and Test Circuit.
FIGURE 2. AC-Coupled, G = +2, Single-Supply Specification
and Test Circuit.
1/2
OPA2691
+5V
+
DIS
5V
50
Load
50
50
V
O
V
I
50
Source
R
G
402
R
F
402
+
6.8
F
0.1
F
6.8
F
0.1
F
0.01
F
+V
S
V
S
1/2
OPA2691
+5V
+V
S
DIS
V
S
/2
806
100
V
O
V
I
57.6
806
R
F
453
R
G
453
0.1
F
0.1
F
6.8
F
+
0.1
F
OPA2691
12
SBOS224A
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SINGLE-SUPPLY DIFFERENTIAL ADC DRIVER
Figure 3 shows a gain of +10 Single-Ended In/Diff. Out single-
supply ADC driver. Using a dual amplifier like the OPA2691
helps reduce the necessary board space, as it also reduces the
amount of required supply bypassing components. From a
signal point of view, dual amplifiers provide excellent perfor-
mance matching (e.g., gain and phase matching). The differen-
tial ADC driver circuit shown in Figure 3 takes advantage of this
fact. A transformer converts the single-ended input signal into a
low-level differential signal which is applied to the high imped-
ance noninverting inputs of each of the two amplifiers in the
OPA2691. Resistor R
G
between the inverting inputs controls the
AC-gain of this circuit according to equation G = 1 + 2R
F
/R
G
.
With the resistor values shown, the AC-gain is set to 10. Adding
a capacitor (0.1
F) in series with R
G
blocks, the DC-path gives
a DC gain of +1 for the common-mode voltage. This allows, in
a very simple way, to apply the required DC bias voltage of
+2.5V to the inputs of the amplifiers, which will also appear at
their outputs. Like the OPA2691, the ADC ADS823 operates on
a single +5V supply. Its internal common-mode voltage is
typically +2.5V which equals the required bias voltage for the
OPA2691.
Connecting two resistors between the top reference
(REFT = +3.5V) and bottom reference (REFB = +1.5V)
develops a +2.5V voltage level at their midpoint. Applying
that to the center tap of the transformer biases the ampli-
fiers appropriately. Sufficient bypassing at the center tap
must be provided to keep this point at a solid AC ground.
Resistors R
S
isolate the op amp output from the capacitive
input of the converter, as well as forming a 1st-order, low-
pass filter with capacitor C
1
to attenuate some of the
wideband noise. This interface will provide > 150MHz full-
scale input bandwidth to the ADS823.
WIDEBAND VIDEO MULTIPLEXING
One common application for video speed amplifiers which
include a disable pin is to wire multiple amplifier outputs
together, then select which one of several possible video
inputs to source onto a single line. This simple "Wired-OR
Video Multiplexer" can be easily implemented using the
OPA2691I-14D, see Figure 4.
Typically, channel switching is performed either on sync or
retrace time in the video signal. The two inputs are approxi-
mately equal at this time. The "make-before-break" disable
characteristic of the OPA2691 ensures that there is always
one amplifier controlling the line when using a wired-OR
circuit like that presented in Figure 4. Since both inputs may
be on for a short period during the transition between
channels, the outputs are combined through the output
impedance matching resistors (82.5
in this case). When
one channel is disabled, its feedback network forms part of
the output impedance and slightly attenuates the signal in
getting out onto the cable. The gain and output matching
resistors have been slightly increased to get a signal gain of
+1 at the matched load and provide a 75
output impedance
to the cable. The video multiplexer connection (see Figure 4)
also insures that the maximum differential voltage across the
inputs of the unselected channel do not exceed the rated
1.2V maximum for standard video signal levels.
The section on Disable Operation shows the turn-on and
turn-off switching glitches using a grounded input for a single
channel is typically less than
50mV. Where two outputs are
switched (see Figure 4), the output line is always under the
control of one amplifier or the other due to the "make-before-
break" disable timing. In this case, the switching glitches for
two 0V inputs drop to < 20mV.
FIGURE 3. Wideband, Single-Supply, Differential ADC Driver.
R
F
200
R
S
24.9
50
ADS823
10-Bit
60MSPS
R
S
24.9
0.1
F
IN
IN
GND
R
F
200
R
G
44
V
BIAS
= +2.5V
REFT
(+3.5V)
REFB
(+1.5V)
C
1
10pF
C
1
10pF
1/2
OPA2691
1/2
OPA2691
2k
2k
0.1
F
0.1
F
+V
S
+5V
+5V
V
IN
1:1
0.1
F
G = 1 + = 10
2 R
F
R
G
4.7
F
+
OPA2691
13
SBOS224A
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HIGH-SPEED ACTIVE FILTERS
Wideband current-feedback op amps make ideal elements
for implementing high-speed active filters where the amplifier
is used as a fixed gain block inside a passive RC circuit
network. Their relatively constant bandwidth versus gain,
provides low interaction between the actual filter poles and
the required gain for the amplifier. Figure 5 shows an ex-
ample single-supply buffered filter application. In this case,
one of the OPA2691 channels is used to setup the DC
operating point and provide impedance isolation from the
signal source into the 2nd-stage filter. That stage is set up to
implement a 20MHz maximally flat Butterworth frequency
response and provide an AC gain of +4.
FIGURE 5. Buffered Single-Supply Active Filter.
FIGURE 4. Two-Channel Video Multiplexer.
2k
82.5
75
Cable
RG-59
82.5
75
402
340
Video 1
+5V
+5V
5V
1/2
OPA2691
1/2
OPA2691
2k
75
402
340
Video 2
5V
+5V
V
DIS
DIS
DIS
Power-supply
decoupling not shown.
600
20MHz, 2nd-Order Butterworth Low-Pass
1/2
OPA2691
+5V
Power-supply
decoupling not shown.
32.3
105
5k
5k
51
V
I
0.1
F
375
1/2
OPA2691
4V
I
100pF
125
0.1
F
150pF
12
8
4
0
4
8
12
Frequency (MHz)
20MHz, 2ND-ORDER BUTTERWORTH
LOW-PASS FREQUENCY RESPONSE
0.1
100
10
1
Gain (dB)
OPA2691
14
SBOS224A
www.ti.com
The 51
input matching resistor is optional in this case. The
input signal is AC-coupled to the 2.5V DC reference voltage
developed through the resistor divider from the +5V power
supply. This first stage acts as a gain of +1 voltage buffer for
the signal where the 600
feedback resistor is required for
stability. This first stage easily drives the low input resistors
required at the input of this high-frequency filter. The 2nd
stage is set for a DC gain of +1--carrying the 2.5V operating
point through to the output pin, and an AC gain of +4. The
feedback resistor has been adjusted to optimize bandwidth
for the amplifier itself. As the single-supply frequency re-
sponse plots show, the OPA2691 in this configuration will
give > 200MHz small-signal bandwidth. The capacitor values
were chosen as low as possible but adequate to swamp out
the parasitic input capacitance of the amplifier. The resistor
values were slightly adjusted to give the desired filter fre-
quency response while accounting for the approximate 1ns
propagation delay through each channel of the OPA2691.
HIGH-POWER TWISTED-PAIR DRIVER
A very demanding application for a high-speed amplifier is to
drive a low load impedance while maintaining a high output
voltage swing to high frequencies. Using the dual current-
feedback op amp OPA2691, a 15Vp-p output signal swing
into a twisted-pair line with a typical impedance of 100
can
be realized. Configured as shown on the front page, the two
amplifiers of the OPA2691 drive the output transformer in a
push-pull configuration thus doubling the peak-to-peak signal
swing at each op amp's output to 15Vp-p. The transformer
has a turns ratio of 2. In order to provide a matched source,
this requires a 25
source impedance (R
S
), for the primary
side, given the transformer equation n
2
= R
L
/R
S
. Dividing this
impedance equally between the outputs requires a series
termination matching resistor at each output of 12.4
. Taking
the total resistive load of 25
(for the differential output
signal) and drawing a load line on the "Output Voltage and
Current Limitations" plot it can be seen that a 1.5V headroom
is required at both the positive and negative peak currents of
150mA.
Line driver applications usually have a high demand for
transmitting the signal with low distortion. Current-feedback
amplifiers like the OPA2691 are ideal for delivering low
distortion performance to higher gains. The example shown
is set for a differential gain of 7.5. This circuit can deliver the
maximum 15Vp-p signal with over 60MHz bandwidth.
WIDEBAND (200MHz) INSTRUMENTATION AMPLIFIER
As discussed previously, the current-feedback topology of
the OPA2691 provides a nearly constant bandwidth as signal
gain is increased. The three op amp wideband instrumenta-
tion amplifiers depicted in Figure 6 takes advantage of this,
achieving a differential bandwidth of 200MHz. The signal is
applied to the high-impedance noninverting inputs of the
OPA2691. The differential gain is set by (1 + 2R
F
/R
G
)--which
is equal to 5 using the values shown in Figure 6. The
feedback resistors, R
F
, are optimized at this particular gain.
Gain adjustments can be made by adjusting R
G
. The differ-
ential to single-ended conversion is performed by the volt-
age-feedback amplifier OPA690, configured as a standard
difference amplifier. To maintain good distortion performance
for the OPA2691, the loading at each amplifier output has
been matched by setting R
3
+ R
4
= R
1
, rather than using the
same resistor values within the difference amplifier.
DEMO BOARD
ORDERING
PRODUCT
PACKAGE
NUMBER
NUMBER
OPA2691ID
SO-8
DEM-OPA268xU
SBOU003
OPA2691I-14D
SO-14
DEM-OPA268xN
SBOU002
R
F
261
R
G
130
R
3
249
R
4
249
R
1
499
R
2
499
R
F
261
1/2
OPA2691
1/2
OPA2691
+5V
V
IN
V
O
V
IN
OPA690
5V
5V
+5V
V
O
(V
IN
V
IN
)
= 5
FIGURE 6. Wideband, 3-Op Amp Instrumentation Diff. Amp.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial
evaluation of circuit performance using the OPA2691 in its
two package styles. Both of these are available, free, as an
unpopulated PC board delivered with descriptive documen-
tation. The summary information for these boards is shown
in the table below.
15
10
5
0
Frequency (MHz)
INSTRUMENTATION DIFF. AMP
FREQUENCY RESPONSE
1
400
100
10
Gain (dB)
To request any of these boards, check the Texas Instru-
ments web site at www.ti.com.
OPA2691
15
SBOS224A
www.ti.com
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. A
SPICE model for the OPA2691 is available through the TI
web site (www.ti.com). These models do a good job of
predicting small-signal AC and transient performance under
a wide variety of operating conditions. They do not do as well
in predicting the harmonic distortion or dG/dP characteristics.
These models do not attempt to distinguish between the
package types in their small-signal AC performance, nor do
they attempt to simulate channel-to-channel coupling.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO
OPTIMIZE BANDWIDTH
A current-feedback op amp like the OPA2691 can hold an
almost constant bandwidth over signal gain settings with the
proper adjustment of the external resistor values. This is
shown in the Typical Characteristics; the small-signal band-
width decreases only slightly with increasing gain. Those
curves also show that the feedback resistor has been changed
for each gain setting. The resistor "values" on the inverting
side of the circuit for a current-feedback op amp can be
treated as frequency response compensation elements while
their "ratios" set the signal gain. Figure 7 shows the small-
signal frequency response analysis circuit for the OPA2691.
R
I
, the buffer output impedance, is a critical portion of the
bandwidth control equation. The OPA2691 is typically about 37
.
A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error volt-
age for a voltage-feedback op amp) and passes this on to the
output through an internal frequency-dependent transimped-
ance gain. The Typical Characteristics show this open-loop
transimpedance response. This is analogous to the open-
loop voltage gain curve for a voltage-feedback op amp.
Developing the transfer function for the circuit of Figure 7
gives Equation 1:
V
V
R
R
R
R
R
R
Z
NG
R
R NG
Z
NG
R
R
O
I
F
G
F
I
F
G
S
F
I
S
F
G
=
+




+
+
+




=
+
+
+




1
1
1
1
1
( )
( )
(1)
This is written in a loop-gain analysis format where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z
(S)
were infinite over all frequencies, the
denominator of Equation 1 would reduce to 1 and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 1 determines the
frequency response. Equation 2 shows this as the loop-gain
equation:
Z
R
R NG
Loop Gain
S
F
I
( )
+
=
(2)
If 20 log(R
F
+ NG R
I
) were drawn on top of the open-loop
transimpedance plot, the difference between the two would
be the loop gain at a given frequency. Eventually, Z
(S)
rolls off
to equal the denominator of Equation 2 at which point the
loop gain has reduced to 1 (and the curves have intersected).
This point of equality is where the amplifier's closed-loop
frequency response given by Equation 1 will start to roll off,
and is exactly analogous to the frequency at which the noise
gain equals the open-loop voltage gain for a voltage-feed-
back op amp. The difference here is that the total impedance
in the denominator of Equation 2 may be controlled some-
what separately from the desired signal gain (or NG).
The OPA2691 is internally compensated to give a maximally
flat frequency response for R
F
= 402
at NG = 2 on
5V
supplies. Evaluating the denominator of Equation 2 (which is
the feedback transimpedance) gives an optimal target of 476
.
As the signal gain changes, the contribution of the NG R
I
term
in the feedback transimpedance will change, but the total can
be held constant by adjusting R
F
. Equation 3 gives an approxi-
mate equation for optimum R
F
over signal gain:
R
NG R
F
I
=
-
476
(3)
As the desired signal gain increases, this equation will even-
tually predict a negative R
F
. A somewhat subjective limit to this
adjustment can also be set by holding R
G
to a minimum value
of 20
. Lower values will load both the buffer stage at the input
and the output stage if R
F
gets too low--actually decreasing
The key elements of this current-feedback op amp model are:
Buffer gain from the noninverting input to the inverting input
R
I
Buffer output impedance
i
ERR
Feedback error current signal
Z(s)
Frequency dependent open-loop transimpedance
gain from i
ERR
to V
O
The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however, set
the CMRR for a single op amp differential amplifier configura-
tion. For a buffer gain
< 1.0, the CMRR = 20 log (1
)dB.
FIGURE 7. Current-Feedback Transfer Function Analysis Circuit.
R
F
V
O
R
G
R
I
Z
(S)
I
ERR
I
ERR
V
I
OPA2691
16
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the bandwidth. Figure 8 shows the recommended R
F
versus
NG for both
5V and a single +5V operation. The values for R
F
versus Gain shown here are approximately equal to the values
used to generate the Typical Characteristics. They differ in that
the optimized values used in the Typical Characteristics are
also correcting for board parasitics not considered in the
simplified analysis leading to Equation 3. The values shown in
Figure 8 give a good starting point for design where bandwidth
optimization is desired.
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted-pair, long
PC board trace, or other transmission line conductor), it is
normally necessary to add an additional matching resistor to
ground. R
G
by itself is normally not set to the required input
impedance since its value, along with the desired gain, will
determine an R
F
which may be non-optimal from a frequency
response standpoint. The total input impedance for the
source becomes the parallel combination of R
G
and R
M
.
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and will have slight effect on
the bandwidth through Equation 1. The values shown in
Figure 9 have accounted for this by slightly decreasing R
F
(from Figure 1) to re-optimize the bandwidth for the noise
gain of Figure 9 (NG = 2.74) In the example of Figure 9, the
R
M
value combines in parallel with the external 50
source
impedance, yielding an effective driving impedance of
50
|| 68
= 28.8
. This impedance is added in series with
R
G
for calculating the noise gain--which gives NG = 2.74.
This value, along with the R
F
of Figure 8 and the inverting
input impedance of 37
, are inserted into Equation 3 to get
a feedback transimpedance nearly equal to the 476
opti-
mum value.
Note that the noninverting input in this bipolar supply invert-
ing application is connected directly to ground. It is often
suggested that an additional resistor be connected to ground
on the noninverting input to achieve bias current error can-
cellation at the output. The input bias currents for a current-
feedback op amp are not generally matched in either magni-
tude or polarity. Connecting a resistor to ground on the
noninverting input of the OPA2691 in the circuit of Figure 9
will actually provide additional gain for that input's bias and
noise currents, but will not decrease the output DC error
since the input bias currents are not matched.
OUTPUT CURRENT AND VOLTAGE
The OPA2691 provides output voltage and current capabili-
ties that are unsurpassed in a low-cost, dual monolithic op
amp. Under no-load conditions at 25
C, the output voltage
typically swings closer than 1V to either supply rail; the tested
600
500
400
300
200
100
0
Noise Gain
0
20
10
15
5
Feedback Resistor (
)
+5V
5V
FIGURE 8. Recommended Feedback Resistor vs Noise Gain.
1/2
OPA2691
R
F
374
R
G
182
+5V
5V
50
50
Load
V
O
Power-supply
decoupling not shown.
V
I
50
Source
R
M
68.1
FIGURE 9. Inverting Gain of 2 with Impedance Matching.
The total impedance going into the inverting input may be
used to adjust the closed-loop signal bandwidth. Inserting a
series resistor between the inverting input and the summing
junction will increase the feedback impedance (denominator
of Equation 2), decreasing the bandwidth. The internal buffer
output impedance for the OPA2691 is slightly influenced by
the source impedance looking out of the noninverting input
terminal. High source resistors will have the effect of increas-
ing R
I
, decreasing the bandwidth. For those single-supply
applications which develop a midpoint bias at the noninverting
input through high valued resistors, the decoupling capacitor
is essential for power-supply ripple rejection, noninverting
input noise current shunting, and to minimize the high-
frequency value for R
I
in Figure 7.
INVERTING AMPLIFIER OPERATION
Since the OPA2691 is a general-purpose, wideband current-
feedback op amp, most of the familiar op amp application
circuits are available to the designer. Those dual op amp
applications that require considerable flexibility in the feed-
back element (e.g., integrators, transimpedance, and some
filters) should consider the unity-gain stable voltage-feed-
back OPA2690, since the feedback resistor is the compen-
sation element for a current-feedback op amp. Wideband
inverting operation (and especially summing) is particularly
suited to the OPA2691. Figure 9 shows a typical inverting
configuration where the I/O impedances and signal gain from
Figure 1 are retained in an inverting circuit configuration.
In the inverting configuration, two key design considerations
must be noted. The first is that the gain resistor (R
G
)
becomes part of the signal channel input impedance. If input
OPA2691
17
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swing limit is within 1.2V of either rail. Into a 15
load (the
minimum tested load), it is tested to deliver more than
160mA.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage x current, or V-I product,
which is more relevant to circuit operation. Refer to the
"Output Voltage and Current Limitations" plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA2691's output drive capabilities,
noting that the graph is bounded by a "Safe Operating Area"
of 1W maximum internal power dissipation (in this case for 1
channel only). Superimposing resistor load lines onto the plot
shows that the OPA2691 can drive
2.5V into 25
or
3.5V
into 50
without exceeding the output capabilities or the 1W
dissipation limit. A 100
load line (the standard test circuit
load) shows the full
3.9V output swing capability, as shown
in the Electrical Characteristics.
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold start-up will the output
current and voltage decrease to the numbers shown in the
electrical characteristic tables. As the output transistors de-
liver power, their junction temperatures will increase, de-
creasing their V
BE
's (increasing the available output voltage
swing) and increasing their current gains (increasing the
available output current). In steady-state operation, the avail-
able output voltage and current will always be greater than
that shown in the over-temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.
To protect the output stage from accidental shorts to ground
and the power supplies, output short-circuit protection is
included in the OPA2691. The circuit acts to limit the maxi-
mum source or sink current to approximately 250mA.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC--including additional
external capacitance which may be recommended to im-
prove the ADC's linearity. A high-speed, high open-loop gain
amplifier like the OPA2691 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier's open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.
The Typical Characteristics show the recommended "R
S
vs
Capacitive Load" and the resulting frequency response at the
load. Parasitic capacitive loads greater than 2pF can begin to
degrade the performance of the OPA2691. Long PC board
traces, unmatched cables, and connections to multiple de-
vices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA2691 output
pin (see Board Layout Guidelines).
DISTORTION PERFORMANCE
The OPA2691 provides good distortion performance into a
100
load on
5V supplies. Relative to alternative solutions,
it provides exceptional performance into lighter loads and/or
operating on a single +5V supply. Generally, until the funda-
mental signal reaches very high frequency or power levels,
the 2nd-harmonic will dominate the distortion with a negligible
3rd-harmonic component. Focusing then on the 2nd-har-
monic, increasing the load impedance improves distortion
directly. Remember that the total load includes the feedback
network--in the noninverting configuration (see Figure 1) this
is the sum of R
F
+ R
G
, while in the inverting configuration it is
just R
F
. Also, providing an additional supply decoupling ca-
pacitor (0.01
F) between the supply pins (for bipolar opera-
tion) improves the 2nd-order distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. The Typical Character-
istics show the 2nd-harmonic increasing at a little less than
the expected 2x rate while the 3rd-harmonic increases at a
little less than the expected 3x rate. Where the test power
doubles, the difference between it and the 2nd-harmonic
decreases less than the expected 6dB while the difference
between it and the 3rd-harmonic decreases by less than the
expected 12dB. This also shows up in the 2-tone, 3rd-order
intermodulation spurious (IM3) response curves. The 3rd-
order spurious levels are extremely low at low output power
levels. The output stage continues to hold them low even as
the fundamental power reaches very high levels. As the
Typical Characteristics show, the spurious intermodulation
powers do not increase as predicted by a traditional intercept
model. As the fundamental power level increases, the dy-
namic range does not decrease significantly. For two tones
centered at 20MHz, with 10dBm/tone into a matched 50
load (i.e., 2Vp-p for each tone at the load, which requires
8Vp-p for the overall 2-tone envelope at the output pin), the
Typical Characteristics show 48dBc difference between the
test-tone power and the 3rd-order intermodulation spurious
levels. This exceptional performance improves further when
operating at lower frequencies.
NOISE PERFORMANCE
Wideband current-feedback op amps generally have a higher
output noise than comparable voltage-feedback op amps. The
OPA2691 offers an excellent balance between voltage and
OPA2691
18
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current noise terms to achieve low output noise. The inverting
current noise (15pA/
Hz) is significantly lower than earlier
solutions while the input voltage noise (1.7nV/
Hz) is lower
than most unity-gain stable, wideband, voltage-feedback op
amps. This low input voltage noise was achieved at the price
of higher noninverting input current noise (12pA/
Hz). As long
as the AC source impedance looking out of the noninverting
node is less than 100
, this current noise will not contribute
significantly to the total output noise. The op amp input voltage
noise and the two input current noise terms combine to give
low output noise under a wide variety of operating conditions.
Figure 10 shows the op amp noise analysis model with all the
noise terms included. In this model, all noise terms are taken
to be noise voltage or current density terms in either nV/
Hz
or pA/
Hz.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA2691 provides
exceptional bandwidth in high gains, giving fast pulse settling
but only moderate DC accuracy. The Electrical Characteris-
tics show an input offset voltage comparable to high-speed
voltage-feedback amplifiers. However, the two input bias
currents are somewhat higher and are unmatched. Whereas
bias current cancellation techniques are very effective with
most voltage-feedback op amps, they do not generally re-
duce the output DC offset for wideband current-feedback op
amps. Since the two input bias currents are unrelated in both
magnitude and polarity, matching the source impedance
looking out of each input to reduce their error contribution to
the output is ineffective. Evaluating the configuration of
Figure 1, using worst-case +25
C input offset voltage and the
two input bias currents, gives a worst-case output offset
range equal to:
(NG V
OS(MAX)
) + (I
BN
R
S
/2 NG)
(I
BI
R
F
)
where NG = noninverting signal gain
=
(2 3.0mV) + (35
A 25
2)
(402
25
A)
=
6mV + 1.75mV
10.05mV
= 14.3mV
+17.8mV
DISABLE OPERATION (SO-14 ONLY)
The OPA2691I-14D provides an optional disable feature that
may be used either to reduce system power or to implement
a simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA2691I-14D will operate
normally. To disable, the control pin must be asserted low.
Figure 11 shows a simplified internal circuit for the disable
control feature.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 4 shows the general form for the
output noise voltage using the terms shown in Figure 10.
(4)
E
E
I
R
kTR NG
I R
kTR NG
O
NI
BN
S
S
BI
F
F
=
+
(
)
+
(
)
+
(
)
+
2
2
2
2
4
4
Dividing this expression by the noise gain (NG = (1 + R
F
/R
G
))
will give the equivalent input referred spot noise voltage at
the noninverting input, as shown in Equation 5.
E
E
I
R
kTR
I R
NG
kTR
NG
N
NI
BN
S
S
BI
F
F
=
+
(
)
+
+


+
2
2
2
4
4
(5)
Evaluating these two equations for the OPA2691 circuit and
component values presented in Figure 1 will give a total
output spot noise voltage of 8.08nV/
Hz and a total equiva-
lent input spot noise voltage of 4.04nV/
Hz. This total input
referred spot noise voltage is higher than the 1.7nV/
Hz
specification for the op amp voltage noise alone. This reflects
the noise added to the output by the inverting current noise
times the feedback resistor. If the feedback resistor is re-
duced in high-gain configurations (as suggested previously),
the total input referred voltage noise given by Equation 5 will
approach just the 1.7nV/
Hz of the op amp itself. For
example, going to a gain of +10 using R
F
= 180
will give a
total input referred noise of 2.1nV/
Hz.
In normal operation, base current to Q1 is provided through
the 110k
resistor while the emitter current through the 15k
resistor sets up a voltage drop that is inadequate to turn on
the two diodes in Q1's emitter. As V
DIS
is pulled low, addi-
tional current is pulled through the 15k
resistor, eventually
turning on these two diodes (
100
A). At this point, any
further current pulled out of V
DIS
goes through those diodes
FIGURE 10. Op Amp Noise Analysis Model.
4kT
R
G
R
G
R
F
R
S
1/2
OPA2691
I
BI
E
O
I
BN
4kT = 1.6E 20J
at 290
K
E
RS
E
NI
4kTR
S
4kTR
F
25k
110k
15k
I
S
Control
V
S
+V
S
V
DIS
Q1
FIGURE 11. Simplified Disable Control Circuit, Each Channel.
OPA2691
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THERMAL ANALYSIS
Due to the high output power capability of the OPA2691,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175
C. Operating junction
temperature (T
J
) is given by T
A
+ P
D
JA
. The total internal
power dissipation (P
D
) is the sum of quiescent power (P
DQ
)
and additional power dissipation in the output stage (P
DL
) to
deliver load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage across
the part. P
DL
will depend on the required output signal and
load but would, for a grounded resistive load, be at a
maximum when the output is fixed at a voltage equal to 1/2
of either supply voltage (for equal bipolar supplies). Under
this condition, P
DL
= V
S
2
/(4 R
L
) where R
L
includes feedback
network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA2691 SO-8 in the circuit of Figure 1 operating at the
maximum specified ambient temperature of +85
C with both
outputs driving a grounded 20
load to +2.5V.
P
D
= 10V 11.5mA + 2 [5
2
/(4 (20
|| 804
))] = 756mW
Maximum T
J
= +85
C + (0.756 125
C/W) = 179.5
C
This absolute worst-case condition exceeds specified maxi-
mum junction temperature. Normally this extreme case will
not be encountered. Careful attention to internal power
dissipation is required.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency ampli-
fier like the OPA2691 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Other-
wise, ground and power planes should be unbroken else-
where on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1
F decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 4 and 7) should always be decoupled
with these capacitors. An optional supply decoupling capaci-
tor across the two power supplies (for bipolar operation) will
improve 2nd-harmonic distortion performance. Larger (2.2
F
to 6.8
F) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA2691.
Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film and carbon composition axially-
leaded resistors can also provide good high-frequency per-
formance. Again, keep their leads and PC board trace length
holding the emitter-base voltage of Q1 at approximately 0V.
This shuts off the collector current out of Q1, turning the
amplifier off. The supply currents in the disable mode are only
those required to operate the circuit of Figure 11. Additional
circuitry ensures that turn-on time occurs faster than turn-off
time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA2691 is operating in a gain of +1,
this will show a very high impedance (4pF || 1M
) at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(R
F
+ R
G
) will appear as the impedance looking back into the
output, but the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
input and output will be connected through the feedback
network resistance (R
F
+ R
G
) giving relatively poor input to
output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 12
shows these glitches for the circuit of Figure 1 with the input
signal set to 0V. The glitch waveform at the output pin is
plotted along with the DIS pin voltage.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 12, the edge rate
was reduced until no further reduction in glitch amplitude was
observed. This approximately 1V/ns maximum slew rate may
be achieved by adding a simple RC filter into the V
DIS
pin
from a higher speed logic line. If extremely fast transition
logic is used, a 2k
series resistor between the logic gate
and the V
DIS
input pin will provide adequate bandlimiting
using just the parasitic input capacitance on the V
DIS
pin
while still ensuring adequate logic level swing.
FIGURE 12. Disable/Enable Glitch.
30
20
10
0
10
20
30
Time (20ns/div)
Output Voltage (10mV/div)
6.0
4.0
2.0
0.0
V
DIS
(2V/div)
OPA2691
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as short as possible. Never use wirewound type resistors in
a high-frequency application. Since the output pin and invert-
ing input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as noninverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. The
frequency response is primarily determined by the feedback
resistor value as described previously. Increasing its value
will reduce the bandwidth, while decreasing it will give a more
peaked frequency response. The 402
feedback resistor
used in the electrical characteristics at a gain of +2 on
5V
supplies is a good starting point for design. Note that a 453
feedback resistor, rather than a direct short, is recommended
for the unity-gain follower application. A current-feedback op
amp requires a feedback resistor even in the unity-gain
follower configuration to control stability.
d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
S
from the
plot of "Recommended R
S
vs Capacitive Load". Low parasitic
capacitive loads (< 5pF) may not need an R
S
since the
OPA2691 is nominally compensated to operate with a 2pF
parasitic load. If a long trace is required, and the 6dB signal
loss intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance transmission
line using microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline layout tech-
niques). A 50
environment is normally not necessary on
board, and in fact a higher impedance environment will
improve distortion as shown in the "Distortion vs Load" plots.
With a characteristic board trace impedance defined based
on board material and trace dimensions, a matching series
resistor into the trace from the output of the OPA2691 is used
as well as a terminating shunt resistor at the input of the
destination device. Remember also that the terminating im-
pedance will be the parallel combination of the shunt resistor
and the input impedance of the destination device: this total
effective impedance should be set to match the trace imped-
ance. The high output voltage and current capability of the
OPA2691 allows multiple destination devices to be handled
as separate transmission lines, each with their own series
and shunt terminations. If the 6dB attenuation of a doubly-
terminated transmission line is unacceptable, a long trace
can be series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the series
resistor value as shown in the plot of "R
S
vs Capacitive
Load". This will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the destina-
tion device is low, there will be some signal attenuation due
to the voltage divider formed by the series output into the
terminating impedance.
e) Socketing a high-speed part like the OPA2691 is not
recommended.
The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA2691
onto the board.
INPUT AND ESD PROTECTION
The OPA2691 is built using a very high-speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry de-
vices. These breakdowns are reflected in the Absolute Maxi-
mum Ratings table. All device pins have limited ESD protec-
tion using internal diodes to the power supplies, as shown in
Figure 13.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with
15V supply parts
driving into the OPA2691), current-limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
FIGURE 12. Internal ESD Protection.
External
Pin
+V
CC
V
CC
Internal
Circuitry
OPA2691
21
SBOS224A
www.ti.com
PACKAGE DRAWING
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
OPA2691I-14D
ACTIVE
SOIC
D
14
58
OPA2691I-14DR
ACTIVE
SOIC
D
14
2500
OPA2691ID
ACTIVE
SOIC
D
8
100
OPA2691IDR
ACTIVE
SOIC
D
8
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
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