Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS(
- PACKAGE/ORDERING INFORMATION
- ELECTRICAL CHARACTERISTICS: VS = 5V
- TYPICAL CHARACTERISTICS: VS = 5V
- TYPICAL CHARACTERISTICS: VS = 5V, DIFFERENTIAL CONFIGURATION
- APPLICATIONS INFORMATION
- WIDEBAND, NONINVERTING OPERATION
- WIDEBAND, INVERTING GAIN OPERATION
- LOW-NOISE VDSL RECEIVER
- SINGLE-STAGE TRANSIMPEDANCE DESIGN
- TWO-STAGE TRANSIMPEDANCE DESIGN
- LOW-GAIN COMPENSATION FOR IMPROVED SFDR
- DC-COUPLED, SINGLE-TO-DIFFERENTIAL ADC DRIVER
- AC-COUPLED, SINGLE-TO-DIFFERENTIAL ADC DRIVER
- DESIGN-IN TOOLS
- DEMONSTRATION BOARDS
- MACROMODELS AND APPLICATIONS SUPPORT
- OPERATING SUGGESTIONS
- SETTING RESISTOR VALUES TO MINIMIZE NOISE
- FREQUENCY RESPONSE CONTROL
- DRIVING CAPACITIVE LOADS
- DISTORTION PERFORMANCE
- DC ACCURACY AND OFFSET CONTROL
- THERMAL ANALYSIS
- BOARD LAYOUT
- INPUT AND ESD PROTECTION
FEATURES
D
HIGH BANDWIDTH: 300MHz (G = +10)
D
LOW INPUT VOLTAGE NOISE: 1.2nV/
Hz
D
VERY LOW DISTORTION: 100dBc (5MHz)
D
HIGH SLEW RATE: 600V/
s
D
HIGH DC ACCURACY: V
IO
= 150
V
D
LOW SUPPLY CURRENT: 12.6mA/ch
D
HIGH GAIN BANDWIDTH PRODUCT: 1650MHz
D
STABLE FOR GAINS
+7V/V
APPLICATIONS
D
HIGH DYNAMIC RANGE ADC PREAMPS
D
LOW-NOISE, WIDEBAND, TRANSIMPEDANCE
AMPLIFIERS
D
WIDEBAND, HIGH GAIN AMPLIFIERS
D
LOW-NOISE DIFFERENTIAL RECEIVERS
D
VDSL LINE RECEIVERS
D
ULTRASOUND CHANNEL AMPLIFIERS
D
SECURITY SENSOR FRONT ENDS
DESCRIPTION
The OPA2846 provides two very low-noise, high gain
bandwidth, voltage-feedback op amps in a single
package. Operating from a low 12.6mA/channel quiescent
current, each channel provides a 1.2nV/
Hz input voltage
noise with a 1.65GHz gain bandwidth product. Minimum
stable gain is specified at +7V/V while exceptional flatness
is ensured at a gain of +10V/V.
The combination of low noise, high slew rate (600V/
s)
and broad bandwidth allow very high SFDR differential
receivers to be implemented. Additionally, decompen-
sated, low-noise, voltage-feedback op amps are ideal for
broadband transimpedance requirements. The dual chan-
nel OPA2846 provides matched channels for high-speed
transimpedance requirements. With over 200MHz band-
width at a gain of 20dB, excellent gain and phase matching
are provided at IF frequencies for matched I and Q channel
amplifiers.
OPA2846 RELATED PRODUCTS
SINGLES
INPUT NOISE
VOLTAGE (nV/
Hz)
GAIN BANDWIDTH
PRODUCT (MHz)
OPA842
2.6
200
OPA843
2.0
800
OPA846
1.2
1750
OPA847
0.85
3900
Differential, 14-Bit, ADC Driver
Single-to-Differential
Gain of 10
Power-supply decoup ling
not sho wn.
1/2
O P A 28 46
L
+5V
L
R
1
R
1
R
2
R
2
C
V
-
V+
14-Bit
10MSPS
ADS850
2.1pF
1 /2
O P A2 84 6
500
-
5V
18pF
1000pF
1000pF
18p F
0.1
F
100
100
100
500
2.1pF
C
1
C
1
V
I
50
1:2
100
V
CM
-
80
-
85
-
90
-
95
-
100
-
105
-
110
Frequency (MHz)
1
10
H
a
r
m
on
i
c
D
i
s
t
or
ti
o
n
(
d
B
c
)
V
O
= 2V
PP
Differential
3rd-Harmonic
2nd-Harmonic
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
Dual, Wideband, Low-Noise, Voltage-Feedback
Operational Amplifier
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
www.ti.com
Copyright
2003-2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
2
ABSOLUTE MAXIMUM RATINGS
(1)
Power Supply
6.5VDC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Power Dissipation
See Thermal Analysis
. . . . . . . . . . . . . .
Differential Input Voltage
1.2V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage Range
VS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range: D
-40
C to +125
C
. . . . . . . . . . . . . . . .
Lead Temperature (soldering, 10s)
+300
C
. . . . . . . . . . . . . . . . . . . . .
Junction Temperature (TJ)
+150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Rating (Human Body Model)
2000V
. . . . . . . . . . . . . . . . . . . .
(Charge Device Model)
1500V
. . . . . . . . . . . . . . . . . . .
(Machine Model)
200V
. . . . . . . . . . . . . . . . . . . . . . . . . .
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA2846
SO-8
D
-40
C to +85
C
OPA2846
OPA2846ID
OPA2846IDR
Rails, 100
Tape and Reel, 2500
(1) For the most current specification and package information, refer to our web site at www.ti.com.
Top View
SO
1
2
3
4
8
7
6
5
V+
Out B
-
In B
+In B
Out A
-
In A
+In A
V
-
OPA2846
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
3
ELECTRICAL CHARACTERISTICS: V
S
=
5V
Boldface limits are 100% tested at +25
C.
R
F
= 453
, R
L
= 100
, and G = +10, unless otherwise noted. See Figure 1 for AC performance.
OPA2846ID
TYP
MIN/MAX OVER TEMPERATURE
TEST
PARAMETER
TEST CONDITIONS
+25
C
+25
C(1)
0
C to
+70
C(2)
-40
C to
+85
C(2)
UNITS
MIN/
MAX
TEST
LEVEL
(3)
AC Performance (see Figure 1)
Closed-Loop Bandwidth
G = +7, RG = 50
, VO = 200mVPP
425
MHz
typ
C
G = +10, RG = 50
, VO = 200mVPP
300
250
225
200
MHz
min
B
G = +20, RG = 50
, VO = 200mVPP
100
80
76
70
MHz
min
B
Gain Bandwidth Product
G
+40
1650
1250
1225
1200
MHz
min
B
Bandwidth for 0.1dB Gain Flatness
G = +10, RL = 100
, VO = 200mVPP
100
40
35
30
MHz
min
B
Peaking at a Gain of +7
3
dB
typ
C
Harmonic Distortion
G = +10, f = 5MHz, VO = 2VPP
2nd-Harmonic
RL = 100
-76
-70
-68
-66
dBc
max
B
RL = 500
-100
-89
-87
-85
dBc
max
B
3rd-Harmonic
RL = 100
-109
-95
-92
-90
dBc
max
B
RL = 500
-112
-105
-101
-96
dBc
max
B
2-Tone, 3rd-Order Intercept
G = +10, f = 10MHz
44
41
40
38
dBm
min
B
Input Voltage Noise
f > 1MHz
1.2
1.3
1.4
1.5
nV/
Hz
max
B
Input Current Noise
f > 1MHz
2.8
3.5
3.6
3.6
pA/
Hz
max
B
Rise-and-Fall Time
0.2V Step
1.3
1.6
1.7
1.9
ns
max
B
Slew Rate
2V Step
600
500
400
350
V/
s
min
B
Settling Time to 0.01%
2V Step
18
ns
typ
C
0.1%
2V Step
12
14
16
18
ns
max
B
1%
2V Step
8
10
12
14
ns
max
B
Differential Gain
G = +10, NTSC, RL = 150
0.02
%
typ
C
Differential Phase
G = +10, NTSC, RL = 150
0.02
deg
typ
C
Channel-to-Channel Crosstalk
Input Referrred, f = 5MHz
-60
dBc
typ
C
DC Performance(4)
Open-Loop Voltage Gain (AOL)
VO = 0V
90
82
81
80
dB
min
A
Input Offset Voltage
VCM = 0V
0.15
0.65
0.73
0.76
mV
max
A
Average Offset Voltage Drift
VCM = 0V
0.5
1.6
1.6
1.6
V/
C
max
B
Input Bias Current
VCM = 0V
-10
-20
-20.8
-21.2
max
A
Input Bias Current Drift
VCM = 0V
1
20
20
35
nA/
C
max
B
Input Offset Current
VCM = 0V
0.1
0.4
0.5
0.6
max
A
Input Offset Current Drift
VCM = 0V
0.7
3.0
3.0
3.5
nA/
C
max
B
Input
Common-Mode Input Range (CMIR)(5)
3.2
3.0
2.9
2.8
V
min
A
Common-Mode Rejection Ratio (CMRR)
VCM =
1V, Input Referred
110
95
93
90
dB
min
A
Input Impedance
Differential-Mode
VCM = 0V
6.6
2.0
k
pF
typ
C
Common-Mode
VCM = 0V
4.7
1.8
M
pF
typ
C
Output
Output Voltage Swing
400
Load
3.4
3.3
3.2
3.1
V
min
A
100
Load
3.3
3.2
3.0
2.9
V
min
A
Current Output, Sourcing
VO = 0V
80
65
61
60
mA
min
A
Current Output, Sinking
VO = 0V
-80
-65
-61
-60
mA
min
A
Closed-Loop Output Impedance
G = +10, f = 100kHz
0.008
typ
C
(1) Junction temperature = ambient for +25
C specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23
C at high temperature limit for over temperature
specifications.
(3) Test levels: (A) 100% tested at +25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(4) Current is considered positive out of node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum CMRR specification at
CMIR limits.
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
4
ELECTRICAL CHARACTERISTICS: V
S
=
5V (continued)
Boldface limits are 100% tested at +25
C.
R
F
= 453
, R
L
= 100
, and G = +10, unless otherwise noted. See Figure 1 for AC performance.
OPA2846ID
TEST
LEVEL
(3)
MIN/MAX OVER TEMPERATURE
TYP
PARAMETER
TEST
LEVEL
(3)
MIN/
MAX
UNITS
-40
C to
+85
C(2)
0
C to
+70
C(2)
+25
C(1)
+25
C
TEST CONDITIONS
Power Supply
Specified Operating Voltage
5
V
typ
C
Maximum Operating Voltage
6
6
6
V
max
A
Maximum Quiescent Current
VS =
5V, Both Channels
25.2
25.9
26.3
26.7
mA
max
A
Minimum Quiescent Current
VS =
5V, Both Channels
25.2
24.5
23.9
23.3
mA
min
A
Power-Supply Rejection Ratio (-PSRR)
-VS = -4.5 to 5.5 (Input Referred)
95
90
88
85
dB
min
A
Thermal Characteristics
Specified Operating Range: D Package
-40 to
+85
C
typ
C
Thermal Resistance,
q
JA
Junction-to-Ambient
D
SO-8
125
C/W
typ
C
(1) Junction temperature = ambient for +25
C specifications.
(2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23
C at high temperature limit for over temperature
specifications.
(3) Test levels: (A) 100% tested at +25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(4) Current is considered positive out of node. VCM is the input common-mode voltage.
(5) Tested < 3dB below minimum CMRR specification at
CMIR limits.
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
5
TYPICAL CHARACTERISTICS: V
S
=
5V
TA = 25
C, G = +10, RF = 453
, RG = 50
, and RL = 100
,
unless otherwise noted.
6
3
0
-
3
-
6
-
9
-
12
-
15
-
18
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE
Frequency (Hz)
N
o
r
m
a
l
iz
e
d
G
a
in
(
d
B
)
1M
10M
100M
1G
V
O
= 0.2V
PP
R
G
= 50
See Figure 1
G = 50
G = 20
G = 10
G = 7
23
20
17
14
11
8
5
2
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (Hz)
Ga
i
n
(d
B
)
10M
100M
1G
R
L
= 100
G = +10V/V
See Figure 1
V
O
= 2V
PP
V
O
= 5V
PP
V
O
= 0.2V
PP
V
O
= 1V
PP
2.0
1.6
1.2
0.8
0.4
0
-
0.4
-
0.8
-
1.2
-
1.6
-
2.0
NONINVERTING PULSE RESPONSE
Time (5ns/div)
O
u
t
put
V
o
l
t
age
(
4
0
0
mV
/
d
i
v
)
0.5
0.4
0.3
0.2
0.1
0
-
0.1
-
0.2
-
0.3
-
0.4
-
0.5
O
u
t
put
V
o
l
t
age
(
1
0
0
mV
/
d
i
v
)
G = +10V/V
See Figure 1
Large Signal
1V
Left Scale
Small Signal
100mV
Right Scale
3
0
-
3
-
6
-
9
-
12
-
15
-
18
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
Frequency (Hz)
N
o
r
m
a
l
iz
e
d
G
a
in
(
d
B
)
1M
10M
100M
1G
V
O
= 0.2V
PP
R
G
= R
S
= 50
See Figure 2
G =
-
50
G =
-
20
G =
-
12
29
26
23
20
17
14
11
8
5
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (Hz)
Ga
i
n
(d
B
)
10M
100M
1G
R
L
= 100
R
G
= R
S
= 50
G =
-
20V/V
See Figure 2
V
O
= 2V
PP
V
O
= 5V
PP
V
O
= 1V
PP
V
O
= 0.2V
PP
2.0
1.6
1.2
0.8
0.4
0
-
0.4
-
0.8
-
1.2
-
1.6
-
2.0
INVERTING PULSE RESPONSE
Time (5ns/div)
O
u
t
put
V
o
l
t
age
(
4
0
0
mV
/
d
i
v
)
0.5
0.4
0.3
0.2
0.1
0
-
0.1
-
0.2
-
0.3
-
0.4
-
0.5
O
u
t
put
V
o
l
t
age
(
1
0
0
mV
/
d
i
v
)
G =
-
20V/V
Large Signal
1V
Left Scale
Small Signal
100mV
Right Scale
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
6
TYPICAL CHARACTERISTICS: V
S
=
5V (continued)
TA = 25
C, G = +10, RF = 453
, RG = 50
, and RL = 100
,
unless otherwise noted.
-
60
-
65
-
70
-
75
-
80
-
85
-
90
-
95
-
100
-
105
-
110
-
115
5MHz HARMONIC DISTORTION vs LOAD RESISTANCE
Resistance (
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c
)
100
150
200
250
300
350
400
450
500
G = +10V/V
V
O
= 2V
PP
See Figure 1
3rd-Harmonic
2nd-Harmonic
-
55
-
65
-
75
-
85
-
95
-
105
-
115
HARMONIC DISTORTION vs FREQUENCY
Frequency (MHz)
N
o
r
m
a
l
iz
e
d
G
a
in
(
d
B)
0.1
1
10
100
G = +10V/V
V
O
= 2V
PP
R
L
= 200
See Figure 1
2nd-Harmonic
3rd-Harmonic
-
60
-
65
-
70
-
75
-
80
-
85
-
90
-
95
-
100
-
105
-
110
-
115
HARMONIC DISTORTION vs NONINVERTING GAIN
Gain (V/V)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c
)
5
10
15
20
25
30
35
40
45
50
See Figure 1
2nd-Harmonic
3rd-Harmonic
V
O
= 2V
PP
f = 5MHz
R
L
= 200
-
65
-
70
-
75
-
80
-
85
-
90
-
95
-
100
-
105
-
110
1MHz HARMONIC DISTORTION vs LOAD RESISTANCE
Resistance (
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c
)
100
150
200
250
300
350
400
450
500
G = +10V/V
V
O
= 5V
PP
2nd-Harmonic
3rd-Harmonic
-
65
-
70
-
75
-
80
-
85
-
90
-
95
-
100
-
105
-
110
-
115
HARMONIC DISTORTION vs OUTPUT VOLTAGE
Output Voltage (V
PP
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
0.1
1
10
G = +10V/V
f = 5MHz
R
L
= 200
See Figure 1
2nd-Harmonic
3rd-Harmonic
-
65
-
75
-
85
-
95
-
105
-
115
HARMONIC DISTORTION vs INVERTING GAIN
Gain (
-
V/V)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c
)
10
15
20
25
30
35
40
45
50
V
O
= 2V
PP
f = 5MHz
R
L
= 200
2nd-Harmonic
3rd-Harmonic
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
7
TYPICAL CHARACTERISTICS: V
S
=
5V (continued)
TA = 25
C, G = +10, RF = 453
, RG = 50
, and RL = 100
,
unless otherwise noted.
10
1
INPUT VOLTAGE AND CURRENT NOISE
Frequency (Hz)
Vo
lt
a
g
e
N
o
i
s
e
(
n
V/
Hz
)
Cu
r
r
e
n
t
V
o
i
s
e
(
p
A
/
Hz
)
10
100
1k
10k
100k
1M
10M
100M
Current Noise
2.8pA/
Hz
Voltage Noise
1.2nV/
Hz
0.5
0.4
0.3
0.2
0.1
0
-
0.1
-
0.2
-
0.3
-
0.4
-
0.5
NONINVERTING GAIN FLATNESS TUNE
Frequency (Hz)
D
e
v
i
a
t
i
o
n
f
r
o
m
1
8.06d
B
G
ai
n
(
0.1dB
)
1M
10M
100M
1G
NG = 8.0
NG = 8.5
NG = 10.0
NG = 9.5
NG = 9.0
V
O
= 200mV
PP
A
V
= +8
R
F
= 453
R
G
= 64.9
External Compensation
See Figure 9
100
10
1
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
R
S
(
)
1
10
100
1000
G = +10V/V
50
45
40
35
30
25
20
2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT
Frequency (MHz)
I
n
t
e
r
c
e
p
t
Po
in
t
(
+
d
Bm
)
5
10
15
20
25
30
35
40
45
50
G = +10V/V
R
F
45 3
R
S
5 0
1 /2
O P A 2 8 46
P
IN
P
O
50
R
L
5 0
R
G
5 0
+5V
50
S o u rce
-
5V
3
2
1
0
-
1
-
2
-
3
-
4
-
5
-
6
LOW GAIN INVERTING BANDWIDTH
Frequency (Hz)
N
o
rm
a
l
i
z
e
d
G
a
i
n
(1
d
B
)
1M
10M
100M
1G
G =
-
6
G =
-
4
G =
-
2
G =
-
1
V
O
= 200mV
PP
R
F
= 400
External Compensation
See Figure 5
23
20
17
14
11
8
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (Hz)
N
o
r
m
a
l
i
z
ed
G
a
i
n
to
C
apa
c
i
ti
v
e
Loa
d
(
d
B
)
1M
10M
100M
1G
C = 22pF
C = 47pF
C = 100pF
C = 10pF
R
S
adjusted for capacitive load.
R
45 3
R
S
1/ 2
O P A 2 846
V
IN
V
O
50
R
L
1k
P ow er- su pp ly
de c ou plin g no t sh ow n.
C
L
R
G
50
+5 V
50
So urce
-
5 V
(1 k
is op tion al.)
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
8
TYPICAL CHARACTERISTICS: V
S
=
5V (continued)
TA = 25
C, G = +10, RF = 453
, RG = 50
, and RL = 100
,
unless otherwise noted.
120
110
100
90
80
70
60
50
40
30
20
COMMON-MODE REJECTION RATIO AND
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
Frequency (Hz)
CM
RR
a
n
d
P
S
RR
(
d
B
)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
CMRR
+PSRR
-
PSRR
4
3
2
1
0
-
1
-
2
-
3
-
4
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
I
O
(mA)
V
O
(V
)
-
150
-
100
-
50
0
50
100
150
R
L
= 100
R
L
= 25
R
L
= 50
10
8
6
4
2
0
-
2
-
4
-
6
-
8
-
10
1.0
0.8
0.6
0.4
0.2
0
-
0.2
-
0.4
-
0.6
-
0.8
-
1.0
NONINVERTING OVERDRIVE RECOVERY
Time (50ns/div)
O
u
t
p
ut
V
o
l
t
ag
e
(
2V
/
d
i
v
)
I
n
p
u
t
V
ol
t
a
ge
(
200m
V
/
di
v
)
See Figure 1
G = +10V/V
R
L
= 100
Output
Input
0
50
100 150 200 250 300 350 400 450 500
120
100
80
60
40
20
0
-
20
0
-
30
-
60
-
90
-
120
-
150
-
180
-
210
OPEN-LOOP GAIN AND PHASE
Frequency (Hz)
O
p
e
n
-
Loo
p
G
ai
n
(
d
B
)
O
p
e
n
-
L
oop
P
has
e
(
_
)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
10
9
20log (A
OL
)
A
OL
10
1
0.1
0.01
0.001
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Frequency (Hz)
O
u
tp
ut
Imp
eda
n
c
e
(
)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
453
1/2
O PA 2846
Z
O
50
10
8
6
4
2
0
-
2
-
4
-
6
-
8
-
10
0.5
0.4
0.3
0.2
0.1
0
-
0.1
-
0.2
-
0.3
-
0.4
-
0.5
INVERTING OVERDRIVE RECOVERY
Time (50ns/div)
O
u
t
put
V
o
l
t
age
(
2
V
/
di
v
)
I
npu
t
V
o
l
tag
e
(
1
00
mV
/d
i
v
)
See Figure 2
G =
-
20V/V
R
L
= 100
Output
Input
0
50
100 150 200 250 300 350 400 450 500
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
9
TYPICAL CHARACTERISTICS: V
S
=
5V (continued)
TA = 25
C, G = +10, RF = 453
, RG = 50
, and RL = 100
,
unless otherwise noted.
0.25
0.20
0.15
0.10
0.05
0
-
0.05
-
0.10
-
0.15
-
0.20
-
0.25
SETTLING TIME
Time (ns)
P
e
r
c
en
t
o
f
F
i
nal
V
a
l
u
e
(
%
)
0
5
10
15
20
25
G = +10V/V
R
L
= 100
V
O
= 2V Step
See Figure 1
0.25
0.20
0.15
0.10
0.05
0
-
0.05
-
0.10
-
0.15
-
0.20
-
0.25
25
20
15
10
5
0
-
5
-
10
-
15
-
20
-
25
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (
_
C)
I
npu
t
O
ff
s
e
t
V
ol
t
age
(
m
V
)
Inp
u
t
B
i
a
s
a
n
d
O
f
fs
et
C
u
r
r
ent
(
A)
-
50
-
25
0
25
50
75
100
125
100 x I
OS
V
IO
I
b
6
4
2
0
-
2
-
4
-
6
COMMON-MODE INPUT RANGE AND OUTPUT SWING
vs SUPPLY VOLTAGE
Supply Voltage (
V)
V
o
l
t
ag
e
R
ang
e
(
V
)
2.5
3.5
3.0
4.5
4.0
5.5
5.0
6.0
+V
IN
-
V
IN
+V
OUT
-
V
OUT
83
80
77
74
71
68
65
62
PHOTODIODE TRANSIMPEDANCE
FREQUENCY RESPONSE
Frequency (MHz)
T
r
a
n
s
i
m
peda
nc
e
G
ai
n
(
dB
)
1
10
100
C
D
= 100pF
R
F
= 10k
C
F
Adjusted
C
D
= 50pF
C
D
= 20pF
C
D
= 10pF
See Figure 4
20 log(10k
)
150
140
130
120
110
100
90
80
70
20
18
16
14
12
10
8
6
4
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (
_
C)
O
u
tpu
t
C
u
r
r
e
n
t
(
10m
A
/
di
v
)
S
u
p
p
l
y
C
u
rre
n
t
(2
m
A
/
d
i
v
)
-
50
-
25
0
25
50
75
100
125
Sourcing Output Current
Supply Current
Sinking Output Current
10
7
10
6
10
5
10
4
10
3
10
2
COMMON-MODE AND DIFFERENTIAL
INPUT IMPEDANCE
Frequency (Hz)
I
n
pu
t
I
m
p
e
d
an
c
e
(
)
10
2
10
4
10
5
10
3
10
6
10
7
10
8
Common-Mode
Differential
4.7M
6.6k
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
10
TYPICAL CHARACTERISTICS: V
S
=
5V (continued)
TA = 25
C, G = +10, RF = 453
, RG = 50
, and RL = 100
,
unless otherwise noted.
-
30
-
35
-
40
-
45
-
50
-
55
-
60
-
65
-
70
-
75
-
80
CHANNEL-TO-CHANNEL CROSSTALK
Frequency (MHz)
C
r
os
s
t
a
l
k
(
5d
B
/
di
v
)
1
10
100
Input-Referred
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
11
TYPICAL CHARACTERISTICS: V
S
=
5V, DIFFERENTIAL CONFIGURATION
TA = 25
C, G = +10, RF = 1k
, RG = 50
, and RL = 400
,
unless otherwise noted.
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
R
F
1k
OPA2846
+5V
V
O
V
I
R
G
50
R
F
1k
R
L
400
OPA2846
-
5V
R
G
50
Gain =
= G
D
=
R
F
R
G
V
O
V
I
29
26
23
20
17
14
DIFFERENTIAL LARGE-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
Ga
i
n
(
d
B
)
1
10
100
300
V
O
= 5V
PP
V
O
= 8V
PP
V
O
= 0.4V
PP
G
D
= +20V/V
R
L
= 400
-
65
-
75
-
85
-
95
-
105
-
115
DIFFERENTIAL DISTORTION vs FREQUENCY
Frequency (MHz)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
1
10
100
2nd-Harmonic
G
D
= +20V/V
R
L
= 400
V
O
= 4V
PP
3rd-Harmonic
3
0
-
3
-
6
-
9
-
12
-
15
-
18
DIFFERENTIAL SMALL-SIGNAL
FREQUENCY RESPONSE
Frequency (MHz)
N
o
r
m
a
l
iz
e
d
G
a
in
(
d
B
)
1
10
100
500
G
D
= +30V/V
G
D
= +40V/V
G
D
= +10V/V
G
D
= +20V/V
R
L
= 400
V
O
= 400mV
PP
-
55
-
60
-
65
-
70
-
75
-
80
-
85
-
90
-
95
-
100
-
105
-
110
-
115
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
Resistance (
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c)
50
100
150
200
250
300
350
400
450
500
2nd-Harmonic
3rd-Harmonic
V
O
= 4V
PP
G = 20V/V
-
75
-
80
-
85
-
90
-
95
-
100
-
105
-
110
-
115
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
Output Voltage Swing (V
PP
)
H
a
r
m
o
n
i
c
D
is
t
o
r
t
io
n
(
d
B
c
)
1
10
2nd-Harmonic
G = +20V/V
f = 5MHz
R
L
= 400
3rd-Harmonic
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
12
APPLICATIONS INFORMATION
WIDEBAND, NONINVERTING OPERATION
The OPA2846 provides a unique combination of
features--low input voltage noise along with a very low
distortion output stage--to give one of the highest dynamic
range dual op amps available. Its very high Gain
Bandwidth Product (GBP) can be used either to deliver
high signal bandwidths at high gains, or to deliver very low
distortion signals at moderate frequencies and lower
gains. To achieve the full performance of the OPA2846,
careful attention to PC board layout and component
selection is required, as discussed in the remaining
sections of this data sheet.
Figure 1 shows the noninverting gain of +10 circuit used as
the basis of the Electrical Characteristics and most of the
Typical Characteristics. Most of the curves were charac-
terized using signal sources with 50
driving impedance,
and with measurement equipment presenting a 50
load
impedance. In Figure 1, the 50
shunt resistor at the V
I
terminal matches the source impedance of the test
generator, while the 50
series resistor at the V
O
terminal
provides a matching resistor for the measurement equip-
ment load. Generally, data sheet voltage swing specifica-
tions are at the output pin (V
O
in Figure 1), while output
power (dBm) specifications are at the matched 50
load.
The total 100
load at the output, combined with the 503
total feedback network load, presents the OPA2846 with
an effective output load of 83
for the circuit of Figure 1.
1/2
O PA 2 846
+5V
-
5V
-
V
S
+V
S
50
V
O
V
I
50
+
0.1
F
+
6.8
F
6.8
F
R
G
50
R
F
453
50
Source
50
Load
0.1
F
Figure 1. Noninverting, G = +10 Specification and
Test Circuit
Voltage-feedback op amps, unlike current-feedback
designs, can use a wide range of resistor values to set their
gains. The circuit of Figure 1, and the specifications at
other gains, uses the constraint that R
G
should always be
set to 50
and R
F
adjusted to get the desired gain.
Observing this guideline will ensure that the thermal noise
contribution of the feedback network is insignificant
compared to the 1.2nV/
Hz input voltage noise for the op
amp itself.
WIDEBAND, INVERTING GAIN OPERATION
Operating the OPA2846 as an inverting amplifier has
several benefits and is particularly appropriate when a
matched input impedance is required. Figure 2 shows the
inverting gain circuit used as the basis of the inverting
mode Typical Characteristics.
1 /2
O P A 2846
+5V
-
5V
+V
S
-
V
S
91
50
V
O
V
I
+
6.8
F
0.1
F
+
6.8
F
0.1
F
0.1
F
R
F
1k
R
G
50
50
Source
50
Load
Figure 2. Inverting, G = -20 Characterization
Circuit
Driving this circuit from a 50
source, and constraining the
gain resistor (R
G
) to equal 50
, will give both a signal
bandwidth and noise advantage. R
G
acts as both the input
termination resistor and the gain setting resistor for the
circuit. Although the signal gain (V
O
/V
I
) for the circuit of
Figure 2 is double that for Figure 1, the noise gains are in
fact equal when the 50
source resistor is included. This
has the interesting effect of doubling the equivalent GBP
of the amplifier. This can be seen in comparing the G = +10
and G = -20 small-signal frequency response curves. Both
show approximately 250MHz bandwidth, but the inverting
configuration of Figure 2 gives 6dB higher signal gain. If
the signal source is actually the low impedance output of
another amplifier, R
G
should be increased to the minimum
load resistance value allowed for that amplifier and R
F
should be adjusted to achieve the desired gain. For stable
operation of the OPA2846, it is critical that this driving
amplifier show a very low output impedance at frequencies
beyond the expected closed-loop bandwidth for the
OPA2846.
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
13
LOW-NOISE VDSL RECEIVER
Most xDSL transceiver channels are differential for both
the driver and the receiver. The low-noise, high-gain
bandwidth, and low distortion for the dual OPA2846 make
it an ideal receiver channel element for the demanding
requirements emerging in VDSL. One possible imple-
mentation is shown in Figure 3. This circuit presumes full
duplex communication using frequency division multiplex-
ing, with send-and-receive isolation improved through the
use of a diplexer line interface. The differential receive
signal is brought into the inverting channel gain resistors
to get both noise and distortion improvement for a given
desired gain setting. To get impedance matching, set 2R
G
equal to the required load looking out of the diplexer. The
signal gain is then set by adjusting feedback resistors, R
F
.
Using the OPA2846 in the inverting mode will give you a
reduced noise gain as described in the Wideband,
Inverting Gain Operation section of this data sheet. This
will improve both the SNR and distortion performance. If
the noise gain for a particular application drops below the
minimum recommended stable gain (+7), consider using
the Low-Gain Compensation technique described later in
this data sheet.
1/ 2
OPA 28 46
1/ 2
OPA 28 46
R
F
R
F
R
G
R
G
Diplexer
Driver
Passive
Filter
Analog
Front
End
Low-Noise VDSL Receiver
Figure 3. Low-Noise VDSL Receiver
SINGLE-STAGE TRANSIMPEDANCE DESIGN
When setting up either one or both stages as a broadband
photodiode amplifier, the key elements in the design are
the expected diode capacitance (C
D
) with the reverse bias
voltage (-V
B
) applied, the desired transimpedance gain
R
F
, and the GBP of the OPA2846 (1650MHz). Figure 4
shows a design using a 10pF source capacitance diode
and a 10k
transimpedance gain. With these three
variables set (and including the parasitic input capacitance
for the OPA2846 added to C
D
), the feedback capacitor
value (C
F
) may be set to control the frequency response.
R
F
10k
Power-supply decoupling
not shown.
C
D
10pF
1/2
O P A28 46
+5V
-
5V
-
V
B
I
D
V
O
= I
D
R
F
C
F
0.3pF
Figure 4. Wideband, Low-Noise, Transimpedance
Amplifier
To achieve a maximally-flat, 2nd-order Butterworth
frequency response, the feedback pole should be set to:
1 (2
p
R
F
C
F
)
+
GBP (4
p
R
F
C
D
)
Adding the common-mode and differential mode input
capacitance (1.8 + 2.0)pF to the 10pF diode source
capacitance of Figure 4, and targeting a 10k
transimpedance gain using the 1650MHz GBP for the
OPA2846, will require a feedback pole set to 31MHz. This
will require a total feedback capacitance of 0.5pF. Typical
surface-mount resistors have a parasitic capacitance of
0.2pF, leaving the required 0.3pF value shown in Figure 4
to get the required feedback pole.
(1)
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
14
This will give a -3dB bandwidth approximately equal to:
f
*
3dB
+
GBP 2
p
R
F
C
D
Hz
The example of Figure 4 will give approximately 44MHz
flat bandwidth using the 0.3pF feedback compensation.
If the total output noise is bandlimited to a frequency less
than the feedback pole frequency, a very simple
expression for the equivalent input noise current can be
derived as:
I
EQ
+
I
N
2
)
4kT
R
F
)
E
N
R
F
2
)
(E
N
2
p
C
D
F)
2
3
Where:
I
EQ
= Equivalent input noise current if the output noise is
bandlimited to F < 1/(2
R
F
C
F
)
I
N
= Input current noise for the op amp inverting input
E
N
= Input voltage noise for the op amp
C
D
= Diode capacitance
F = Bandlimiting frequency in Hz (usually a post filter
prior to further signal processing)
Evaluating this expression up to the feedback pole
frequency at 31MHz for the circuit of Figure 4 gives an
equivalent input noise current of 3.1pA/Hz. This is only
slightly higher than the current noise of the op amp itself.
TWO-STAGE TRANSIMPEDANCE DESIGN
The dual OPA2846 may be used as either a dual
transimpedance channel from two photodetectors, or as a
very high gain stage by using one amplifier as the
transimpedance stage with the second used as a post gain
amplifier. See Figure 5 for an example of using one
channel as a transimpedance front end from a large area
detector, with the second amplifier used as a voltage gain
stage to get a 100k
total gain (Z
T
) from a large 50pF
detector (C
D
in Figure 5).
2.67k
20
20
732
2.67k
1/2
O P A 2 84 6
1000pF
C
D
50pF
1.9pF
1 /2
O P A 28 46
-
V
B
Figure 5. High-Gain, Wideband Transimpedance
Amplifier
One key question in this design is how best to split up the
first and second stage gains. If bandwidth optimization
from a given photodetector capacitance (C
D
in Figure 5) is
the primary goal, Equation 4 gives a solution for R
F
in the
input stage that will provide an equal bandwidth in the first
and second stages, giving the maximum overall channel
bandwidth.
R
F
+
Z
T
2
2
p
C
D
GBP
Where:
Z
T
= Desired total transimpedance gain
C
D
= Diode capacitance at reverse bias
GBP = Amplifier Gain Bandwidth Product (MHz)
This equation is used to calculate the required input stage
feedback resistor in Figure 5. The remaining total signal
gain is provided by the second stage; in the example of
Figure 5, setting G = 37.5 gives the same bandwidth
(approximately 44MHz) as the bandwidth achieved by the
input stage. To set this first stage bandwidth to its
maximally flat values, use Equation 5 to set the feedback
capacitor value:
C
F
+
C
D
p
R
F
GBP
f
*
3dB
+
1
2
(GBP)
2 3
(2
p
C
D
)
1 3
(Z
T
)
1 3
The approximate achievable bandwidth in the two stages
is given by Equation 6, which gives approximately 30MHz
for Figure 5.
LOW-GAIN COMPENSATION FOR
IMPROVED SFDR
Where a low gain is desired, and inverting operation is
acceptable, a new external compensation technique may
be used to retain the full slew rate and noise benefits of the
OPA2846 while giving increased loop gain and the
associated improvement in distortion offered by the
decompensated architecture. This technique shapes the
loop gain for good stability while giving an easily-con-
trolled, 2nd-order, low-pass frequency response. Consid-
ering only the noise gain (noninverting signal gain, which
is also called the Noise Gain or NG) for the circuit of
Figure 6, the low-frequency noise gain, (NG
1
) will be set
by the resistor ratios while the high-frequency noise gain
(NG
2
) will be set by the capacitor ratios. The capacitor
values set both the transition frequencies and the
high-frequency noise gain. If this noise gain (determined
by NG
2
= 1 + C
S
/C
F
) is set to a value greater than the
recommended minimum stable gain for the op amp, and
the noise gain pole (set by 1/R
F
C
F
) is placed correctly, a
very well-controlled, 2nd-order, low-pass frequency
response will result.
(2)
(3)
(4)
(5)
(6)
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
15
R
F
402
C
S
29pF
1/2
O P A 2846
+5V
-
5V
V
O
V
I
C
F
3.2pF
R
G
201
Figure 6. Broadband Low-Gain Inverting External
Compensation
To choose the values for both C
S
and C
F
, two parameters
and only three equations need to be solved. The first
parameter is the target high-frequency noise gain NG
2
,
which should be greater than the minimum stable gain for
the OPA2846. Here, a target NG
2
of 10 will be used. The
second parameter is the desired low-frequency signal
gain, which also sets the low-frequency noise gain NG
1
. To
simplify this discussion, we will target a maximally-flat,
2nd-order, low-pass Butterworth frequency response
(Q = 0.707). The signal gain of -2 shown in Figure 6 will
set the low-frequency noise gain to NG
1
= 1 + R
F
/R
G
(NG
1
= 3 in this example). Then, using only these two
gains and the GBP for the OPA2846 (1650MHz), the key
frequency in the compensation can be determined as:
Z
0
+
GBP
NG
2
1
1
*
NG
1
NG
2
*
1
*
2
NG
1
NG
2
Physically, this Z
0
(12.4MHz for the values shown above)
is set by 1/[2
R
F
(C
F
+ C
S
)] and is the frequency at which
the rising portion of the noise gain would intersect unity
gain if projected back to 0dB gain. The actual zero in the
noise gain occurs at NG
1
Z
0
, and the pole in the noise
gain occurs at NG
2
Z
0
. Since GBP is expressed in Hz,
multiply Z
0
by 2
and use this to get C
F
by solving:
C
F
+
1
2
p
R
F
Z
0
NG
2
(
+
3.2pF)
Finally, since C
S
and C
F
set the high-frequency noise gain,
determine C
S
by:
C
S
+
(NG
2
*
1)C
F
(
+
28.8pF)
The resulting closed-loop bandwidth will be approximately
equal to:
f
*
3dB
^
Z
0
GBP
(
+
143MHz)
For the values of Figure 6, the f
-3dB
will be approximately
130MHz. This is less than that predicted by simply dividing
the GBP by NG
1
. The compensation network controls the
bandwidth to a lower value while providing the full slew rate
at the output and an exceptional distortion performance
due to increased loop gain at frequencies below NG
1
Z
0
.
The capacitor values of Figure 6 are calculated for NG
1
=
3 and NG
2
= 10 with no adjustment for parasitics.
Figure 7 shows the measured frequency response for the
circuit of Figure 6. This shows the expected gain of -2
(6dB) with exceptional flatness through 70MHz and a
-3dB bandwidth of 170MHz. Measured distortion into a
100
load shows > 5dB improvement through 20MHz
over the performance shown in the Typical Characteris-
tics. Into a 500
load, the 5MHz, 2V
PP
, 2nd-harmonic
improves from -85dBc to -92dBc.
9
6
3
0
-
3
-
6
-
9
-
12
-
15
Frequency (Hz)
G
a
i
n
(
3dB
/
d
i
v
)
1M
10M
100M
1G
Figure 7. Low Gain Inverting Frequency
Response
DC-COUPLED, SINGLE-TO-DIFFERENTIAL
ADC DRIVER
Many very high performance CMOS ADCs are intended to
operate with a differential input signal. Translating a
single-ended source to this differential input while
controlling the common-mode operating voltage can
present a considerable challenge where high SFDR is
required. See Figure 8 for one way to do this, where very
low harmonic distortion is required, and good common-
mode control and DC precision is desired.
This particular example is set for a signal gain of 16 from
the single-ended input to the differential output voltage.
Since the common-mode control signal (from the output of
the OPA820) is fed into the midpoint of the two gain
resistors (93.8
), this DC control path requires a very low
source impedance through high frequencies to maintain
the desired signal path gain. A wideband, unity-gain
stable, voltage-feedback op amp like the OPA820 makes
an ideal choice to provide this low output impedance DC
control signal. This op amp also compares the output
common-mode voltage to the desired V
CM
, and servos the
OPA2846 common-mode output voltage to that value,
using an integrator loop. This holds the output common-
mode voltage precisely at V
CM
while giving the low output
impedance required of the circuit.
(7)
(8)
(9)
(10)
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
16
OPA8 20
Power-supply decoupling
not shown.
1/2
OPA2846
200
1.3
H
2.01k
12
750
95
+5V
200
3.8k
100
3.8k
93.8
93.8
750
+5V
1
F
30pF
0.1
F
V
-
V
CM
V+
14-Bit
10MSPS
ADS850
+5V
-
5V
1/2
OPA2846
750
-
5V
49.9
50
Input
Impedance
750
93.8
0.1
F
+5V
V
I
1.3
H
Voltage at V+ to V
-
= 2V
PP
2nd-order Butterworth post filter f
-
3dB
= 18MHz.
2.5V
Figure 8. DC-Coupled, Single-to-Differential High SFDR ADC Driver
Operating at +2.5V output common-mode requires a DC
level shifting current through the feedback resistors. Since
this current is to the supply midpoint, pull-up resistors
equal to the feedback resistors are connected to the
positive supply to keep the output stage signal currents
equal and bipolar. This significantly improves 2nd-har-
monic distortion.
One side of the OPA2846 is operating at a gain of +9 with
some attenuation of the input signal to have an equivalent
+8 gain. The other side of the OPA2846 is operating at a
gain of -8.
To deliver a 2V
PP
differential input signal on a 2.5V
common-mode voltage, each output must swing between
2.0V and 3.0V. Tested harmonic distortion performance for
this condition from 1MHz to 10MHz is shown in Figure 9.
In this case, the 2nd-harmonic distortion is still dominant
due to slight signal path imbalances. The distortion levels,
however, are very low. Thus, narrowband applications
which are impacted by only 3rd-order terms will see very
low single- and two-tone distortion levels.
-
70
-
75
-
80
-
85
-
90
-
95
Frequency (MHz)
1
10
H
a
r
m
on
i
c
D
i
s
t
or
ti
o
n
(
d
B
c
)
2nd-Harmonic
3rd-Harmonic
Figure 9. Harmonic Distortion vs Frequency for
the Circuit of Figure 8
For more information on the 2nd-order post filter, refer to
RLC Filter Design for ADC Interface Applications
(SBAA108), available for download at www.ti.com.
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
17
AC-COUPLED, SINGLE-TO-DIFFERENTIAL
ADC DRIVER
Where the signal path may be AC-coupled, a very
balanced, high SFDR dual op amp interface circuit can
easily be provided by the OPA2846. Figure 10 shows a
specific example of this application, where the input
single-to-differential conversion is provided by an input
transformer. Once the signal source is purely differential,
the circuit of Figure 10 provides low harmonic distortion
with a common-mode control path that does not interact
with the signal path gain. If the source is already
differential, such as at the output of a balanced mixer, the
input transformer could be replaced by blocking
capacitors.
In the example of Figure 10, the secondary of the
transformer is connected into the two inverting path gain
resistors (100
). These resistors provide both an input
impedance match (assuming a 50
source on the primary
of this 1:2 step-up transformer) and set the signal gain for
each amplifier along with the 500
feedback resistors.
Although relatively high signal gain is provided by this
circuit (10 in this case), each amplifier is operating at a
relatively low noise gain (3.5V/V). This low-noise gain at
low frequencies gives high loop gain for distortion
suppression in the baseband. External compensation
capacitors (18pF and 2.1pF) are included to hold the
frequency response flat, as described in the Low-Gain
Compensation For Improved SFDR section of this data
sheet. The common-mode operating voltage is fed into
each amplifier's noninverting input. Since these are equal,
and will appear at each inverting input as well, no DC
current is produced through the transformer secondary
due to this common-mode operating voltage. Since no
current flows due to V
CM
, the output will operate at V
CM
as
well. This is one of the few common-mode operating point
control techniques that requires no current to flow. This
makes the common-mode control aspect of this circuit
essentially non-interactive with the signal path. To provide
a 2V
PP
differential signal operating at a 2.5V output
common-mode requires a 2.0V to 3.0V output swing on
each output. Tested performance over frequency for the
circuit of Figure 10 is shown in Figure 11.
Single-to-Differential
Gain of 10
Power-supply decoupling
not shown.
V
CM
+10V
I
1/2
OPA2846
L
2.5V
+5V
V
CM
V
CM
L
R
1
R
1
500
500
R
2
C
1
F
C
V
-
V
CM
R
2
V+
14-Bit
10MSPS
ADS850
2.1pF
1/2
OPA2846
500
-
5V
18pF
1000pF
1000pF
18pF
100
100
500
2.1pF
V
I
50
1:2
Figure 10. AC-Coupled, Single-to-Differential High SFDR ADC Driver
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
18
-
80
-
85
-
90
-
95
-
100
-
105
-
110
Frequency (MHz)
1
10
H
a
r
m
on
i
c
D
i
s
t
or
ti
o
n
(
d
B
c
)
V
O
= 2V
PP
Differential
3rd-Harmonic, 0V
DC
3rd-Harmonic, +2.5V
DC
2nd-Harmonic, 0V
DC
2nd-Harmonic, +2.5V
DC
Figure 11. Harmonic Distortion for Figure 10
Figure 11 shows 2nd- and 3rd-harmonic distortion for a
2V
PP
differential output swing at both 0V output
common-mode voltage and +2.5V common-mode volt-
age. Since there is no DC current required from the output
to level shift to +2.5V in this circuit, no pull-up resistors to
the power supply were used as in the circuit of Figure 8.
The 2nd harmonic remains the dominant distortion
mechanism, but shows little sensitivity to the common-
mode operating voltage (improved 2nd-harmonic distor-
tion results were achieved with this circuit using two
individual OPA846's with an extremely symmetrical
layout). The 3rd harmonic is essentially unmeasureable
for the ground-centered output swing, but increases as the
output is shifted to a +2.5V DC output. Narrowband
systems, where a bandpass filter less than an octave wide
can be inserted between the amplifier and the converter,
will only be concerned about 2-tone, 3rd-order inter-
modulation distortion. Since this bandpass filter is also
AC-coupled, the outputs of Figure 10 may be operated
ground-centered, giving the extremely low 3rd-order
distortions of Figure 11.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
A PC board is available to assist in the initial evaluation of
circuit performance using the OPA2846. It is available free,
as an unpopulated PC board delivered with descriptive
documentation. The summary information for this board is
shown in Table 1.
Contact the Texas Instruments applications support line to
request this board or visit Texas Instruments' web site at
www.ti.com.
PRODUCT
PACKAGE
BOARD PART
NUMBER
LITERATURE
REQUEST
NUMBER
OPA2846ID
SO-8 Surface-Mount
DEM-OPA268xU
SBOU003
Table 1. Evaluation Module Ordering Information
MACROMODELS AND APPLICATIONS
SUPPORT
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance.
A SPICE model for the OPA2846 is available through the
Texas Instruments web page (http://www.ti.com).
These models do a good job of predicting small-signal AC
and transient performance under a wide variety of
operating conditions. They do not do as well in predicting
the harmonic distortion characteristics.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO MINIMIZE
NOISE
The OPA2846 provides a very low input noise voltage
while requiring a low 12.6mA/channel quiescent current.
To take full advantage of this low input noise, careful
attention to the other possible noise contributors is
required. Figure 12 shows the op amp noise analysis
model with all the noise terms included. In this model, all
the noise terms are taken to be noise voltage or current
density terms in either nV/
Hz or pA/
Hz.
4kT
R
G
R
G
R
F
R
S
1/2
OPA2846
I
BI
E
O
I
BN
4kT = 1.6E
-
20J
at 290
_
K
E
RS
E
NI
4kTR
S
4kTR
F
Figure 12. Op Amp Noise Analysis Model
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
19
The total output spot noise voltage can be computed as the
square root of the squared contributing terms to the output
noise voltage. This computation adds all the contributing
noise powers at the output by superposition, then takes the
square root to get back to a spot noise voltage.
Equation 11 shows the general form for this output noise
voltage using the terms shown in Figure 12.
E
O
+
E
2
NI
)
I
BN
R
S
2
)
4kTR
S
NG
2
)
I
BI
R
F
2
)
4kTR
F
NG
Dividing this expression by the noise gain
(NG = 1 + R
F
/R
G
) will give the equivalent input-referred
spot noise voltage at the noninverting input as shown in
Equation 12.
E
N
+
E
2
NI
)
I
BN
R
S
2
)
4kTR
S
)
I
BI
R
F
NG
2
)
4kTR
F
NG
Inserting high resistor values into Equation 12 can quickly
dominate the total equivalent input referred noise. A 105
source impedance on the noninverting input will add a
thermal voltage noise term equal to that of the amplifier
itself. As a simplifying constraint, set R
G
= R
S
in
Equation 12 and assume an R
S
/2 source impedance at
the noninverting input (where R
S
is the signal's source
impedance with another matching R
S
to ground on the
noninverting input). This results in Equation 13, where
NG > 10 has been assumed to further simplify the
expression.
E
N
+
(E
NI
)
2
)
5
4
I
B
R
S
2
)
4kT
3R
S
2
Evaluating this expression for R
S
= 50
will give a total
equivalent input noise of 1.64nV/
Hz. Note that the NG
has dropped out of this expression. This is valid only for
NG > 10.
FREQUENCY RESPONSE CONTROL
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the GBP shown in the
specifications. Ideally, dividing GBP by the noninverting
signal gain will predict the closed-loop bandwidth. In
practice, this only holds true when the phase margin
approaches 90
, as it does in high gain configurations. At
low gains (with an increased feedback factor), most
high-speed amplifiers will exhibit a more complex
response with lower phase margin. The OPA2846 is
compensated to give a maximally-flat, 2nd-order,
Butterworth, closed-loop response at a noninverting gain
of +10 (see Figure 1). This results in a typical gain of +10
bandwidth of 300MHz, far exceeding that predicted by
dividing the 1650MHz GBP by 10. Increasing the gain will
cause the phase margin to approach 90
and the
bandwidth to more closely approach the predicted value of
(GBP/NG). At a gain of +40, the OPA2846 will show the
41MHz bandwidth predicted using the simple formula and
the typical GBP of 1650MHz.
Inverting operation offers some interesting opportunities to
increase the available GBP. When the source impedance
is matched by the gain resistor (see Figure 2), the signal
gain is (1 + R
F
/R
G
) while the noise gain for bandwidth
purposes is (1 + R
F
/2R
G
). This cuts the noise gain almost
in half, increasing the minimum stable gain for inverting
operation under these condition to -12 and the equivalent
GBP to 3.2GHz.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter, including
additional external capacitance which may be recom-
mended to improve ADC linearity. A high-speed, high
open-loop gain amplifier like the OPA2846 can be very
susceptible to decreased stability and closed-loop re-
sponse peaking when a capacitive load is placed directly
on the output pin. When the amplifier's open-loop output
resistance is considered, this capacitive load introduces
an additional pole in the signal path that can decrease the
phase margin. Several external solutions to this problem
have been suggested. When the primary considerations
are frequency response flatness, pulse response fidelity,
and/or distortion, the simplest and most effective solution
is to isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds
a zero at a higher frequency. The additional zero acts to
cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
The Typical Characteristics show the recommended R
S
vs
Capacitive Load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA2846. Long
PC board traces, unmatched cables, and connections to
multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and add
the recommended series resistor as close as possible to
the OPA2846 output pin (see the Board Layout section).
The criterion for setting this R
S
resistor is a maximum
bandwidth, flat frequency response at the load. For the
OPA2846 operating in a gain of +10, the frequency
response at the output pin is very flat to begin with,
allowing relatively small values of R
S
to be used for low
capacitive loads. As the signal gain is increased, the
unloaded phase margin will also increase. Driving
capacitive loads at higher gains will require lower R
S
values than those shown for a gain of +10.
(11)
(12)
(13)
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
20
DISTORTION PERFORMANCE
The OPA2846 is capable of delivering an exceptionally low
distortion signal at high frequencies over a wide range of
gains. The distortion plots in the Typical Characteristics
show the typical distortion under a wide variety of
conditions. Most of these plots are limited to 110dB
dynamic range.
Generally, until the fundamental signal reaches very high
frequencies or powers, the 2nd-harmonic will dominate the
distortion with a negligible 3rd-harmonic component.
Focusing then on the 2nd-harmonic, increasing the load
impedance improves distortion directly. Remember that
the total load includes the feedback network; in the
noninverting configuration, this is sum of (R
F
+ R
G
), while
in the inverting configuration, it is just R
F
(see Figure 1 and
Figure 2). Increasing output voltage swing increases
harmonic distortion directly. A 6dB increase in output
swing will generally increase the 2nd-harmonic to 12dB
and the 3rd-harmonic to 18dB. Increasing the signal gain
will also increase the 2nd-harmonic distortion. Again, a
6dB increase in gain will increase the 2nd and 3rd
harmonic by approximately 6dB each, even with constant
output power and frequency. Finally, the distortion
increases as the fundamental frequency increases, due to
the rolloff in the loop gain with frequency. Conversely, the
distortion will improve going to lower frequencies down to
the dominant open-loop pole at approximately 100kHz.
Starting from the -82dBc 2nd-harmonic for a 5MHz, 2V
PP
fundamental into a 200
load at G = +10 (from the Typical
Characteristics), the 2nd-harmonic distortion for frequen-
cies lower than 100kHz will approximately be:
-82dBc - 20 log(5MHz/100kHz) = -116dBc
The OPA2846 has extremely low 3rd-order harmonic
distortion. This also gives a high 2-tone, 3rd-order
intermodulation intercept as shown in the Typical
Characteristics. This intercept curve is defined at the 50
load when driven through a 50
matching resistor to allow
direct comparisons to RF MMIC devices. This matching
network attenuates the voltage swing from the output pin
to the load by 6dB. If the OPA2846 drives directly into the
input of a high impedance device, such as an A/D
converter, the 6dB attenuation is not taken. Under these
conditions, the intercept will increase by a minimum 6dBm.
The intercept is used to predict the intermodulation
spurious for two, closely-spaced frequencies. If the two
test frequencies, f
1
and f
2
, are specified in terms of
average and delta frequency, f
O
= (f
1
+ f
2
)/2 and f = |f
2
-
f
1
|/2, the two 3rd-order, close-in spurious tones will appear
at f
O
3
f. The difference between two equal test-tone
power levels and these intermodulation spurious power
levels is given by dBc = 2
(IM3 - P
O
) where IM3 is the
intercept taken from the Typical Characteristic and P
O
is
the power level, in dBm, at the 50
load for one of the two
closely-spaced test frequencies. For instance, at 10MHz,
the OPA2846 at a gain of +10 has an intercept of 44dBm
at a matched 50
load. If the full envelope of the two
frequencies needs to be 2V
PP
, this requires each tone to
be 4dBm. The 3rd-order intermodulation spurious tones
will then be 2
(48 - 4) = 88dBc below the test-tone
power level (-84dBm). If this same 2V
PP
, 2-tone envelope
were delivered directly into the input of an ADC--without
the matching loss or the loading of the 50
network--the
intercept would increase to at least 50dBm. With the same
signal and gain conditions, but now driving directly into a
light load, the spurious tones will then be at least
2
(54 - 4) = 100dBc below the 4dBm test-tone power
levels centered on 10MHz.
DC ACCURACY AND OFFSET CONTROL
The OPA2846 can provide excellent DC signal accuracy
due to its high open-loop gain, high common-mode
rejection, high power-supply rejection, and low input offset
voltage and bias current offset errors. To take full
advantage of its low
0.65mV input offset voltage, careful
attention to input bias current cancellation is also required.
The low noise input stage of the OPA2846 has a relatively
high input bias current (10
A typical into the pins), but with
a very close match between the two input currents--typi-
cally
100nA input offset current. The total output offset
voltage may be reduced considerably by matching the
source impedances looking out of the two inputs. For
example, one way to add bias current cancellation to the
circuit of Figure 1 (page 12) would be to insert a 20
series resistor into the noninverting input from the 50
terminating resistor. When the 50
source resistor is
DC-coupled, this will increase the source resistances for
the noninverting input bias current to 45
. Since this is
now equal to the resistance looking out of the inverting
input (R
F
|| R
G
), the circuit will cancel the gains for the bias
currents to the output, leaving only the offset current times
the feedback resistor as a residual DC error term at the
output. Using the 453
feedback resistor, this output error
will now be less than
0.6
A
453
=
0.27mV over the
full temperature range.
A fine-scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing a DC offset control into an op amp
circuit. Most of these techniques eventually reduce to
setting up a DC current through the feedback resistor. One
key consideration to selecting a technique is to insure that
it has a minimal impact on the desired signal path
frequency response. If the signal path is intended to be
noninverting, the offset control is best applied as an
inverting summing signal to avoid interaction with the
signal source. If the signal path is intended to be inverting,
applying the offset control to the noninverting input can be
considered. For a DC-coupled inverting input signal, this
DC offset signal will set up a DC current back into the
source that must be considered. An offset adjustment
placed on the inverting op amp input can also change the
noise gain and frequency response flatness.
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
21
Figure 13 shows one example of an offset adjustment for
a DC-coupled signal path that will have minimum impact
on the signal frequency response. In this case, the input is
brought into an inverting gain resistor with the DC
adjustment an additional current summed into the
inverting node. The resistor values setting this offset
adjustment are much larger than the signal path resistors.
This will insure that this adjustment has minimal impact on
the loop gain and hence, the frequency response as well.
R
F
1k
200mV Output Adjustment
=
-
=
-
20
Power-supply decoupling
not shown.
5k
5k
48
0.1
F
R
G
50
V
I
20k
10k
0.1
F
-
5V
+5V
1/2
OPA2846
+5V
-
5V
V
O
V
O
V
I
R
F
R
G
Figure 13. DC-Coupled, Inverting Gain of -20,
with Output Offset Adjustment
THERMAL ANALYSIS
The OPA2846 will not require heatsinking or airflow in
most applications. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed +150
C.
Operating junction temperature (T
J
) is given by
T
A
+ P
D
q
JA
. The total internal power dissipation (P
D
) is
the sum of quiescent power (P
DQ
) and additional power
dissipated in the output stage (P
DL
) to deliver load power.
Quiescent power is simply the specified no-load supply
current times the total supply voltage across the part. P
DL
will depend on the required output signal and load but
would, for a grounded resistive load, be at a maximum
when the output is fixed at a voltage equal to 1/2 either
supply voltage (for equal bipolar supplies). Under this
worst-case condition, P
DL
= V
S
2
/(4
R
L
) where R
L
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using
both channels of the OPA2846ID in the circuit of Figure 1
(page 12) operating at the maximum specified ambient
temperature of +85
C and driving a grounded 100
load
at +2.5V
DC
:
P
D
= 10V
(26.6mA) + 2
[5
2
/(4
(100
|| 500
))] = 416mW
Maximum T
J
= +85
C + (0.416
125
C/
) = 137
C
This absolute worst-case example will never be
encountered in practice. Therefore, 137
C sets an upper
limit to maximum operating junction temperature.
BOARD LAYOUT
Achieving optimum performance with a high-frequency
amplifier like the OPA2846 requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability; on the
noninverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around
those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
b) Minimize the distance (< 0.25") from the
power-supply pins to high-frequency 0.1
F decoup-
ling capacitors. At the device pins, the ground and
power-plane layout should not be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces to
minimize inductance between the pins and the decoupling
capacitors. The power-supply connections should always
be decoupled with these capacitors. Larger (2.2
F to
6.8
F) decoupling capacitors, effective at lower frequen-
cies, should also be used on the main supply pins. These
may be placed somewhat farther from the device and may
be shared among several devices in the same area of the
PC board.
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA2846. Resistors should be a very
low reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Metal-film and carbon
composition, axially-leaded resistors can also provide
good high-frequency performance. Again, keep their leads
and PC board trace length as short as possible. Never use
wirewound type resistors in a high-frequency application.
Since the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input termination resistors, should
also be placed close to the package. Where double-side
component mounting is allowed, place the feedback
OPA2846
SBOS274A -JUNE 2003 - REVISED MARCH 2004
www.ti.com
22
resistor directly under the package on the other side of the
board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external
resistors, excessively high resistor values can create
significant time constants that can degrade performance.
Good axial metal-film or surface-mount resistors have
approximately 0.2pF in shunt with the resistor. For resistor
values > 1.5k
, this parasitic capacitance can add a pole
and/or a zero below 500MHz that can affect circuit
operation. Keep resistor values as low as possible,
consistent with load driving considerations. It has been
suggested here that a good starting point for design would
be to set R
G
to 50
. Doing this will automatically keep the
resistor noise terms low, and minimize the effect of their
parasitic capacitance.
d) Connections to other wideband devices on the
board may be made with short direct traces or through
onboard transmission lines. For short connections,
consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the total
capacitive load and set R
S
from the plot of recommended
R
S
vs Capacitive Load. Low parasitic capacitive loads
(< 5pF) may not need an R
S
since the OPA2846 is
nominally compensated to operate with a 2pF parasitic
load. Higher parasitic capacitive loads without an R
S
are
allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated transmis-
sion line is acceptable, implement a matched impedance
transmission line using microstrip or stripline techniques
(consult an ECL design handbook for microstrip and
stripline layout techniques). A 50
environment is
normally not necessary on board, and in fact, a higher
impedance environment will improve distortion, as shown
in the distortion versus load plots. With a characteristic
board trace impedance defined based on board material
and trace dimensions, a matching series resistor into the
trace from the output of the OPA2846 is used as well as a
terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance
will be the parallel combination of the shunt resistor and
the input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as
a capacitive load in this case and set the series resistor
value as shown in the plot, R
S
vs Capacitive Load. This will
not preserve signal integrity as well as a doubly-terminated
line. If the input impedance of the destination device is low,
there will be some signal attenuation due to the voltage
divider formed by the series output into the terminating
impedance.
e) Socketing a high-speed part like the OPA2846 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an
extremely troublesome parasitic network, which can make
it almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the
OPA2846 onto the board.
INPUT AND ESD PROTECTION
The OPA2846 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very small
geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device pins are
protected with internal ESD protection diodes to the power
supplies, as shown in Figure 13.
External
Pin
+V
CC
-
V
CC
Internal
Circuitry
Figure 14. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA continuous
current. Where higher currents are possible (for example,
in systems with
15V supply parts driving into the
OPA2846), current-limiting series resistors should be
added into the two inputs. Keep these resistor values as
low as possible since high values degrade both noise
performance and frequency response.
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