TM
1998 Burr-Brown Corporation
PDS-1434C
Printed in U.S.A. October, 1999
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
OPA3680
Triple, Wideband, Voltage-Feedback
OPERATIONAL AMPLIFIER With Disable
FEATURES
q
WIDEBAND +5V OPERATION: 220MHz (G = +2)
q
HIGH OUTPUT CURRENT: 150mA
q
OUTPUT VOLTAGE SWING:
4.0V
q
HIGH SLEW RATE: 1800V/
s
q
LOW SUPPLY CURRENT: 6.4mA/ch
q
LOW DISABLED CURRENT: 300
A/ch
q
ENABLE/DISABLE TIME: 25ns/100ns
APPLICATIONS
q
VIDEO LINE DRIVING
q
xDSL LINE DRIVER
q
HIGH-SPEED IMAGING CHANNELS
q
ADC BUFFERS
q
PORTABLE INSTRUMENTS
q
TRANSIMPEDANCE AMPLIFIERS
q
ACTIVE FILTERS
DESCRIPTION
The OPA3680 represents a major step forward in
unity gain stable, voltage-feedback op amps. A new
internal architecture provides slew rate and full power
bandwidth previously found only in wideband cur-
rent-feedback op amps. A new output stage architec-
ture delivers high currents with a minimal headroom
requirement. These give exceptional single-supply
operation. Using a single +5V supply, the OPA3680
can deliver a 1V to 4V output swing with over 80mA
drive current and 150MHz bandwidth. This combina-
tion of features makes the OPA3680 an ideal RGB
line driver or single-supply ADC input driver.
The OPA3680's low 6.4mA/ch supply current is pre-
cisely trimmed at 25
C. This trim, along with low
temperature drift, guarantees lower maximum supply
current than competing products. System power may be
reduced further using the optional disable control pin.
Leaving this disable pin open, or holding it high, will
operate the OPA3680 normal. If pulled low, the
OPA3680 supply current drops to less than 300
A/ch
while the output goes into a high impedance state. This
feature may be used for either power savings or to
implement video MUX applications.
OPA3680 RELATED PRODUCTS
SINGLES
DUALS
TRIPLES
Voltage Feedback
OPA680
OPA2680
OPA3680
Current Feedback
OPA681
OPA2681
OPA3681
Fixed Gain
OPA682
OPA2682
OPA3682
OPA3680
OPA3680
1/3
OPA3680
1/3
OPA3680
V
IN
V
OUT
49.9
49.9
R
75.0
49.9
49.9
R
75.0
249
249
249
1pF
C
330pF
C
330pF
1/3
OPA3680
249
1pF
Buffered Analog Delay Line (100ns)
For most current data sheet and other product
information, visit www.burr-brown.com
SBOS087
2
OPA3680
SPECIFICATIONS: V
S
=
5V
R
F
= 250
, R
L
= 100
, and G = +2
,
(Figure 1 for AC performance only), R
F
= 25
for G = +1, unless otherwise noted.
OPA3680E, U
TYP
GUARANTEED
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(2)
70
C
(3)
+85
C
(3)
UNITS
MAX
LEVEL
(1)
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth
G = +1, V
O
= 0.5Vp-p, R
F
= 25
400
MHz
typ
C
G = +2, V
O
= 0.5Vp-p
220
210
200
190
MHz
min
B
G = +10, V
O
= 0.5Vp-p
30
20
20
20
MHz
min
B
Gain Bandwidth Product
G
10
300
200
200
200
MHz
min
B
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
< 0.5Vp-p
30
MHz
typ
C
Peaking at a Gain of +1
V
O
< 0.5Vp-p
4
dB
typ
C
Large-Signal Bandwidth
G = +2, V
O
= 5Vp-p
175
MHz
typ
C
Slew Rate
G = +2, 4V Step
1800
1400
1200
900
V/
s
min
B
Rise/Fall Time
G = +2, V
O
= 0.5V Step
1.4
ns
max
B
G = +2, V
O
= 4V Step
2.8
ns
max
B
Settling Time to 0.02%
G = +2, V
O
= 0
2V Step
12
ns
typ
C
0.1%
G = +2, V
O
= 0
2V Step
8
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, V
O
= 2Vp-p
2nd Harmonic
R
L
= 100
80
dBc
typ
C
R
L
500
90
dBc
typ
C
3rd Harmonic
R
L
= 100
77
dBc
typ
C
R
L
500
90
dBc
typ
C
Crosstalk
Input Referred, f = 5MHz, All Hostile
58
dBc
typ
C
Input Voltage Noise
f > 1MHz
4.8
5.3
5.9
6.1
nV/
Hz
max
B
Input Current Noise
f > 1MHz
2.5
2.8
3.0
3.6
pA/
Hz
max
B
Differential Gain
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150
0.05
%
typ
C
Differential Phase
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150
0.03
deg
typ
C
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (A
OL
)
V
O
= 0V, R
L
= 100
58
54
52
50
dB
min
A
Input Offset Voltage
V
CM
= 0V
1.0
5.0
5.5
6.5
mV
max
A
Average Offset Voltage Drift
V
CM
= 0V
10
10
V/
C
max
B
Input Bias Current
V
CM
= 0V
+8
+15
+20
+35
A
max
A
Average Bias Current Drift (magnitude)
V
CM
= 0V
70
150
nA/
C
max
B
Input Offset Current
V
CM
= 0V
0.1
0.8
1.2
1.5
A
max
A
Average Offset Current Drift
V
CM
= 0V
1
1.5
nA/
C
max
B
INPUT
Common-Mode Input Range (CMIR)
(5)
3.5
3.4
3.3
3.2
V
min
A
Common-Mode Rejection Ratio (CMRR)
V
CM
=
1.0V
59
56
53
53
dB
min
A
Input Impedance
Differential-Mode
190 || 0.6
k
|| pF
typ
C
Common-Mode
3.2 || 0.9
M
|| pF
typ
C
OUTPUT
Voltage Output Swing
No Load
4.0
3.8
3.7
3.6
V
min
A
100
Load
3.9
3.7
3.6
3.3
V
min
A
Current Output, Sourcing
V
O
= 0
+190
+160
+140
+80
mA
min
A
Current Output, Sinking
V
O
= 0
150
135
130
80
mA
min
A
Closed-Loop Output Impedance
G = +2, f = 100kHz
0.03
typ
C
DISABLE
Disable Low
Power-Down Supply Current (+V
S
)
V
DIS
= 0V, Each Channel
300
A
typ
C
Disable Time
100
ns
typ
C
Enable Time
25
ns
typ
C
Off Isolation
G = +2, 5MHz
70
dB
typ
C
Output Capacitance in Disable
4
pF
typ
C
Turn On Glitch
G = +2, R
L
= 150
50
mV
typ
C
Turn Off Glitch
G = +2, R
L
= 150
20
mV
typ
C
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
Control Pin Input Bias Current
V
DIS
= 0V
100
160
160
160
A
max
A
POWER SUPPLY
Specified Operating Voltage
5
V
typ
C
Maximum Operating Voltage Range
6
6
6
V
max
A
Max Quiescent Current
V
S
=
5V, Each Channel
6.4
6.8
7.0
7.2
mA
max
A
Min Quiescent Current
V
S
=
5V, Each Channel
6.4
6.0
6.0
5.3
mA
min
A
Power Supply Rejection Ratio (+PSRR)
Input Referred
65
60
58
58
dB
min
A
THERMAL CHARACTERISTICS
Specified Operating Range U, E Package
40 to +85
C
typ
C
Thermal Resistance,
JA
U
SO-16
100
C/W
typ
C
E
SSOP-16
100
C/W
typ
C
NOTES: (1) Test Levels: (A) 100% tested at 25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25
C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = Ambient +23
C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node.
V
CM
is the input common-mode voltage. (5) Tested < 3dB below minimum CMR specification at
CMIR limits.
3
OPA3680
SPECIFICATIONS: V
S
= +5V
R
F
= 250
, R
L
= 100
to V
S
/2, G = +2
,
(Figure 2 for AC performance only), R
F
= 25
for G = +1, unless otherwise noted.
OPA3680E, U
TYP
GUARANTEED
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(2)
70
C
(3)
+85
C
(3)
UNITS
MAX LEVEL
(1)
AC PERFORMANCE (Figure 2)
Small-Signal Bandwidth
G = +1, V
O
< 0.5Vp-p
300
MHz
typ
C
G = +2, V
O
< 0.5Vp-p
220
160
160
140
MHz
min
B
G = +10, V
O
< 0.5Vp-p
25
20
19
18
MHz
min
C
Gain Bandwidth Product
G
10
250
200
190
180
MHz
min
B
Bandwidth for 0.1dB Gain Flatness
G = +2, V
O
< 0.5Vp-p
20
MHz
typ
C
Peaking at a Gain of +1
V
O
< 0.5Vp-p
5
dB
typ
C
Large-Signal Bandwidth
G = +2, V
O
= 2Vp-p
175
MHz
typ
C
Slew Rate
G = +2, 2V Step
1000
700
670
550
V/
s
min
B
Rise Time
G = +2, V
O
= 0.5V Step
1.6
ns
typ
C
Fall Time
G = +2, V
O
= 2V Step
2.0
ns
typ
C
Settling Time to 0.02%
G = +2, V
O
= 2V Step
12
ns
typ
C
0.1%
G = +2, V
O
= 2V Step
8
ns
typ
C
Harmonic Distortion
G = +2, f = 5MHz, V
O
= 2Vp-p
2nd Harmonic
R
L
= 100
70
dBc
typ
C
R
L
500
80
dBc
typ
C
3rd Harmonic
R
L
= 100
71
dBc
typ
C
R
L
500
84
dBc
typ
C
Input Voltage Noise
f > 1MHz
5
5.5
6
6.2
nV/
Hz
max
B
Input Current Noise
f > 1MHz
2.5
3
3.5
3.4
pA/
Hz
max
B
Differential Gain
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150 to V
S
/2
0.06
%
typ
C
Differential Phase
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150 to V
S
/2
0.03
deg
typ
C
DC PERFORMANCE
(4)
Open-Loop Voltage Gain (A
OL
)
V
O
= 0V, R
L
= 100
58
54
52
50
dB
min
A
Input Offset Voltage
V
CM
= 2.5V
1.0
6.5
7.5
9.0
mV
max
A
Average Offset Voltage Drift
V
CM
= 2.5V
10
12
V/
C
max
B
Input Bias Current
V
CM
= 2.5V
+8
+16
+21
+37
A
max
A
Average Bias Current Drift (magnitude)
V
CM
= 2.5V
52
80
nA/
C
max
B
Input Offset Current
V
CM
= 2.5V
0.1
0.7
1.0
1.2
A
max
A
Average Offset Current Drift
V
CM
= 2.5V
0.5
1.0
nA/
C
max
B
INPUT
Least Positive Input Voltage
(5)
1.5
1.6
1.7
1.8
V
min
A
Most Positive Input Voltage
(5)
3.5
3.4
3.3
3.2
V
max
A
Common-Mode Rejection Ratio (CMRR)
V
CM
= 2.5V
59
56
53
52
dB
min
A
Input Impedance
Differential-Mode
92 || 1.4
k
|| pF
typ
C
Common-Mode
2.2 || 1.5
M
|| pF
typ
C
OUTPUT
Most Positive Output Voltage
No Load
4
3.8
3.6
3.5
V
min
A
R
L
= 100
, 2.5V
3.9
3.7
3.5
3.4
V
min
A
Least Positive Output Voltage
No Load
1
1.2
1.4
1.5
V
min
A
R
L
= 100
, 2.5V
1.1
1.3
1.5
1.7
V
min
A
Current Output, Sourcing
+150
+110
+110
+60
mA
min
A
Current Output, Sinking
110
80
70
50
mA
min
A
Closed-Loop Output Impedance
G = +2, f = 100kHz
0.03
typ
C
DISABLE
Disable Low
Power-Down Supply Current (+V
S
)
V
DIS
= 0V, Each Channel
250
A
typ
C
Disable Time
100
ns
typ
C
Enable Time
25
ns
typ
C
Off Isolation
G = +2, 5MHz
65
dB
typ
C
Output Capacitance in Disable
4
pF
typ
C
Turn On Glitch
G = +2, R
L
= 150
, V
IN
= V
S
/2
50
mV
typ
C
Turn Off Glitch
G = +2, R
LP
= 150
, V
IN
= V
S
/2
20
mV
typ
C
Enable Voltage
3.3
3.5
3.6
3.7
V
min
A
Disable Voltage
1.8
1.7
1.6
1.5
V
max
A
Control Pin Input Bias Current
V
DIS
= 0V
100
A
typ
C
POWER SUPPLY
Specified Single Supply Operating Voltage
5
V
typ
C
Maximum Single Supply Operating Voltage
12
12
12
V
max
A
Max Quiescent Current
V
S
= +5V, Each Channel
5.1
6.0
6.0
6.0
mA
max
A
Min Quiescent Current
V
S
= +5V, Each Channel
5.1
4.0
4.0
3.8
mA
min
A
Power Supply Rejection Ratio (+PSRR)
Input Referred
55
dB
typ
C
TEMPERATURE RANGE
Specification: U, E
40 to +85
C
typ
C
Thermal Resistance,
JA
U
SO-16
100
C/W
typ
C
E
SSOP-16
100
C/W
typ
C
NOTES: (1) Test Levels: (A) 100% tested at 25
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25
C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +23
C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node.
V
CM
is the input common-mode voltage. (5) Tested < 3dB below minimum CMR specification at
CMIR limits.
4
OPA3680
PIN CONFIGURATION
Top View
SSOP-16/SO-16
ABSOLUTE MAXIMUM RATINGS
Power Supply ...............................................................................
6.5V
DC
Internal Power Dissipation ................................ See Thermal Information
Differential Input Voltage ..................................................................
1.2V
Input Voltage Range ............................................................................
V
S
Storage Temperature Range: U, E ................................ 40
C to +125
C
Lead Temperature (soldering, 10s) .............................................. +300
C
Junction Temperature (T
J
) ........................................................... +175
C
PACKAGE
DRAWING
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
NUMBER
RANGE
MARKING
NUMBER
(1)
MEDIA
OPA3680E
SSOP-16 Surface Mount
322
40
C to +85
C
OPA3680E
OPA3680E/250
Tape and Reel
"
"
"
"
"
OPA3680E/2K5
Tape and Reel
OPA3680U
SO-16 Surface Mount
265
40
C to +85
C
OPA3680U
OPA3680U
Rails
"
"
"
"
"
OPA3680U/2K5
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of "OPA3680E/2K5" will get a single 2500-piece Tape and Reel.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from perfor-
mance degradation to complete device failure. Burr-Brown Corpo-
ration recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
PACKAGE/ORDERING INFORMATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN A
+IN A
DIS B
IN B
+IN B
DIS C
IN C
+IN C
DIS A
+V
S
OUT A
V
S
OUT B
+V
S
OUT C
V
S
OPA3680
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product
for use in life support devices and/or systems.
5
OPA3680
TYPICAL PERFORMANCE CURVES: V
S
=
5V
At T
A
= +25
C, G = +2, R
F
= 250
, and R
L
= 100
, unless otherwise noted. See Figure 1.
6
3
0
3
6
9
12
15
18
21
24
SMALL-SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
Normalized Gain (3dB/div)
0.5
10
100
500
G = +5
V
O
= 0.5Vp-p
G = +10
G = +2
G = +1
R
F
= 25
15
12
9
6
3
0
3
6
9
12
15
LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
0.5
10
100
500
V
O
= 7Vp-p
V
O
= 1Vp-p
V
O
= 2Vp-p
V
O
= 4Vp-p
Gain (3dB/div)
400
300
200
100
0
100
200
300
400
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
G = +2
V
O
= 0.5Vp-p
+4
+3
+2
+1
0
1
2
3
4
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (1V/div)
G = +2
V
O
= 5Vp-p
2.0
1.6
0.8
0.4
0
6.0
4.0
2.0
0
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
Time (50ns/div)
V
O
(0.4V/div)
V
DIS
(2V/div)
Output Voltage
V
DIS
G = +2
V
IN
= +1V
DISABLED FEEDTHROUGH vs FREQUENCY
45
50
55
60
65
70
75
80
85
90
95
Frequency (MHz)
1
10
100
Feedthrough (5dB/div)
Forward
V
DIS
= 0
Reverse
6
OPA3680
TYPICAL PERFORMANCE CURVES: V
S
=
5V
(Cont.)
At T
A
= +25
C, G = +2, R
F
= 250
, and R
L
= 100
, unless otherwise noted. See Figure 1.
HARMONIC DISTORTION
vs OUTPUT VOLTAGE
50
60
70
80
90
0.1
1
5
Harmonic Distortion (dBc)
Output Voltage (Vp-p)
f = 5MHz
3
rd
Harmonic
2
nd
Harmonic
HARMONIC DISTORTION
vs NON-INVERTING GAIN
V
O
= 2Vp-p
f = 5MHz
3
rd
Harmonic
2
nd
Harmonic
50
60
70
80
90
Harmonic Distortion (dBc)
1
10
Gain Magnitude (V/V)
HARMONIC DISTORTION
vs INVERTING GAIN
V
O
= 2Vp-p
f = 5MHz
3
rd
Harmonic
2
nd
Harmonic
50
60
70
80
90
Harmonic Distortion (dBc)
1
10
Gain Magnitude (V/V)
HARMONIC DISTORTION
vs FREQUENCY
50
60
70
80
90
0.1
1
20
10
Harmonic Distortion (dBc)
Frequency (MHz)
3
rd
Harmonic
2
nd
Harmonic
V
O
= 2Vp-p
HARMONIC DISTORTION
vs LOAD RESISTANCE
50
60
70
80
90
100
10
1000
Harmonic Distortion (dBc)
R
L
(
)
3
rd
Harmonic
2
nd
Harmonic
V
O
= 2Vp-p
f
0
= 5MHz
HARMONIC DISTORTION
vs SUPPLY VOLTAGE
50
60
70
80
90
5
6
7
8
9
10
11
12
Harmonic Distortion (dBc)
Total Supply Voltage (V)
3
rd
Harmonic
2
nd
Harmonic
V
O
= 2Vp-p
f
0
= 5MHz
7
OPA3680
TYPICAL PERFORMANCE CURVES: V
S
=
5V
At T
A
= +25
C, G = +2, R
F
= 250
, and R
L
= 100
, unless otherwise noted. See Figure 1.
70
60
50
40
30
20
10
0
10
20
0
30
60
90
120
150
180
210
240
270
OPEN-LOOP GAIN AND PHASE
Frequency (Hz)
10k
1G
100k
10M
1M
100M
Open-Loop Gain (dB)
Open-Loop Phase (degrees)
Open-Loop Gain
Open-Loop Phase
100
90
80
70
60
50
40
30
20
10
0
CMRR AND PSRR vs FREQUENCY
Frequency (Hz)
10k
100M
100k
1M
10M
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
PSRR
+PSRR
CMRR
12
9
6
3
0
3
6
9
12
15
18
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (20MHz/div)
0
200MHz
100MHz
Gain-to-Capacitive Load (3dB/div)
1/3
OPA3680
R
S
V
IN
V
O
C
L
1k
250
250
250
1k
is optional
Signal Gain = +2
Noise Gain = +3
22pF/32.4
10pF/22.2
47pF/26.7
100pF/20
35
30
25
20
15
10
5
0
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
10
100
R
S
(
)
40
50
60
70
80
90
TWO-TONE, 3rd-ORDER SPURIOUS LEVEL
Single-Tone Load Power (dBm)
8
6
4
2
0
2
4
6
8
10
3rd-Order Spurious Level (dBc)
50MHz
20MHz
10MHz
Load Power at matched 50
load
100
10
1
INPUT VOLTAGE AND CURRENT NOISE DENSITY
Frequency (Hz)
100
1k
10k
100k
1M
10M
Voltage Noise (nV/
Hz)
Current Noise (pA/
Hz)
Voltage Noise
Current Noise
2.5pA/
Hz
4.8nV/
Hz
8
OPA3680
TYPICAL PERFORMANCE CURVES: V
S
=
5V
(Cont.)
At T
A
= +25
C, G = +2, R
F
= 250
, and R
L
= 100
, unless otherwise noted. See Figure 1.
20
30
40
50
60
70
80
90
100
ALL HOSTILE CROSSTALK
Crosstalk (dB)
Frequency (MHz)
0.3
1
10
100
300
10
1
0.1
0.01
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Frequency (Hz)
10k
100M
100k
1M
10M
Output Impedance (
)
1/3
OPA3680
250
+5V
5V
250
200
Z
O
200
150
100
50
0
30
22.5
15
7.5
0
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Ambient Temperature (
C)
40
20
0
20
40
60
80
100
120
140
Output Current (50mA/div)
Supply Current (7.5mA/div)
Quiescent Supply Current
Sourcing Output Current
Sinking Output Current
5
4
3
2
1
0
1
2
3
4
5
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
I
O
(mA)
300
200
100
0
100
200
300
V
O
(Volts)
100
Load Line
50
Load Line
25
Load Line
Output Current Limited
1W Internal
Power Limit
One
Channel
Only
1W Internal
Power Limit
Output Current Limit
15
10
5
0
5
10
15
TYPICAL DC DRIFT OVER TEMPERATURE
Ambient Temperature (
C)
40
20
0
20
40
60
80
100
120
140
Input Offset Voltage (mV)
Input Bias and Offset Current (
A)
I
B
V
IO
I
OS
0.2
0.175
0.15
0.125
0.1
0.075
0.05
0.025
0
COMPOSITE VIDEO dG/dP
Number of 150
Loads
1
2
3
4
d
dG
dG/d
(%/degrees)
1/3
OPA3680
250
250
75
250
Optional
1.3k
Pulldown
Video In
+5V
DIS
5V
Video
Loads
d
dG
No Pulldown
With 1.3k
Pulldown
9
OPA3680
TYPICAL PERFORMANCE CURVES: V
S
= +5V
At T
A
= +25
C, G = +2, R
F
= 250
, and R
L
= 100
to V
S
/2, unless otherwise noted. See Figure 2.
12
9
6
3
0
3
6
9
12
15
18
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Frequency (20MHz/div)
0
200MHz
100MHz
Gain-to-Capacitive Load (3dB/div)
C
L
= 22pF
C
L
= 10pF
Signal Gain = +2
Noise Gain = 3.2
C
L
= 47pF
C
L
= 100pF
1/3
OPA3680
250
250
58
714
250
714
V
I
+5V
0.1
F
V
O
R
S
C
L
0.1
F
70
60
50
40
30
20
10
0
RECOMMENDED R
S
vs CAPACITIVE LOAD
Capacitive Load (pF)
1
10
100
R
S
(
)
Noise Gain = 3.2
4.1
3.7
3.3
2.9
2.5
2.1
1.7
1.3
0.9
LARGE-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (400mV/div)
G = +2
V
O
= 2Vp-p
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
SMALL-SIGNAL PULSE RESPONSE
Time (5ns/div)
Output Voltage (100mV/div)
G = +2
V
O
= 0.5Vp-p
12
9
6
3
0
3
6
9
12
15
18
LARGE-SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
0.5
10
100
500
V
O
= 2Vp-p
V
O
= 0.5Vp-p
V
O
= 1Vp-p
V
O
= 3Vp-p
Gain (3dB/div)
6
3
0
3
6
9
12
15
18
21
24
SMALL-SIGNAL FREQUENCY RESPONSE
Frequency (MHz)
Normalized Gain (3dB/div)
0.5
10
100
500
G = +5
G = +10
G = +2
G = +1
R
F
= 25
V
O
= 0.5Vp-p
10
OPA3680
TYPICAL PERFORMANCE CURVES: V
S
= +5V
(Cont.)
At T
A
= +25
C, G = +2, R
F
= 402
, and R
L
= 100
to V
S
/2, unless otherwise noted. See Figure 2.
TWO-TONE, 3rd-ORDER SPURIOUS LEVEL
3rd-Order Spurious Level (dBc)
P
O
(dBm)
40
50
60
70
80
90
12
14
10
8
6
4
2
0
Load Power at Matched 50
Load
50MHz
20MHz
10MHz
11
OPA3680
APPLICATIONS INFORMATION
WIDEBAND VOLTAGE FEEDBACK OPERATION
The OPA3680 provides an exceptional combination of high
output power capability with a wideband, unity gain stable
voltage feedback op amp using a new high slew rate input
stage. Typical differential input stages used for voltage
feedback op amps are designed to steer a fixed-bias current
to the compensation capacitor, setting a limit to the achiev-
able slew rate. The OPA3680 uses a new input stage which
places the transconductance element between two input
buffers, using their output currents as the forward signal. As
the error voltage increases across the two inputs, an increas-
ing current is delivered to the compensation capacitor. This
provides very high slew rate (1800V/
s) while consuming
relatively low quiescent current (6.4mA). This exceptional
full power performance comes at the price of a slightly
higher input noise voltage than alternative architectures. The
4.8nV/
Hz input voltage noise for the OPA3680 is excep-
tionally low for this type of input stage.
Figure 1 shows the DC-coupled, gain of +2, dual power
supply circuit configuration used as the basis of the
5V
Specifications and Typical Performance Curves. For test
purposes, the input impedance is set to 50
with a resistor to
ground and the output impedance is set to 50
with a series
output resistor. Voltage swings reported in the specifications
are taken directly at the input and output pins, while output
powers (dBm) are at the matched 50
load. For the circuit of
Figure 1, the total effective load will be 100
|| 498
. The
disable control line is typically left open to guarantee normal
amplifier operation. Two optional components are included
in Figure 1. An additional resistor (100
) is included in
series with the non-inverting input. Combined with the 25
DC source resistance looking back towards the signal genera-
tor, this gives an input bias current cancelling resistance that
matches the 125
source resistance seen at the inverting
input (see the DC Accuracy and Offset Control section). In
addition to the usual power supply decoupling capacitors to
ground, a 0.1
F capacitor is included between the two power
supply pins. In practical PC board layouts, this optional-
added capacitor will typically improve the 2nd harmonic
distortion performance by 3dB to 6dB.
Figure 2 shows the AC-coupled, gain of +2, single supply
circuit configuration which is the basis of the +5V Specifi-
cations and Typical Performance Curves. Though not a "rail-
to-rail" design, the OPA3680 requires minimal input and
output voltage headroom compared to other very wideband
voltage feedback op amps. It will deliver a 3Vp-p output
swing on a single +5V supply with >150MHz bandwidth.
The key requirement of broadband single-supply operation is
to maintain input and output signal swings within the useable
voltage ranges at both the input and the output. The circuit
of Figure 2 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 402
resistors).
The input signal is then AC-coupled into the midpoint
voltage bias. The input voltage can swing to within 1.5V of
either supply pin, giving a 2Vp-p input signal range centered
between the supply pins. The input impedance matching
resistor (68
) used for testing is adjusted to give a 50
input
load when the parallel combination of the biasing divider
network is included. Again, an additional resistor (50
in
this case) is included directly in series with the non-inverting
input. This minimum recommended value provides part of
the DC source resistance matching for the non-inverting
input bias current. It is also used to form a simple parasitic
pole to roll off the frequency response at very high frequen-
cies (>500MHz) using the input parasitic capacitance to
form a bandlimiting pole. The gain resistor (R
G
) is AC-
coupled, giving the circuit a DC gain of +1, which puts the
input DC bias voltage (2.5V) at the output as well. The
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifi-
cation and Test Circuit.
FIGURE 2. AC-Coupled, G = +2, Single Supply, Specifica-
tion and Test Circuit.
1/3
OPA3680
+5V
+
DIS
5V
50
Load
50
50
100
V
O
+V
S
V
S
V
I
50
Source
R
G
249
R
F
249
+
6.8
F
0.1
F
6.8
F
0.1
F
0.1
F
1/3
OPA3680
+5V
+V
S
DIS
V
S
/2
402
50
68
100
V
O
V
I
402
R
G
249
R
F
249
0.1
F
0.1
F
+
6.8
F
0.1
F
12
OPA3680
FIGURE 3. Analog Delay Line's Pulse Response.
FIGURE 4. Instrumentation Amplifier.
Delay
for each section
=
+
(
)
=
2
1
2
2
f
RC
,
Time (200ns/div)
Input and Output Voltage (200mV/div)
800
600
400
200
0
200
400
600
800
106ns
Output
Input
output voltage can swing to within 1V of either supply pin
while delivering >100mA output current. A demanding 100
load to a midpoint bias is used in this characterization circuit.
The new output stage circuit used in the OPA3680 can
deliver large bipolar output currents into this midpoint load
with minimal crossover distortion, as shown in the
5V
supply, Harmonic Distortion vs Supply Voltage plot.
ANALOG DELAY LINE
The diagram on the front page of this data sheet shows an
analog delay line using the OPA3680. The first op amp
buffers the delay line from the source, and can be used to
establish the DC operating point if single +5V supply opera-
tion is desired. The last two sections provide an analog delay
function given by Equation 1:
(1)
where, f represents the frequency components of interest in
the input signal. For input frequencies below 0.39/2
=
2.5MHz the delay will be within 15% of the desired value
(2
). The circuit on the front page gives a delay of 50ns per
stage for a total delay of 100ns. Excellent pulse fidelity will
be retained as long as the first 5 harmonics are delayed
equally. For the circuit shown on the front page, the 5th
harmonic should be
2.5MHz/5, which will support a square
wave up to 500kHz, with good pulse response. The input rise
and fall times also need to be
0.30/2.5MHz = 120ns in order
to keep the spectral energy within this 2.5MHz limit. Quicker
rise or fall times will cause propagation delay errors and
excessive pre-shoot.
Shorter delays may be implemented at higher frequencies by
adjusting R and C. To maintain bias current cancellation, it
is best to simply reduce C without changing R.
The 1pF capacitors limit the noise, while maintaining good
pulse response. If desired, these two capacitors may be
removed for circuits that produce less delay.
INSTRUMENTATION DIFFERENTIAL AMPLIFIER
Figure 4 shows an instrumentation differential amplifier
based on the OPA3680. This application benefits from the
OPA3680's DC precision, common-mode rejection, high
impedance input and low current noise. The resistors on the
last (difference) amplifier were selected to keep the loads
equal on the input stage op amps. The matched loads and a
careful PC board layout can improve 2nd harmonic distor-
tion at higher frequencies.
BUFFERED 2 x 1 MULTIPLEXER
Using two of the three channels in an OPA3680 to select one
of two possible input signals, then using the 3rd to isolate the
summing point and drive the load, will give a very flexible,
wideband, multiplexing capability. Figure 5 shows one ex-
ample of this where the two input stages have been set up for
a gain of +2.
Summing the two output signals together at the output stage
buffer's non-inverting input through 400
resistors allows
excellent isolation between the two channels to be main-
tained. When one channel is operating, the other will see an
attenuated version of the active channel's signal on its
inverting node. In this circuit, that signal is attenuated by
20dB at this inactive inverting input--this will keep the
swing low enough on the off channel to avoid parasitic turn
on at that input stage. The desired signal is attenuated by
0.6V/V due to this resistor divider, then recovered by the
gain set in the output stage.
One modification to this circuit would give a high speed
switched gain. The same signal would be fed into both
inputs and each amplifier would be set to a different gain.
1/3
OPA3680
V
1
V
OUT
249
249
499
V
2
124
249
249
124
1/3
OPA3680
1/3
OPA3680
= 2 (V
1
V
2
)
13
OPA3680
FIGURE 5. Buffered 2-to-1 MUX.
FIGURE 6. Triple ADC Driver.
FIGURE 7. Wideband Integrator.
1/3
OPA3680
Video1
Video2
100
100
49.9
49.9
75
402
249
75
100
100
2k
5V
+5V
+5V
374
75
DIS
1/3
OPA3680
2k
402
5V
+5V
DIS
V
DIS
1/3
OPA3680
5V
+5V
DIS
1/3
OPA3680
V
1
249
249
124
24.9
100pF
1/3
OPA3680
V
2
249
249
124
24.9
100pF
1/3
OPA3680
V
3
249
249
124
24.9
100pF
Triple
ADC
V
IN
V
OUT
50
50
1/3
OPA3680
25
1/3
OPA3680
R
50
1/3
OPA3680
75
150
C
TRIPLE ADC DRIVER
Figure 6 shows the OPA3680 driving a triple ADC. Most
ADC's are defined for single +5V operation. The OPA3680
can be adapted to single +5V as well using the techniques
described for Figure 2. The signal flowthrough pinout for the
OPA3680 allows a higher signal fidelity through higher
frequencies due to the simplified PC layout requirements.
WIDEBAND INTEGRATOR
The three unity-gain stable, voltage-feedback amplifiers in
the OPA3680 may be used to develop an exceptional inte-
grator function, as shown in Figure 7. This circuit effectively
multiplies the open-loop gain using two of the amplifiers
and uses the 3rd to provide an input impedance buffering
and low output impedance over broad frequencies required
for proper operation. The interstage attenuator (resistive
divider into the last stage non-inverting input) shown in
Figure 6 is critical to maintaining stability. This circuit can
deliver a 90
phase shift over a 5-decade frequency span.
14
OPA3680
FIGURE 8. State Variable Filter.
BOARD
LITERATURE
PART
REQUEST
PRODUCT
PACKAGE
NUMBER
NUMBER
OPA3680E
16-Lead SSOP
DEM-OPA368xE
MKT-354
OPA3680U
SO-16
DEM-OPA368xU
MKT-364
STATE VARIABLE FILTER
Figure 8 shows a state variable filter using the OPA3680.
This active filter is quite useful for high Q filter responses,
and will produce lowpass, highpass, bandpass, notch and
allpass functions. The filter response is:
(2)
The desired filter frequency response is achieved by the
correct selection of the feed-forward components at the
input.
The resistor R
ISO
isolates the last op amp and the input
driver from capacitive loading problems when
> 0. To
ensure good performance, make sure that:
(3)
where, f
GBP
is the OPA3680's gain bandwidth product
(300MHz).
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
PC boards are available to assist in the initial evaluation of
circuit performance using the OPA3680. They are available
free as an unpopulated PC board delivered with descriptive
documentation. The summary information for the boards is
shown below:
Contact the Burr-Brown Applications support line
(1-800-548-6132) to request this board (ask for the desired
literature number).
MACROMODELS
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. A
SPICE model for the OPA680 is available through either the
Burr-Brown Internet web page (http://www.burr-brown.com).
These models do a good job of predicting small-signal AC
and transient performance under a wide variety of operating
conditions. They do not do as well in predicting the har-
monic distortion, temperature performance or dG/d
charac-
teristics. These models do not attempt to distinguish be-
tween the package types in their small-signal AC perfor-
mance.
V
IN
V
OUT
R/
C
49.9
R
R
R
R
C
Q
P
R
Q
P
R/
Q
P
R/
R
ISO
1/3
OPA3680
1/3
OPA3680
C
49.9
49.9
1/3
OPA3680
P
GBP
P
P
GBP
P
f
Q
Q
f
Q
2
20
1
20
1
>
,
,
V
V
s
s
Q
s
s
Q
RC
OUT
IN
P
P
P
P
P
P
P
=
( )
+
(
)
+
( )
+
+
=
2
2
2
2
1
15
OPA3680
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Since the OPA3680 is a unity-gain stable, voltage-feedback
op amp, a wide range of resistor values may be used for the
feedback and gain setting resistors. The primary limits on
these values are set by dynamic range (noise and distortion)
and parasitic capacitance considerations. For a non-inverting
unity gain follower application, the feedback connection
should be made with a 25
resistor, not a direct short. This
will isolate the inverting input capacitance from the output
pin and improve the frequency response flatness. Usually,
for G > 1 applications, the feedback resistor value should be
between 100
and 1.5k
. Below 100
, the feedback net-
work will present additional output loading which can de-
grade the harmonic distortion performance of the OPA3680.
Above 1.5k
, the typical parasitic capacitance (approxi-
mately 0.2pF) across the feedback resistor may cause unin-
tentional band-limiting in the amplifier response.
A good rule of thumb is to target the parallel combination of
R
F
and R
G
(Figure 1) to be less than approximately 125
.
The combined impedance R
F
|| R
G
interacts with the invert-
ing input capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward response.
Assuming a 3pF total parasitic on the inverting node, hold-
ing R
F
|| R
G
< 125
will keep this pole above 400MHz. By
itself, this constraint implies that the feedback resistor R
F
can increase to several k
at high gains. This is acceptable
as long as the pole formed by R
F
and any parasitic capaci-
tance appearing in parallel with it is kept out of the fre-
quency range of interest.
BANDWIDTH VS GAIN: NON-INVERTING OPERATION
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP by
the non-inverting signal gain (also called the Noise Gain, or
NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90
, as it
does in high gain configurations. At low gains (increased
feedback factors), most amplifiers will exhibit a more com-
plex response with lower phase margin. The OPA3680 is
compensated to give a slightly peaked response in a non-
inverting gain of 2 (Figure 1). This results in a typical gain
of +2 bandwidth of 220MHz, far exceeding that predicted by
dividing the 300MHz GBP by 2. Increasing the gain will
cause the phase margin to approach 90
and the bandwidth
to more closely approach the predicted value of (GBP/NG).
At a gain of +10, the 30MHz bandwidth shown in the
Typical Specifications agrees with that predicted using the
simple formula and the typical GBP of 300MHz.
Frequency response in a gain of +2 may be modified to
achieve exceptional flatness simply by increasing the noise
gain to 2.5. One way to do this, without affecting the +2
signal gain, is to add a 453
resistor across the two inputs
in the circuit of Figure 1. A similar technique may be used
to reduce peaking in unity gain (voltage follower) applica-
FIGURE 9. Gain of 2 Example Circuit.
tions. For example, by using a 250
feedback resistor along
with a 250
resistor across the two op amp inputs, the
voltage follower response will be similar to the gain of +2
response of Figure 2. Further reducing the value of the
resistor across the op amp inputs will further dampen the
frequency response due to increased noise gain.
The OPA3680 exhibits minimal bandwidth reduction going
to single supply (+5V) operation as compared with
5V.
This is because the internal bias control circuitry retains
nearly constant quiescent current as the total supply voltage
between the supply pins is changed.
INVERTING AMPLIFIER OPERATION
Since the OPA3680 is a general purpose, wideband voltage
feedback op amp, all of the familiar op amp application
circuits are available to the designer. Inverting operation is
one of the more common requirements and offers several
performance benefits. Figure 9 shows a typical inverting
configuration where the I/O impedances and signal gain
from Figure 1 are retained in an inverting circuit configura-
tion.
In the inverting configuration, three key design consider-
ation must be noted. The first is that the gain resistor (R
G
)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted pair, long
PC board trace or other transmission line conductor), R
G
may be set equal to the required termination value and R
F
adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise per-
formance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting R
G
to
50
for input matching eliminates the need for R
M
but
requires a 100
feedback resistor. This has the interesting
1/3
OPA3680
50
R
F
250
R
G
124
R
B
95.6
R
M
84.5
Source
DIS
+5V
5V
R
O
50
0.1
F
6.8
F
+
0.1
F
0.1
F
6.8
F
+
50
Load
16
OPA3680
advantage that the noise gain becomes equal to 2 for a 50
source impedance--the same as the non-inverting circuits
considered above. However, the amplifier output will now
see the 100
feedback resistor in parallel with the external
load. In general, the feedback resistor should be limited to
the 100
to 1.5k
range. In this case, it is preferable to
increase both the R
F
and R
G
values as shown in Figure 9 and
then achieve the input matching impedance with a third
resistor (R
M
) to ground. The total input impedance becomes
the parallel combination of R
G
and R
M
.
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence influences the
bandwidth. For the example in Figure 9, the R
M
value
combines in parallel with the external 50
source imped-
ance, yielding an effective driving impedance of 50
||
84.5
= 31.4
. This impedance is added in series with R
G
for calculating the noise gain (NG). The resultant NG is 2.6
for Figure 9, as opposed to only 2 if R
M
could be eliminated
as discussed above. The bandwidth will therefore be slightly
lower for the gain of 2 circuit of Figure 9 than for the gain
of +2 circuit of Figure 1.
The third important consideration in inverting amplifier
design is setting the bias current cancellation resistor on the
non-inverting input (R
B
). If this resistor is set equal to the
total DC resistance looking out of the inverting node, the
output DC error, due to the input bias currents, will be
reduced to (Input Offset Current) R
F
. If the 50
source
impedance is DC-coupled in Figure 9, the total resistance to
ground on the inverting input will be 155
. Combining this
in parallel with the feedback resistor gives the R
B
= 95.6
used in this example. To reduce the additional high fre-
quency noise introduced by this resistor, it is sometimes
bypassed with a capacitor. As long as R
B
< 350
, the
capacitor is not required since the total noise contribution of
all other terms will be less than that of the op amp's input
noise voltage. As a minimum, the OPA3680 requires an R
B
value of 50
to damp out parasitic-induced peaking--a
direct short to ground on the non-inverting input runs the
risk of a very high frequency instability in the input stage.
OUTPUT CURRENT AND VOLTAGE
The OPA3680 provides output voltage and current capabili-
ties that are unsurpassed in a low cost monolithic op amp.
Under no-load conditions at +25
C, the output voltage
typically swings closer than 1V to either supply rail; the
guaranteed swing limit is within 1.2V of either rail. Into a
15
load (the minimum tested load), it is guaranteed to
deliver more than
135mA.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage current, or V-I product,
which is more relevant to circuit operation. Refer to the
"Output Voltage and Current Limitations" plot in the Typi-
cal Performance Curves. The X and Y axes of this graph
show the zero-voltage output current limit and the zero-
current output voltage limit, respectively. The four quad-
rants give a more detailed view of the OPA3680's output
drive capabilities, noting that the graph is bounded by a
"Safe Operating Area" of 1W maximum internal power
dissipation for a single channel. Superimposing resistor load
lines onto the plot shows that the OPA3680 can drive
2.5V
into 25
or
3.5V into 50
without exceeding the output
capabilities or the 1W dissipation limit. A 100
load line
(the standard test circuit load) shows the full
3.9V output
swing capability, as shown in the typical specifications.
The minimum specified output voltage and current specifi-
cations over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold startup will the
output current and voltage decrease to the numbers shown in
the guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
V
BE
's (increasing the available output voltage swing) and
increasing their current gains (increasing the available out-
put current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem since most applications include a series match-
ing resistor at the output that will limit the internal power
dissipation if the output side of this resistor is shorted to
ground. However, shorting the output pin directly to the
adjacent positive power supply pins will, in most cases,
destroy the amplifier. If additional short-circuit protection
is required, consider a small series resistor in the power
supply leads. Under heavy output loads, this will reduce the
available output voltage swing. A 5
series resistor in each
power supply lead will limit the internal power dissipation to
less than 1W for an output short circuit while decreasing the
available output voltage swing only 0.5V for up to 100mA
desired load currents. Always place the 0.1
F power supply
decoupling capacitors after these supply current limiting
resistors directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter--including
additional external capacitance which may be recommended
to improve A/D linearity. A high speed, high open-loop gain
amplifier like the OPA3680 can be very susceptible to
decreased stability and closed-loop response peaking when
a capacitive load is placed directly on the output pin. When
the amplifier's open-loop output resistance is considered,
this capacitive load introduces an additional pole in the
signal path that can decrease the phase margin. Several
external solutions to this problem have been suggested.
When the primary considerations are frequency response
flatness, pulse response fidelity and/or distortion, the sim-
plest and most effective solution is to isolate the capacitive
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive
load. This does not eliminate the pole from the loop
17
OPA3680
FIGURE 11. Op Amp Noise Analysis Model.
FIGURE 10. Capacitive Load Driving with Noise Gain Tuning.
response, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
The Typical Performance Curves show the recommended
R
S
versus capacitive load and the resulting frequency re-
sponse at the load. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the OPA3680.
Long PC board traces, unmatched cables, and connections
to multiple devices can easily exceed this value. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA3680 output
pin (see Board Layout Guidelines).
The criterion for setting this R
S
resistor is a maximum
bandwidth, flat frequency response at the load. For the
OPA3680 operating in a gain of +2, the frequency response
at the output pin is already slightly peaked without the
capacitive load requiring relatively high values of R
S
to
flatten the response at the load. Increasing the noise gain
will reduce the peaking as described previously. The circuit
of Figure 10 demonstrates this technique, allowing lower
values of R
S
to be used for a given capacitive load. This was
used to generate the Recommended R
S
versus Capacitive
Load plots.
This gain of +2 circuit includes a noise gain tuning resistor
across the two inputs to increase the noise gain, increasing
the unloaded phase margin for the op amp. Although this
technique will reduce the required R
S
resistor for a given
capacitive load, it does increase the noise at the output. It
also will decrease the loop gain, slightly decreasing the
distortion performance. If, however, the dominant distortion
mechanism arises from a high R
S
value, significant dynamic
range improvement can be achieved using this technique.
DISTORTION PERFORMANCE
The OPA3680 provides good distortion performance into a
100
load on
5V supplies. Relative to alternative solutions,
it provides exceptional performance into lighter loads and/or
operating on a single +5V supply.
The distortion plots show which changes in operation will
improve distortion. Increasing the load impedance improves
distortion directly. Remember that the total load includes the
feedback network; in the non-inverting configuration
(Figure 1) this is sum of R
F
+ R
G
, while in the inverting
configuration (Figure 9), it is just R
F
. Also, providing an
additional supply decoupling capacitor (0.1
F) between the
supply pins (for bipolar operation) improves the 2nd-order
distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing in-
creases intermodulation distortion directly. The new output
stage used in the OPA3680 actually holds the difference
between fundamental power and the 3rd-order
intermodulation powers relatively constant with increasing
output power until very large output swings are required
(> 4Vp-p). The 3rd-order spurious levels are extremely low
at low output power levels. The output stage continues to
hold them low even as the fundamental power reaches very
high levels. As the Typical Performance Curves show, the
spurious intermodulation powers do not increase as pre-
dicted by a traditional intercept model. As the fundamental
power level increases, the dynamic range does not decrease
significantly. For 2 tones centered at 20MHz, with 10dBm/
tone into a matched 50
load (i.e., 2Vp-p for each tone at
the load, which requires 8Vp-p for the overall two-tone
envelope at the output pin), the Typical Performance Curves
show 57dBc difference between the test tone powers and the
3rd-order intermodulation spurious powers. This excep-
tional performance improves further when operating at lower
frequencies.
NOISE PERFORMANCE
High slew rate, unity gain stable, voltage feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 4.8nV/
Hz input voltage noise for
the OPA3680 is, however, much lower than comparable
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms, combine to give low
output noise under a wide variety of operating conditions.
Figure 11 shows the op amp noise analysis model with all
the noise terms included. In this model, all noise terms are
taken to be noise voltage or current density terms in either
nV/
Hz or pA/
Hz.
1/3
OPA3680
250
50
250
+5V
50
50
C
L
R
NG
V
O
R
S
5V
Power supply decoupling
not shown.
4kT
R
G
R
G
R
F
R
S
1/3
OPA3680
I
BI
E
O
I
BN
4kT = 1.6E 20J
at 290
K
E
RS
E
NI
4kTR
S
4kTR
F
18
OPA3680
FIGURE 12. DC-Coupled, Inverting Gain of 2 with Offset
Adjustment.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 4 shows the general form for the
output noise voltage using the terms shown in Figure 11.
(4)
Dividing this expression by the noise gain (NG = (1+R
F
/R
G
))
will give the equivalent input-referred spot noise voltage at
the non-inverting input, as shown in Equation 5:
(5)
Evaluating these two equations for the OPA3680 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 11nV/
Hz and a total equivalent input
spot noise voltage of 5.5nV/
Hz. This is including the noise
added by the bias current cancellation resistor (100
) on the
non-inverting input. This total input-referred spot noise
voltage is only slightly higher than the 4.8nV/
Hz specifica-
tion for the op amp voltage noise alone. This will be the case
as long as the impedances appearing at each op amp input
are limited to the previously recommend maximum value of
125
. Keeping both (R
F
|| R
G
) and the non-inverting input
source impedance less than 125
will satisfy both noise and
frequency response flatness considerations. Since the resis-
tor-induced noise is relatively negligible, additional capaci-
tive decoupling across the bias current cancellation resistor
(R
B
) for the inverting op amp configuration of Figure 9 is not
required.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power supply current trim for the OPA3680
gives even tighter control than comparable products. Al-
though the high speed input stage does require relatively
high input bias current (typically 14
A out of each input
terminal), the close matching between them may be used to
reduce the output DC error caused by this current. The total
output offset voltage may be considerably reduced by match-
ing the DC source resistances appearing at the two inputs.
This reduces the output DC error due to the input bias
currents to the offset current times the feedback resistor.
Evaluating the configuration of Figure 1, using worst-case
+25
C input offset voltage and current specifications, gives
a worst-case output offset voltage equal to: (NG = non-
inverting signal gain)
(NG V
OS(MAX)
)
(R
F
I
OS(MAX)
)
(6)
=
(2 4.5mV)
(250
0.7
A)
=
9.2mV
A fine scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most of these techniques eventually reduce to adding
a DC current through the feedback resistor. In selecting an
offset trim method, one key consideration is the impact on
the desired signal path frequency response. If the signal path
is intended to be non-inverting, the offset control is best
applied as an inverting summing signal to avoid interaction
with the signal source. If the signal path is intended to be
inverting, applying the offset control to the non-inverting
input may be considered. However, the DC offset voltage on
the summing junction will set up a DC current back into the
source which must be considered. Applying an offset adjust-
ment to the inverting op amp input can change the noise gain
and frequency response flatness. For a DC-coupled inverting
amplifier, Figure 12 shows one example of an offset adjust-
ment technique that has minimal impact on the signal fre-
quency response. In this case, the DC offsetting current is
brought into the inverting input node through resistor values
that are much larger than the signal path resistors. This will
insure that the adjustment circuit has minimal effect on the
loop gain and hence the frequency response.
E
E
I
R
kTR NG
I R
kTR NG
O
NI
BN
S
S
BI
F
F
=
+
(
)
+
(
)
+
(
)
+
2
2
2
2
4
4
R
F
250
200mV Output Adjustment
= = 2
Supply Decoupling
Not Shown
5k
5k
328
0.1
F
R
G
125
V
I
1.25k
10k
0.1
F
5V
+5V
1/3
OPA3680
+5V
5V
V
O
V
O
V
I
R
F
R
G
E
E
I
R
kTR
I R
NG
kTR
NG
N
NI
BN
S
S
BI
F
F
=
+
(
)
+
+
+
2
2
2
4
4
19
OPA3680
FIGURE 13. Simplified Disable Control Circuit.
FIGURE 14. Disable/Enable Glitch.
DISABLE OPERATION
The OPA3680 provides an optional disable feature on each
channel that may be used either to reduce system power or to
impleme nt a simple channel multiplexing operation. If the DIS
control pin of each channel is left unconnected, the OPA3680
will operate normally. To disable, the control pin must be
asserted LOW. Figure 13 shows a simplified internal circuit for
the disable control feature available on each channel.
In normal operation, base current to Q1 is provided through
the 110k
resistor, while the emitter current through the
15k
resistor sets up a voltage drop that is inadequate to turn
on the two diodes in Q1's emitter. As V
DIS
is pulled LOW,
additional current is pulled through the 15k
resistor even-
tually turning on those two diodes (
100uA). At this point,
any further current pulled out of V
DIS
goes through those
diodes holding the emitter-base voltage of Q1 at approxi-
mately zero volts. This shuts off the collector current out of
Q1, turning the amplifier off. The supply current in the
disable mode are only those required to operate the circuit of
Figure 13. Additional circuitry ensures that turn-on time
occurs faster than turn-off time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA3680 is operating in a gain of +1,
this will show a very high impedance at the output and
exceptional signal isolation. If operating at a gain greater than
+1, the total feedback network resistance (R
F
+ R
G
) will
appear as the impedance looking back into the output, but the
circuit will still show very high forward and reverse isolation.
If configured as an inverting amplifier, the input and output
will be connected through the feedback network resistance (R
F
+ R
G
) and the isolation will be very poor as a result.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 14
shows these glitches for the circuit of Figure 1 with the input
signal at 0V. The glitch waveform at the output pin is plotted
along with the DIS pin voltage.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 14, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
DIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 1k
series resistor between the
logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA3680,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
JA
.
The total internal power dissipation (P
D
) is the sum of
quiescent power (P
DQ
) and additional power dissipated in
the output stage (P
DL
) to deliver load power. Quiescent
power is simply the specified no-load supply current times
the total supply voltage across the part. P
DL
will depend on
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition, P
DL
= V
S
2
/(4R
L
)
where R
L
includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA3680E in the circuit of Figure 1 operating at the
maximum specified ambient temperature of +85
C and
driving a grounded 100
load.
P
D
= 10V21mA + 3[5
2
/(4(100
|| 500
))] = 435mW
Maximum T
J
= +85
C + (0.44W100
C/W) = 129
C
40
20
0
20
40
Time (20ns/div)
Output Voltage (20mV/div)
Output Voltage
(0V Input)
V
DIS
0.2V
4.8V
25k
110k
15k
I
S
Control
V
S
+V
S
V
DIS
Q1
20
OPA3680
This worst-case condition is still well within rated maximum
T
J
for this 100
load. Heavier loads may, however, exceed
the 175
C maximum junction temperature rating. Careful
attention to internal power dissipation is required and per-
haps airflow considered under extreme conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA3680 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the non-invert-
ing input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Other-
wise, ground and power planes should be unbroken else-
where on the board.
b) Minimize the distance (< 0.25") from the power supply
pins to high frequency 0.1
F decoupling capacitors. At the
device pins, the ground and power plane layout should not be
in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections should always be decoupled with these capaci-
tors. An optional supply decoupling capacitor (0.1
F) across
the two power supplies (for bipolar operation) will improve
2nd harmonic distortion performance. Larger (2.2
F to 6.8
F)
decoupling capacitors, effective at lower frequency, should
also be used on the main supply pins. These may be placed
somewhat farther from the device and may be shared among
several devices in the same area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA3680. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film or carbon composition axially-
leaded resistors can also provide good high frequency per-
formance. Again, keep their leads and PC board traces as
short as possible. Never use wirewound type resistors in a
high frequency application. Since the output pin and invert-
ing input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as non-inverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resis-
tors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values > 1.5k
,
this parasitic capacitance can add a pole and/or zero below
500MHz that can effect circuit operation. Keep resistor
values as low as possible consistent with load driving con-
siderations. The 250
feedback used in the typical perfor-
mance specifications is a good starting point for design.
Note that a 25
feedback resistor, rather than a direct short,
is suggested for the unity gain follower application. This
effectively isolates the inverting input capacitance from the
output pin that would otherwise cause an additional peaking
in the gain of +1 frequency response.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
S
from the
plot of Recommended R
S
vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an R
S
since the
OPA3680 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an
R
S
are allowed as the signal gain increases (increasing the
unloaded phase margin) If a long trace is required, and the
6dB signal loss intrinsic to a doubly terminated transmission
line is acceptable, implement a matched impedance trans-
mission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline layout
techniques). A 50
environment is normally not necessary
on board, and in fact, a higher impedance environment will
improve distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance defined
(based on board material and trace dimensions), a matching
series resistor into the trace from the output of the OPA3680
is used as well as a terminating shunt resistor at the input of
the destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device;
this total effective impedance should be set to match the
trace impedance. The high output voltage and current capa-
bility of the OPA3680 allows multiple destination devices to
be handled as separate transmission lines, each with their
own series and shunt terminations. If the 6dB attenuation of
a doubly terminated transmission line is unacceptable, a
long trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case and set the
series resistor value as shown in the plot of Recommended
R
S
vs Capacitive Load. This will not preserve signal integ-
rity as well as a doubly terminated line. If the input imped-
ance of the destination device is low, there will be some
signal attenuation due to the voltage divider formed by the
series output into the terminating impedance.
21
OPA3680
FIGURE 15. Internal ESD Protection.
INPUT AND ESD PROTECTION
The OPA3680 is built using a very high speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry devices.
These breakdowns are reflected in the Absolute Maximum
Ratings table. All device pins are protected with internal ESD
protection diodes to the power supplies as shown in Figure
15.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with
15V supply
parts driving into the OPA3680), current-limiting series
resistors should be added into the two inputs. Keep these
resistor values as low as possible since high values degrade
both noise performance and frequency response.
External
Pin
+V
CC
V
CC
Internal
Circuitry
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
OPA3680E/250
OBSOLETE
SSOP
DBQ
16
OPA3680E/2K5
OBSOLETE
SSOP
DBQ
16
OPA3680U
OBSOLETE
SOIC
D
16
OPA3680U/2K5
OBSOLETE
SOIC
D
16
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
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in which TI products or services are used. Information published by TI regarding third-party products or services
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright
2003, Texas Instruments Incorporated
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