OPA3690

SBOS237B MARCH 2002 REVISED OCTOBER 2002

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Triple, Wideband, Voltage-Feedback

OPERATIONAL AMPLIFIER With Disable

FEATURES

FLEXIBLE SUPPLY RANGE:

+5V to +12V Single Supply

2.5V to

6V Dual Supply

WIDEBAND +5V OPERATION: 220MHz (G = +2)

HIGH OUTPUT CURRENT: 190mA

OUTPUT VOLTAGE SWING:

4.0V

HIGH SLEW RATE: 1800V/

LOW SUPPLY CURRENT: 5.5mA/ch

LOW DISABLED CURRENT: 100

A/ch

APPLICATIONS

VIDEO LINE DRIVING

HIGH-SPEED IMAGING CHANNELS

ADC BUFFERS

PORTABLE INSTRUMENTS

TRANSIMPEDANCE AMPLIFIERS

ACTIVE FILTERS

DESCRIPTION

The OPA3690 represents a major step forward in unity-gain
stable, voltage-feedback op amps. A new internal architec-
ture provides slew rate and full-power bandwidth previously
found only in wideband current-feedback op amps. A new
output stage architecture delivers high currents with a mini-
mal headroom requirement. These give exceptional single-
supply operation. Using a single +5V supply, the OPA3690
can deliver a 1V to 4V output swing with over 120mA drive
current and 150MHz bandwidth. This combination of fea-
tures makes the OPA3690 an ideal RGB line driver or single-
supply Analog-to-Digital Converter (ADC) input driver.

The OPA3690's low 5.5mA/ch supply current is precisely
trimmed at +25

C. This trim, along with low temperature

drift, ensures lower maximum supply current than compet-
ing products. System power may be reduced further using
the optional disable control pin. Leaving this disable pin
open, or holding it HIGH, will operate the OPA3690 normal.
If pulled LOW, the OPA3690 supply current drops to less
than 100

A/ch while the output goes into a high impedance

state. This feature may be used for power savings.

OPA3690 RELATED PRODUCTS

SINGLES

DUALS

TRIPLES

Voltage-Feedback

OPA690

OPA2690

Current-Feedback

OPA691

OPA2691

OPA3691

Fixed Gain

OPA692

OPA3692

OPA369

OPA3690

1/3

OPA3690

1/3

OPA3690

OUT

49.9

75.0

49.9

75.0

249

1pF

330pF

1/3

OPA3690

249

1pF

Buffered Analog Delay Line

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

OPA3690

SBOS237B

www.ti.com

Power Supply ...............................................................................

6.5V

Internal Power Dissipation ................................ See Thermal Information
Differential Input Voltage ..................................................................

1.2V

Input Voltage Range ............................................................................

Storage Temperature Range: D, DBQ ........................... 40

C to +125

Lead Temperature (soldering, 10s) .............................................. +300

Junction Temperature (T

) ........................................................... +175

ESD Resistance: HBM .................................................................... 2000V

MM ........................................................................ 200V
CDM ................................................................... 1500V

NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those specified is not implied.

ABSOLUTE MAXIMUM RATINGS

(1)

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.

SPECIFIED

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE-LEAD

DESIGNATOR

(1)

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

OPA3690

SO-16

C to +85

OPA3690

OPA3690ID

Rails, 48

OPA3690IDR

Tape and Reel, 2500

OPA3690

SSOP-16

DBQ

C to +85

OPA3690

OPA3690IDBQT

Tape and Reel, 250

OPA3690IDBQR

Tape and Reel, 2500

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

PACKAGE/ORDERING INFORMATION

PIN CONFIGURATION

Top View

SO, SSOP

IN A

+IN A

DIS B

IN B

+IN B

DIS C

IN C

+IN C

DIS A

OUT A

OUT B

OUT C

OPA3690

OPA3690

SBOS237B

www.ti.com

AC PERFORMANCE (see Figure 1)

Small-Signal Bandwidth

G = +1, V

= 0.5Vp-p, R

= 25

500

MHz

typ

G = +2, V

= 0.5Vp-p

220

165

160

150

MHz

min

G = +10, V

= 0.5Vp-p

MHz

min

Gain Bandwidth Product

300

200

190

180

MHz

min

Bandwidth for 0.1dB Gain Flatness

G = +2, V

< 0.5Vp-p

MHz

typ

Peaking at a Gain of +1

< 0.5Vp-p

typ

Large-Signal Bandwidth

G = +2, V

= 5Vp-p

200

MHz

typ

Slew Rate

G = +2, 4V Step

1800

1400

1200

500

min

Rise-and-Fall Time

G = +2, V

= 0.5V Step

1.4

max

G = +2, V

= 4V Step

2.8

max

Settling Time to 0.02%

G = +2, V

= 2V Step

typ

0.1%

G = +2, V

= 2V Step

typ

Harmonic Distortion

G = +2, f = 5MHz, V

= 2Vp-p

2nd-Harmonic

= 100

dBc

typ

500

dBc

typ

3rd-Harmonic

= 100

dBc

typ

500

dBc

typ

Crosstalk

Input Referred, f = 5MHz, All Hostile

dBc

typ

Input Voltage Noise

f > 1MHz

5.5

nV/

typ

Input Current Noise

f > 1MHz

3.1

pA/

typ

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.06

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.01

deg

typ

DC PERFORMANCE

(4)

Open-Loop Voltage Gain (A

)

= 0V, R

= 100

min

Input Offset Voltage

= 0V

1.0

4.5

5.2

max

Average Offset Voltage Drift

= 0V

max

Input Bias Current

= 0V

max

Average Bias Current Drift (magnitude)

= 0V

nA/

max

Input Offset Current

= 0V

0.1

1.0

1.4

1.6

max

Average Offset Current Drift

= 0V

max

INPUT

Common-Mode Input Range (CMIR)

(5)

3.5

3.4

3.3

3.2

min

Common-Mode Rejection Ratio (CMRR)

1.0V

min

Input Impedance

Differential Mode

190 || 0.6

|| pF

typ

Common-Mode

3.2 || 0.9

|| pF

typ

OUTPUT

Voltage Output Swing

No Load

4.0

3.8

3.7

3.6

min

100

Load

3.9

3.7

3.6

3.3

min

Current Output, Sourcing

= 0

+190

+160

+140

+100

min

Sinking

= 0

190

160

140

100

min

Short-Circuit Current

= 0

250

typ

Closed-Loop Output Impedance

G = +2, f = 100kHz

0.04

typ

ELECTRICAL CHARACTERISTICS:

Boldface limits are tested at +25

= 402

, R

= 100

G = +2, (see Figure 1 for AC performance only), and R

= 25

for G = +1, unless otherwise noted.

OPA3690ID, IDBQ

TYP

MIN/MAX OVER TEMPERATURE

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

NOTES: (1) Junction temperature = ambient for 25

C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = Ambient

+20

C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at 25

C. Over temperature limits by characterization and

simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V

is the input

common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at

CMIR limits.

OPA3690

SBOS237B

www.ti.com

ELECTRICAL CHARACTERISTICS:

5V (Cont.)

Boldface limits are tested at +25

= 402

, R

= 100

G = +2, (see Figure 1 for AC performance only), and R

= 25

for G = +1, unless otherwise noted.

OPA3690ID, IDBQ

TYP

MIN/MAX OVER TEMPERATURE

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

DISABLE

Disable Low

Power-Down Supply Current (+V

)

DIS

= 0V, All Channels

300

600

720

780

max

Disable Time

= 1V

200

typ

Enable Time

= 1V

typ

Off Isolation

G = +2, 5MHz

typ

Output Capacitance in Disable

typ

Turn-On Glitch

G = +2, R

= 150

, V

= 0

typ

Turn-Off Glitch

G = +2, R

= 150

, V

= 0

typ

Enable Voltage

3.3

3.5

3.6

3.7

min

Disable Voltage

1.8

1.7

1.6

1.5

max

Control Pin Input Bias Current

DIS

= 0V, Each Channel

130

150

160

max

POWER SUPPLY

Specified Operating Voltage

typ

Maximum Operating Voltage Range

max

Max Quiescent Current (3 Channels)

16.5

17.4

18.6

max

Min Quiescent Current (3 Channels)

16.5

15.9

15.3

14.1

min

Power-Supply Rejection Ratio (+PSRR)

Input Referred

min

TEMPERATURE RANGE

Specification: D, DB

40 to +85

typ

Thermal Resistance,

SO-16

100

C/W

typ

DBQ

SSOP-16

100

C/W

typ

NOTES: (1) Junction temperature = ambient for +25

C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = Ambient

+20

C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25

C. Over-temperature limits by characterization and

simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V

is the input

common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at

CMIR limits.

OPA3690

SBOS237B

www.ti.com

AC PERFORMANCE (see Figure 2)

Small-Signal Bandwidth

G = +1, V

< 0.5Vp-p

400

MHz

typ

G = +2, V

< 0.5Vp-p

190

150

145

140

MHz

min

G = +10, V

< 0.5Vp-p

MHz

min

Gain Bandwidth Product

250

180

170

160

MHz

min

Bandwidth for 0.1dB Gain Flatness

G = +2, V

< 0.5Vp-p

MHz

typ

Peaking at a Gain of +1

< 0.5Vp-p

typ

Large-Signal Bandwidth

G = +2, V

= 2Vp-p

220

MHz

typ

Slew Rate

G = +2, 2V Step

1000

700

670

550

min

Rise Time

G = +2, V

= 0.5V Step

1.6

typ

Fall Time

G = +2, V

= 2V Step

2.0

typ

Settling Time to 0.02%

G = +2, V

= 2V Step

typ

0.1%

G = +2, V

= 2V Step

typ

Harmonic Distortion

G = +2, f = 5MHz, V

= 2Vp-p

2nd-Harmonic

= 100

dBc

typ

500

dBc

typ

3rd-Harmonic

= 100

dBc

typ

500

dBc

typ

Input Voltage Noise

f > 1MHz

5.6

nV/

typ

Input Current Noise

f > 1MHz

3.2

pA/

typ

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150 to V

0.06

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150 to V

0.02

deg

typ

DC PERFORMANCE

(4)

Open-Loop Voltage Gain (A

)

= 0V, R

= 100

min

Input Offset Voltage

= 2.5V

1.0

4.5

4.8

5.2

max

Average Offset Voltage Drift

= 2.5V

max

Input Bias Current

= 2.5V

max

Average Bias Current Drift (magnitude)

= 2.5V

nA/

max

Input Offset Current

= 2.5V

0.3

1.4

1.6

max

Average Offset Current Drift

= 2.5V

nA/

max

INPUT

Least Positive Input Voltage

(5)

1.5

1.6

1.7

1.8

min

Most Positive Input Voltage

(5)

3.5

3.4

3.3

3.2

max

Common-Mode Rejection Ratio (CMRR)

= 2.5V

min

Input Impedance

Differential Mode

92 || 1.4

|| pF

typ

Common-Mode

2.2 || 1.5

|| pF

typ

OUTPUT

Most Positive Output Voltage

No Load

3.8

3.6

3.5

min

= 100

, 2.5V

3.9

3.7

3.5

3.4

min

Least Positive Output Voltage

No Load

1.2

1.4

1.5

min

= 100

, 2.5V

1.1

1.3

1.5

1.7

min

Current Output, Sourcing

+160

+120

+100

+80

min

Sinking

160

120

100

min

Short-Circuit Current

= V

250

typ

Closed-Loop Output Impedance

G = +2, f = 100kHz

0.04

typ

ELECTRICAL CHARACTERISTICS:

= +5V

Boldface limits are tested at +25

= 402

, R

= 100

to V

G = +2, (see Figure 2 for AC performance only), and R

= 25

for G = +1, unless otherwise noted.

OPA3690ID, IDBQ

TYP

MIN/MAX OVER TEMPERATURE

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

NOTES: (1) Junction temperature = ambient for 25

C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = Ambient

+20

C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at 25

C. Over temperature limits by characterization and

simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V

is the input

common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at

CMIR limits.

OPA3690

SBOS237B

www.ti.com

ELECTRICAL CHARACTERISTICS:

= +5V (Cont.)

Boldface limits are tested at +25

= 402

, R

= 100

to V

G = +2, (see Figure 2 for AC performance only), and R

= 25

for G = +1, unless otherwise noted.

OPA3690ID, IDBQ

TYP

MIN/MAX OVER TEMPERATURE

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

NOTES: (1) Junction temperature = ambient for +25

C specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = Ambient

+20

C at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25

C. Over-temperature limits by characterization and

simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V

is the input

common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at

CMIR limits.

DISABLE

Disable Low

Power-Down Supply Current (+V

)

DIS

= 0V, All Channels

300

600

720

780

max

Off Isolation

G = +2, 5MHz

typ

Output Capacitance in Disable

typ

Turn-On Glitch

G = +2, R

= 150

, V

= V

typ

Turn-Off Glitch

G = +2, R

= 150

, V

= V

typ

Enable Voltage

3.3

3.5

3.6

3.7

min

Disable Voltage

1.8

1.7

1.6

1.5

max

Control Pin Input Bias Current

DIS

= 0V, Each Channel

130

150

160

typ

POWER SUPPLY

Specified Single-Supply Operating Voltage

typ

Maximum Single-Supply Operating Voltage

max

Max Quiescent Current (3 Channels)

= +5V

14.7

15.6

16.2

16.8

max

Min Quiescent Current (3 Channels)

= +5V

14.7

14.1

13.2

12.0

min

Power-Supply Rejection Ratio (+PSRR)

Input Referred

typ

TEMPERATURE RANGE

Specification: D, DBQ

40 to +85

typ

Thermal Resistance,

SO-16

100

C/W

typ

DBQ

SSOP-16

100

C/W

typ

OPA3690

SBOS237B

www.ti.com

TYPICAL CHARACTERISTICS: V

At T

= +25

C, G = +2, R

= 402

, and R

= 100

(see Figure 1 for AC performance only), unless otherwise noted.

SMALL-SIGNAL FREQUENCY RESPONSE

Normalized Gain (3dB/div)

Frequency (MHz)

0.7

100

700

= 0.5Vp-p

G = +1

= 25

G = 2

G = 5

G = 10

LARGE-SIGNAL FREQUENCY RESPONSE

0.5

100

500

Frequency (MHz)

Gain (3dB/div)

= 4Vp-p

= 7Vp-p

= 2Vp-p

= 1Vp-p

SMALL-SIGNAL PULSE RESPONSE

Time (5ns/div)

400

300

200

100

200

300

400

G = +2

= 0.5Vp-p

Output V

oltage (100mV/div)

LARGE-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output V

oltage (1V/div)

G = +2

= 5Vp-p

COMPOSITE VIDEO dG/dP

dG/dP (%/degree)

Number of 150

Loads

0.2

0.175

0.15

0.125

0.1

0.075

0.05

0.025

No Pull-Down
With 1.3k

Pull-Down

1/3

OPA3690

402

+5V

Video In

402

Optional
1.3k

Pull-Down

ALL HOSTILE CROSSTALK

Frequency (MHz)

Crosstalk (5dB/div)

Input Referred

0.1

100

OPA3690

SBOS237B

www.ti.com

TYPICAL CHARACTERISTICS: V

(Cont.)

At T

= +25

C, G = +2, R

= 402

, and R

= 100

(see Figure 1 for AC performance only), unless otherwise noted.

HARMONIC DISTORTION vs LOAD RESISTANCE

Harmonic Distortion (dBc)

Resistance (

)

100

1000

= 2Vp-p

f = 5MHz

3rd-Harmonic

2nd-Harmonic

5MHz HARMONIC DISTORTION

vs SUPPLY VOLTAGE

Harmonic Distortion (dBc)

Supply Voltage (

)

2.5

3.5

4.5

5.5

3rd-Harmonic

2nd-Harmonic

= 2Vp-p

= 100

f = 5MHz

HARMONIC DISTORTION vs FREQUENCY

Harmonic Distortion (dBc)

Frequency (MHz)

0.1

100

= 2Vp-p

= 100

2nd-Harmonic

3rd-Harmonic

HARMONIC DISTORTION vs OUTPUT VOLTAGE

Harmonic Distortion (dBc)

Output Voltage Swing (Vp-p)

0.1

= 100

f = 5MHz

3rd-Harmonic

2nd-Harmonic

HARMONIC DISTORTION vs NONINVERTING GAIN

Harmonic Distortion (dBc)

Noninverting Gain (V/V)

3rd-Harmonic

2nd-Harmonic

= 2Vp-p

= 100

f = 5MHz

HARMONIC DISTORTION vs INVERTING GAIN

Harmonic Distortion (dBc)

Inverting Gain (V/V)

= 2Vp-p

= 100

f = 5MHz

3rd-Harmonic

2nd-Harmonic

OPA3690

SBOS237B

www.ti.com

TYPICAL CHARACTERISTICS: V

(Cont.)

At T

= +25

C, G = +2, R

= 402

, and R

= 100

(see Figure 1 for AC performance only), unless otherwise noted.

INPUT VOLTAGE AND CURRENT NOISE DENSITY

Current Noise (pA/

Hz)

Voltage Noise (nV/

Hz)

Frequency (Hz)

100

100k

10k

10M

100

Voltage Noise 5.5nV/

Current Noise 3.1pA/

2-TONE, 3RD-ORDER

INTERMODULATION SPURIOUS

3rd-Order Spurious Level (dBc)

Single-Tone Load Power (dBm)

20MHz

10MHz

50MHz

Load Power at Matched 50

Load,

see Figure 1

RECOMMENDED R

vs CAPACITIVE LOAD

(

)

Capacitive Load (pF)

100

1000

FREQUENCY RESPONSE vs CAPACITIVE LOAD

Gain-to-Capacitive Load (dB)

Frequency (20MHz/div)

100

120

140

160

180

200

402

OUT

1/3

OPA3690

is optional.

= 22pF

= 47pF

= 100pF

= 10pF

G = +2

LARGE-SIGNAL DISABLE/ENABLE RESPONSE

Time (50ns/div)

Output V

oltage (0.4V/div)

2.0

1.6

1.2

0.8

0.4

DIS

(2V/div)

G = +2

= +1V

DIS

Output Voltage

DISABLE FEEDTHROUGH vs FREQUENCY

Frequency (Hz)

Feedthrough (5dB/div)

Forward

Reverse

DIS

= 0

100k

10M

100M

OPA3690

SBOS237B

www.ti.com

TYPICAL CHARACTERISTICS: V

(Cont.)

At T

= +25

C, G = +2, R

= 402

, and R

= 100

(see Figure 1 for AC performance only), unless otherwise noted.

OUTPUT VOLTAGE AND CURRENT LIMITATIONS

(V)

(mA)

300

200

100

200

300

Output Current Limited

1W Internal

Power Limit

One Channel

Only

1W Internal

Power Limit

One Channel Only

Output Current Limit

100

Load Line

TYPICAL DC DRIFT OVER TEMPERATURE

Input Offset Voltage (mV)

Input Bias and Offset Currents (

Ambient Temperature (

100

125

1.5

0.5

1.5

Input Offset Current (I

)

Input Offset Voltage (V

)

Input Bias Current (I

)

COMMON-MODE REJECTION RATIO AND

POWER-SUPPLY REJECTION RATIO vs FREQUENCY

Power-Supply Rejection Ratio (dB)

Common-Mode Rejection Ratio (dB)

Frequency (MHz)

10k

100k

10M

100M

100

CMRR

+PSRR

PSRR

SUPPLY AND OUTPUT CURRENT vs TEMPERATURE

Supply Current (2mA/div)

Output Current (50mA/div)

Ambient Temperature (

100

125

250

200

150

100

Sourcing Output Current

Sinking Output Current

Quiescent Supply Current

CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY

Output Impedance (

)

Frequency (Hz)

10k

100k

10M

100M

0.1

0.01

1/3

OPA3690

402

+5V

200

402

OPEN-LOOP GAIN AND PHASE

Open-Loop Gain (dB)

Frequency (MHz)

100k

10k

10M

100M

Open-Loop Phase (

)

120

150

180

210

240

270

Open-Loop Gain

Open-Loop Phase

OPA3690

SBOS237B

www.ti.com

TYPICAL CHARACTERISTICS: V

= +5V

At T

= +25

C, G = +2, R

= 402

, and R

= 100

(see Figure 2 for AC performance only), unless otherwise noted.

SMALL-SIGNAL FREQUENCY RESPONSE

Normalized Gain (3dB/div)

Frequency (Hz)

0.7 1

700

100

G = +1

= 25

G = +2

G = +5

G = +10

= 0.5Vp-p

LARGE-SIGNAL FREQUENCY RESPONSE

Gain (3dB/div)

Frequency (MHz)

0.5

500

100

= 2Vp-p

= 3Vp-p

= 1Vp-p

SMALL-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output V

oltage (100mV/div)

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

G = +2

= 0.5Vp-p

LARGE-SIGNAL PULSE RESPONSE

Time (5ns/div)

Output V

oltage (400mV/div)

4.1

3.7

3.3

2.9

2.5

2.1

1.7

1.3

0.9

G = +2

= 2Vp-p

RECOMMENDED R

vs CAPACITIVE LOAD

(

)

Capacitive Load (pF)

100

1000

FREQUENCY RESPONSE vs CAPACITIVE LOAD

Gain-to-Capacitive Load (dB)

Frequency (20MHz/div)

100

120

140

160

180

200

= 22pF

= 47pF

= 100pF

= 10pF

402

714

0.1

714

402

+5V

OUT

1/3

OPA3690

OPA3690

SBOS237B

www.ti.com

APPLICATIONS INFORMATION

WIDEBAND VOLTAGE-FEEDBACK OPERATION

The OPA3690 provides an exceptional combination of high
output power capability with a wideband, unity-gain stable,
voltage-feedback op amp using a new high slew rate input
stage. Typical differential input stages used for voltage-
feedback op amps are designed to steer a fixed-bias current
to the compensation capacitor, setting a limit to the achiev-
able slew rate. The OPA3690 uses a new input stage which
places the transconductance element between two input
buffers, using their output currents as the forward signal. As
the error voltage increases across the two inputs, an increas-
ing current is delivered to the compensation capacitor. This
provides very high slew rate (1800V/

s) while consuming

relatively low quiescent current (5.5mA). This exceptional
full-power performance comes at the price of a slightly higher
input noise voltage than alternative architectures. The 5.5nV/

input voltage noise for the OPA3690 is exceptionally low for
this type of input stage.

Figure 1 shows the DC-coupled, gain of +2, dual power-
supply circuit configuration used as the basis of the

Electrical and Typical Characteristics. For test purposes, the
input impedance is set to 50

with a resistor to ground and

the output impedance is set to 50

with a series output

resistor. Voltage swings reported in the Electrical Character-
istics are taken directly at the input and output pins, while
output powers (dBm) are at the matched 50

load. For the

circuit of Figure 1, the total effective load will be 100

|| 804

The disable control line is typically left open to ensure normal
amplifier operation. Two optional components are included in
Figure 1. An additional resistor (100

) is included in series

with the noninverting input. Combined with the 25

source resistance looking back towards the signal generator,
this gives an input bias current cancelling resistance that

matches the 125

source resistance seen at the inverting

input (see the DC Accuracy and Offset Control section). In
addition to the usual power-supply decoupling capacitors to
ground, a 0.1

F capacitor is included between the two power-

supply pins. In practical PC board layouts, this optional-added
capacitor will typically improve the 2nd-harmonic distortion
performance by 3dB to 6dB.

Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration which is the basis of the +5V Electrical
and Typical Characteristics. Though not a "rail-to-rail" design,
the OPA3690 requires minimal input and output voltage
headroom compared to other very wideband voltage- feed-
back op amps. It will deliver a 3Vp-p output swing on a single
+5V supply with > 150MHz bandwidth. The key requirement
of broadband single-supply operation is to maintain input and
output signal swings within the useable voltage ranges at
both the input and the output. The circuit of Figure 2 estab-
lishes an input midpoint bias using a simple resistive divider
from the +5V supply (two 698

resistors). The input signal is

then AC-coupled into the midpoint voltage bias. The input
voltage can swing to within 1.5V of either supply pin, giving
a 2Vp-p input signal range centered between the supply pins.
The input impedance matching resistor (59

) used for testing

is adjusted to give a 50

input load when the parallel

combination of the biasing divider network is included. Again,
an additional resistor (50

in this case) is included directly in

series with the noninverting input. This minimum recom-
mended value provides part of the DC source resistance
matching for the noninverting input bias current. It is also
used to form a simple parasitic pole to roll off the frequency
response at very high frequencies (> 500MHz) using the input
parasitic capacitance to form a bandlimiting pole. The gain
resistor (R

) is AC-coupled, giving the circuit a DC gain of +1,

which puts the input DC bias voltage (2.5V) at the output as
well. The output voltage can swing to within 1V of either

1/3

OPA3690

+5V

DIS

Load

175

Source

402

6.8

0.1

6.8

0.1

FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specifica-

tion and Test Circuit.

FIGURE 2. AC-Coupled, G = +2, Single-Supply, Specifica-

tion and Test Circuit.

1/3

OPA3690

+5V

DIS

698

100

698

402

0.1

6.8

0.1

OPA3690

SBOS237B

www.ti.com

supply pin while delivering > 100mA output current. A de-
manding 100

load to a midpoint bias is used in this charac-

terization circuit. The new output stage circuit used in the
OPA3690 can deliver large bipolar output currents into this
midpoint load with minimal crossover distortion, as shown in
the

5V supply "Harmonic Distortion vs Supply Voltage" plot.

SINGLE-SUPPLY ADC INTERFACE

Most modern, high-performance ADCs (such as the ADS8xx
and ADS9xx series from Texas Instruments) operate on a
single +5V (or lower) power supply. It has been a consider-
able challenge for single-supply op amps to deliver a low
distortion input signal at the ADC input for signal frequencies
exceeding 5MHz. The high slew rate, exceptional output
swing, and high linearity of the OPA3690 make it an ideal
single-supply ADC driver. The circuit on the front page shows
one possible interface particularly suited to differential I/O,
AC-coupled requirements. Figure 3 shows the AC-coupled
test circuit of Figure 2 modified for a capacitive (ADC) load
and with an optional output pull-down resistor (R

). This

circuit would be suitable to dual-channel ADC driving with a
single-ended I/O.

The OPA3690 in the circuit of Figure 3 provides > 200MHz
bandwidth for a 2Vp-p output swing. Minimal 3rd-harmonic
distortion or 2-tone, 3rd-order intermodulation distortion will be
observed due to the very low crossover distortion in the
OPA3690 output stage. The limit of output Spurious-Free
Dynamic Range (SFDR) will be set by the 2nd-harmonic
distortion. Without R

, the circuit of Figure 3 measured at

10MHz shows an SFDR of 57dBc. This may be improved by
pulling additional DC bias current (I

) out of the output stage

through the optional R

resistor to ground (the output midpoint

is at 2.5V for Figure 3). Adjusting I

gives the improvement in

SFDR shown in Figure 4. SFDR improvement is achieved for
I

values up to 5mA, with worse performance for higher

values. Using the dual OPA3690 in an I/Q receiver channel will
give matched AC performance through high frequencies.

ANALOG DELAY LINE

The diagram on the front page of this data sheet shows an
analog delay line using the OPA3690. The first op amp

1/3

OPA3690

402

1Vp-p

698

+5V

0.1

50pF

0.1

2.5V DC

1V AC

ADC Input

Power-supply decoupling not shown.

FIGURE 3. Single-Supply ADC Input Driver. One of three channels.

buffers the delay line from the source, and can be used to
establish the DC operating point if single +5V supply opera-
tion is desired. The last two sections provide an analog delay
function given by Equation 1:

Delay

for each

tion

(

)

sec

where, f represents the frequency components of interest in
the input signal. For input frequencies below 0.39/2

2.5MHz, the delay will be within 15% of the desired value (2

The circuit on the front page gives a delay of 50ns per stage
for a total delay of 100ns. Excellent pulse fidelity will be
retained as long as the first 5 harmonics are delayed equally.
For the circuit shown on the front page, the 5th-harmonic
should be

2.5MHz/5, which will support a square wave up to

500kHz, with good pulse response. The input rise-and-fall
times also need to be

0.30/2.5MHz = 120ns in order to keep

the spectral energy within this 2.5MHz limit. Quicker rise or fall
times will cause propagation delay errors and excessive pre-
shoot.

Output Pull-Down Current (mA)

SFDR (dBc)

= 2Vp-p, 10MHz

FIGURE 4. SFDR vs I

(1)

OPA3690

SBOS237B

www.ti.com

Shorter delays may be implemented at higher frequencies by
adjusting R and C. To maintain bias current cancellation, it is
best to simply reduce C without changing R. The analog
delay line's pulse response is shown in Figure 5.

The 1pF capacitors limit the noise, while maintaining good
pulse response. If desired, these two capacitors may be
removed for circuits that produce less delay.

FIGURE 5. Analog Delay Line's Pulse Response.

Frequency (MHz)

100

400

Gain (dB)

FIGURE 7. Frequency Response for the OPA3690 as an

Instrumentation Amplifier.

INSTRUMENTATION DIFFERENTIAL AMPLIFIER

Figure 6 shows an instrumentation differential amplifier based
on the OPA3690. This application benefits from the
OPA3690's DC precision, common-mode rejection, high im-
pedance input, and low-current noise. The resistors on the
last (difference) amplifier were selected to keep the loads
equal on the input stage op amps. The matched loads and a
careful PC board layout can improve 2nd-harmonic distortion
at higher frequencies. Figure 7 shows the frequency re-
sponse of the instrumentation differential amplifier.

In applications where current-feedback amplifiers or fixed-
gain amplifiers can be used, the OPA3691 or OPA3692 will
provide wider bandwidth instrumentation amplifiers.

BUFFERED 2 x 1 MULTIPLEXER

Using two of the three channels in an OPA3690 to select one
of two possible input signals, then using the 3rd to isolate the
summing point and drive the load, will give a very flexible,
wideband, multiplexing capability. Figure 8 shows one ex-
ample of this where the two input stages have been set up
for a gain of +2.

1/3

OPA3690

OUT

402

806

200

402

200

1/3

OPA3690

1/3

OPA3690

OUT

= 2 (V

)

FIGURE 6. Instrumentation Amplifier.

FIGURE 8. Buffered 2-to-1 MUX.

1/3

OPA3690

Video 1

Video 2

100

49.9

402

249

100

+5V

374

DIS

1/3

OPA3690

402

+5V

DIS

1/3

OPA3690

+5V

DIS

Time (200ns/div)

Input and Output Voltage (200mV/div)

800

600

400

200

400

600

800

106ns

Output

Input

OPA3690

SBOS237B

www.ti.com

Summing the two output signals together at the output stage
buffer's noninverting input through 400

resistors allows

excellent isolation between the two channels to be main-
tained. When one channel is operating, the other will see an
attenuated version of the active channel's signal on its
inverting node. In this circuit, that signal is attenuated by
20dB at this inactive inverting input--this will keep the swing
low enough on the off channel to avoid parasitic turn-on at
that input stage. The desired signal is attenuated by 0.6V/V
due to this resistor divider, then recovered by the gain set in
the output stage.

One modification to this circuit would give a high-speed
switched gain. The same signal would be fed into both inputs
and each amplifier would be set to a different gain.

TRIPLE ADC DRIVER

Figure 9 shows the OPA3690 driving a triple ADC. Most
ADCs are defined for single +5V operation. The OPA3690
can be adapted to single +5V as well, using the techniques
described for Figure 2. The signal flowthrough pinout for the
OPA3690 allows a higher signal fidelity through higher fre-
quencies due to the simplified PC layout requirements.

WIDEBAND INTEGRATOR

The three unity-gain stable, voltage-feedback amplifiers in
the OPA3690 may be used to develop an exceptional inte-
grator function, as shown in Figure 10. This circuit effectively
multiplies the open-loop gain using two of the amplifiers and
uses the 3rd to provide an input impedance buffering and low

output impedance over broad frequencies required for proper
operation. The interstage attenuator (resistive divider into the
last stage noninverting input) shown in Figure 9 is critical to
maintaining stability. This circuit can deliver a 90

phase shift

over a 5-decade frequency span.

STATE VARIABLE FILTER

Figure 11 shows a state variable filter using the OPA3690.
This active filter is quite useful for high Q filter responses,

1/3

OPA3690

402

200

24.9

100pF

1/3

OPA3690

402

200

24.9

100pF

1/3

OPA3690

402

200

24.9

100pF

Triple

ADC

OUT

1/3

OPA3690

1/3

OPA3690

1/3

OPA3690

150

OUT

49.9

ISO

1/3

OPA3690

1/3

OPA3690

49.9

1/3

OPA3690

FIGURE 11. State Variable Filter.

FIGURE 9. Triple ADC Driver.

FIGURE 10. Wideband Integrator.

OPA3690

SBOS237B

www.ti.com

and will produce low-pass, high-pass, bandpass, notch, and
all-pass functions. The filter response is:

OUT

(

)

( )

The desired filter frequency response is achieved by the
correct selection of the feed-forward components at the
input.

The resistor R

ISO

isolates the last op amp and the input driver

from capacitive loading problems when

> 0. To ensure

good performance, make sure that:

GBP

where, f

GBP

is the OPA3690's gain bandwidth product

(300MHz).

DESIGN-IN TOOLS

DEMONSTRATION BOARDS

PC boards are available to assist in the initial evaluation of
circuit performance using the OPA3690. They are available,
free, as an unpopulated PC board delivered with descriptive
documentation. The summary information for the boards is
shown below:

OPERATING SUGGESTIONS

OPTIMIZING RESISTOR VALUES

Since the OPA3690 is a unity-gain stable, voltage-feedback
op amp, a wide range of resistor values may be used for the
feedback and gain setting resistors. The primary limits on
these values are set by dynamic range (noise and distortion)
and parasitic capacitance considerations. For a noninverting
unity-gain follower application, the feedback connection should
be made with a 25

resistor, not a direct short. This will

isolate the inverting input capacitance from the output pin
and improve the frequency response flatness. Usually, for
G > 1 applications, the feedback resistor value should be
between 100

and 1.5k

. Below 100

, the feedback net-

work will present additional output loading which can de-
grade the harmonic distortion performance of the OPA3690.
Above 1.5k

, the typical parasitic capacitance (approxi-

mately 0.2pF) across the feedback resistor may cause unin-
tentional band-limiting in the amplifier response.

A good rule of thumb is to target the parallel combination of
R

and R

(see Figure 1) to be less than approximately

125

. The combined impedance (R

|| R

) interacts with the

inverting input capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward response.
Assuming a 3pF total parasitic on the inverting node, holding
R

|| R

< 125

will keep this pole above 400MHz. By itself,

this constraint implies that the feedback resistor R

can

increase to several k

at high gains. This is acceptable as

long as the pole formed by R

and any parasitic capacitance

appearing in parallel with it is kept out of the frequency range
of interest.

BANDWIDTH VERSUS GAIN: NONINVERTING
OPERATION

Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP by
the noninverting signal gain (also called the Noise Gain, or
NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90

, as

it does in high-gain configurations. At low gains (increased
feedback factors), most amplifiers will exhibit a more com-
plex response with lower phase margin. The OPA3690 is
compensated to give a slightly peaked response in a
noninverting gain of 2 see (Figure 1). This results in a typical
gain of +2 bandwidth of 220MHz, far exceeding that pre-
dicted by dividing the 300MHz GBP by 2. Increasing the gain
will cause the phase margin to approach 90

and the band-

width to more closely approach the predicted value of (GBP/
NG). At a gain of +10, the 30MHz bandwidth shown in the
Typical Specifications agrees with that predicted using the
simple formula and the typical GBP of 300MHz.

Frequency response in a gain of +2 may be modified to
achieve exceptional flatness simply by increasing the noise
gain to 2.5. One way to do this, without affecting the +2 signal
gain, is to add a 453

resistor across the two inputs in the

circuit of Figure 1. A similar technique may be used to reduce

(2)

(3)

Consult the Texas Instruments web site (www.ti.com) to
request any of these boards.

MACROMODELS

Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. A
SPICE model for the OPA690 is available through the Texas
Instruments web site (www.ti.com). Use three OPA690 mod-
els to simulate the OPA3690. These models do a good job
of predicting small-signal AC and transient performance
under a wide variety of operating conditions. They do not do
as well in predicting the harmonic distortion, temperature
performance, or dG/df characteristics. These models do not
attempt to distinguish between the package types in their
small-signal AC performance.

BOARD

LITERATURE

PART

REQUEST

PRODUCT

PACKAGE

NUMBER

OPA3690IDBQ

SSOP-16

DEM-OPA368xE

SBOU006

OPA3690ID

SO-16

DEM-OPA368xU

SBOU007

OPA3690

SBOS237B

www.ti.com

peaking in unity-gain (voltage follower) applications. For
example, by using a 402

feedback resistor along with a

402

resistor across the two op amp inputs, the voltage

follower response will be similar to the gain of +2 response
of Figure 2. Further reducing the value of the resistor across
the op amp inputs will further dampen the frequency re-
sponse due to increased noise gain.

The OPA3690 exhibits minimal bandwidth reduction going to
single-supply (+5V) operation as compared with

5V. This is

because the internal bias control circuitry retains nearly
constant quiescent current as the total supply voltage be-
tween the supply pins is changed.

INVERTING AMPLIFIER OPERATION

Since the OPA3690 is a general-purpose, wideband, volt-
age- feedback op amp, all of the familiar op amp application
circuits are available to the designer. Inverting operation is
one of the more common requirements and offers several
performance benefits. Figure 12 shows a typical inverting
configuration where the I/O impedances and signal gain from
Figure 1 are retained in an inverting circuit configuration.

100

feedback resistor in parallel with the external load. In

general, the feedback resistor should be limited to the 100

to 1.5k

range. In this case, it is preferable to increase both

the R

and R

values, see Figure 12, and then achieve the

input matching impedance with a third resistor (R

) to ground.

The total input impedance becomes the parallel combination
of R

and R

The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence influences
the bandwidth. For the example in Figure 12, the R

value combines in parallel with the external 50

source

impedance, yielding an effective driving impedance of
50

|| 66.5

= 28.5

. This impedance is added in series

with R

for calculating the noise gain (NG). The resultant

NG is 2.76 for Figure 11, as opposed to only 2 if R

could

be eliminated, as discussed above. The bandwidth will
therefore be slightly lower for the gain of 2 circuit of Figure 12
than for the gain of +2 circuit of Figure 1.

The third important consideration in inverting amplifier design
is setting the bias current cancellation resistor on the
noninverting input (R

). If this resistor is set equal to the total

DC resistance looking out of the inverting node, the output
DC error, due to the input bias currents, will be reduced to
(Input Offset Current) · R

. If the 50

source impedance is

DC-coupled in Figure 12, the total resistance to ground on
the inverting input will be 228

. Combining this in parallel

with the feedback resistor gives the R

= 145

used in this

example. To reduce the additional high-frequency noise
introduced by this resistor, it is sometimes bypassed with a
capacitor. As long as R

< 350

, the capacitor is not required

since the total noise contribution of all other terms will be less
than that of the op amp's input noise voltage. As a minimum,
the OPA3690 requires an R

value of 50

to damp out

parasitic-induced peaking--a direct short to ground on the
noninverting input runs the risk of a very high-frequency
instability in the input stage.

OUTPUT CURRENT AND VOLTAGE

The OPA3690 provides output voltage and current capabili-
ties that are unsurpassed in a low-cost monolithic op amp.
Under no-load conditions at +25

C, the output voltage typi-

cally swings closer than 1V to either supply rail; the tested
swing limit is within 1.2V of either rail. Into a 15

load

(the minimum tested load), it is tested to deliver more than

160mA.

The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage · current, or V-I product,
which is more relevant to circuit operation. Refer to the
"Output Voltage and Current Limitations" plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA3690's output drive capabilities,
noting that the graph is bounded by a "Safe Operating Area"
of 1W maximum internal power dissipation for a single

In the inverting configuration, three key design consider-
ations must be noted. The first is that the gain resistor (R

)

becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial when-
ever the signal is coupled through a cable, twisted-pair, long
PC board trace, or other transmission line conductor), R

may be set equal to the required termination value and R

adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise per-
formance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting R

to 50

for input matching eliminates the need for R

but requires a

100

feedback resistor. This has the interesting advantage

that the noise gain becomes equal to 2 for a 50

source

impedance--the same as the noninverting circuits consid-
ered above. The amplifier, however, output will now see the

1/3

OPA3690

402

200

145

66.5

Source

DIS

+5V

0.1

6.8

0.1

6.8

Load

FIGURE 12. Gain of 2 Example Circuit.

OPA3690

SBOS237B

www.ti.com

channel. Superimposing resistor load lines onto the plot
shows that the OPA3690 can drive

2.5V into 25

3.5V

into 50

without exceeding the output capabilities or the 1W

dissipation limit. A 100

load line (the standard test circuit

load) shows the full

3.9V output swing capability, as shown

in the Typical Characteristics.

The minimum specified output voltage and current specifica-
tions over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold startup will the
output current and voltage decrease to the numbers shown
in the Electrical Characteristics tables. As the output transis-
tors deliver power, their junction temperatures will increase,
decreasing their V

's (increasing the available output volt-

age swing), and increasing their current gains (increasing the
available output current). In steady-state operation, the avail-
able output voltage and current will always be greater than
that shown in the over temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.

To protect the output stage from accidental shorts to ground
and the power supplies, output short-circuit protection is
included in the OPA3690. This circuits acts to limit the
maximum source or sink current to approximately 250

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC--including additional
external capacitance which may be recommended to im-
prove ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA3690 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier's open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.

The Typical Characteristics show the recommended R

ver-

sus capacitive load and the resulting frequency response at
the load. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA3690. Long PC
board traces, unmatched cables, and connections to multiple
devices can easily exceed this value. Always consider this
effect carefully, and add the recommended series resistor as
close as possible to the OPA3690 output pin (see Board
Layout Guidelines).

The criterion for setting this R

resistor is a maximum

bandwidth, flat frequency response at the load. For the

OPA3690 operating in a gain of +2, the frequency response
at the output pin is already slightly peaked without the
capacitive load requiring relatively high values of R

to flatten

the response at the load. Increasing the noise gain will
reduce the peaking, as described previously. The circuit of
Figure 13 demonstrates this technique, allowing lower values
of R

to be used for a given capacitive load. This was used

to generate the Recommended R

versus Capacitive Load

plots.

1/3

OPA3690

402

175

402

+5V

Power-supply decoupling

not shown.

FIGURE 13. Capacitive Load Driving with Noise Gain Tuning.

This gain of +2 circuit includes a noise gain tuning resistor
across the two inputs to increase the noise gain, increasing
the unloaded phase margin for the op amp. Although this
technique will reduce the required R

resistor for a given

capacitive load, it does increase the noise at the output. It
also will decrease the loop gain, slightly decreasing the
distortion performance. If, however, the dominant distortion
mechanism arises from a high R

value, significant dynamic

range improvement can be achieved using this technique.

Figure 14 shows the required R

versus C

LOAD

parametric on

noise gain using this technique. This is the circuit of Figure
13 with R

adjusted to increase the noise gain (increasing

the phase margin) then sweeping C

LOAD

and finding the

required R

to get a flat frequency response. This plot also

gives the required R

versus C

LOAD

for the OPA3690 oper-

ated at higher signal gains without R

100

Capacitive Load (pF)

100

1000

(

)

NG = 2

NG = 3

NG = 4

FIGURE 14. Required R

vs Noise Gain.

OPA3690

SBOS237B

www.ti.com

DISTORTION PERFORMANCE

The OPA3690 provides good distortion performance into a
100

load on

5V supplies. Relative to alternative solutions,

it provides exceptional performance into lighter loads and/or
operating on a single +5V supply.

The distortion plots show which changes in operation will
improve distortion. Increasing the load impedance improves
distortion directly. Remember that the total load includes the
feedback network; in the noninverting configuration
(see Figure 1) this is sum of R

+ R

, while in the inverting

configuration (see Figure 11), it is just R

. Also, providing an

additional supply decoupling capacitor (0.1

F) between the

supply pins (for bipolar operation) improves the 2nd-order
distortion slightly (3dB to 6dB).

In most op amps, increasing the output voltage swing in-
creases intermodulation distortion directly. The new output
stage used in the OPA3690 actually holds the difference
between fundamental power and the 3rd-order intermodulation
powers relatively constant with increasing output power until
very large output swings are required (> 4Vp-p). The
3rd-order spurious levels are extremely low at low output
power levels. The output stage continues to hold them low
even as the fundamental power reaches very high levels. As
the Typical Characteristics show, the spurious intermodulation
powers do not increase as predicted by a traditional intercept
model. As the fundamental power level increases, the dy-
namic range does not decrease significantly. For 2 tones
centered at 20MHz, with 10dBm/tone into a matched 50

load (i.e., 2Vp-p for each tone at the load, which requires
8Vp-p for the overall 2-tone envelope at the output pin), the
Typical Characteristics show 46dBc difference between the
test-tone powers and the 3rd-order intermodulation spurious
powers. This exceptional performance improves further when
operating at lower frequencies.

NOISE PERFORMANCE

High slew rate, unity-gain stable, voltage-feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 5.5nV/

Hz input voltage noise for

the OPA3690 is, however, much lower than comparable
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms, combine to give low
output noise under a wide variety of operating conditions.
Figure 15 shows the op amp noise analysis model with all the
noise terms included. In this model, all noise terms are taken
to be noise voltage or current density terms in either nV/

or pA/

Hz.

The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 4 shows the general form for the
output noise voltage using the terms shown in Figure 15.

kTR

I R

kTR NG

BN S

BI F

(

)

(

)

4kT

1/3

OPA3690

4kT = 1.6E 20J

at 290

4kTR

FIGURE 15. Op Amp Noise Analysis Model.

Dividing this expression by the noise gain (NG = (1 + R

))

will give the equivalent input-referred spot noise voltage at the
noninverting input, as shown in Equation 5:

(5)

kTR

BN S

BN F

(

)

Evaluating these two equations for the OPA3690 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 12.3nV/

Hz and a total equivalent input

spot noise voltage of 6.1nV/

Hz. This is including the noise

added by the bias current cancellation resistor (100

) on the

noninverting input. This total input-referred spot noise volt-
age is only slightly higher than the 5.5nV/

Hz specification

for the op amp voltage noise alone. This will be the case as
long as the impedances appearing at each op amp input are
limited to the previously recommend maximum value of
300

. Keeping both (R

|| R

) and the noninverting input

source impedance less than 300

will satisfy both noise and

frequency response flatness considerations. Since the resis-
tor-induced noise is relatively negligible, additional capacitive
decoupling across the bias current cancellation resistor (R

)

for the inverting op amp configuration of Figure 12 is not
required.

DC ACCURACY AND OFFSET CONTROL

The balanced input stage of a wideband voltage-feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power-supply current trim for the OPA3690
gives even tighter control than comparable products. Al-
though the high-speed input stage does require relatively
high input bias current (typically 5

A out of each input

terminal), the close matching between them may be used to
reduce the output DC error caused by this current. The total
output offset voltage may be considerably reduced by match-
ing the DC source resistances appearing at the two inputs.
This reduces the output DC error due to the input bias
currents to the offset current times the feedback resistor.
Evaluating the configuration of Figure 1, using worst-case

(4)

OPA3690

SBOS237B

www.ti.com

+25

C input offset voltage and current specifications, gives a

worst-case output offset voltage equal to: (NG = noninverting
signal gain).

(NG · V

OS(MAX)

)

· I

OS(MAX)

)

(6)

(2 · 4.5mV)

(250

· 1

9.25mV

A fine-scale output offset null, or DC operating point adjust-
ment, is often required. Numerous techniques are available
for introducing DC offset control into an op amp circuit. Most
of these techniques eventually reduce to adding a DC current
through the feedback resistor. In selecting an offset trim
method, one key consideration is the impact on the desired
signal path frequency response. If the signal path is intended
to be noninverting, the offset control is best applied as an
inverting summing signal to avoid interaction with the signal
source. If the signal path is intended to be inverting, applying
the offset control to the noninverting input may be consid-
ered. However, the DC offset voltage on the summing
junction will set up a DC current back into the source which
must be considered. Applying an offset adjustment to the
inverting op amp input can change the noise gain and
frequency response flatness. For a DC-coupled inverting
amplifier, Figure 16 shows one example of an offset adjust-
ment technique that has minimal impact on the signal fre-
quency response. In this case, the DC offsetting current is
brought into the inverting input node through resistor values
that are much larger than the signal path resistors. This will
insure that the adjustment circuit has minimal effect on the
loop gain and hence the frequency response.

will operate normally. To disable, the control pin must be
asserted LOW. Figure 17 shows a simplified internal circuit for
the disable control feature available on each channel.

402

200mV Output Adjustment

= = 2

Supply decoupling

not shown.

328

0.1

200

1.25k

10k

0.1

+5V

1/3

OPA3690

+5V

FIGURE 16. DC-Coupled, Inverting Gain of 2 with Offset

Adjustment.

DISABLE OPERATION

The OPA3690 provides an optional disable feature on each
channel that may be used either to reduce system power or to
implement a simple channel multiplexing operation. If the DIS
control pin of each channel is left unconnected, the OPA3690

In normal operation, base current to Q1 is provided through
the 110k

resistor, while the emitter current through the

15k

resistor sets up a voltage drop that is inadequate to

turn on the two diodes in Q1's emitter. As V

DIS

is pulled

LOW, additional current is pulled through the 15k

resistor,

eventually turning on those two diodes (

A). At this point,

any further current pulled out of V

DIS

goes through those

diodes holding the emitter-base voltage of Q1 at approxi-
mately 0V. This shuts off the collector current out of Q1,
turning the amplifier off. The supply current in the disable
mode are only those required to operate the circuit of Figure
17. Additional circuitry ensures that turn-on time occurs
faster than turn-off time (make-before-break).

When disabled, the output and input nodes go to a high
impedance state. If the OPA3690 is operating in a gain of +1,
this will show a very high impedance at the output and
exceptional signal isolation. If operating at a gain greater than
+1, the total feedback network resistance (R

+ R

) will appear

as the impedance looking back into the output, but the circuit
will still show very high forward and reverse isolation. If
configured as an inverting amplifier, the input and output will
be connected through the feedback network resistance
(R

+ R

) and the isolation will be very poor as a result.

One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. See Figure
18 for these glitches for the circuit of Figure 1 with the input
signal at 0V. The glitch waveform at the output pin is plotted
along with the DIS pin voltage.

The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 18, the edge rate
was reduced until no further reduction in glitch amplitude was
observed. This approximately 1V/ns maximum slew rate may
be achieved by adding a simple RC filter into the DIS pin
from a higher speed logic line. If extremely fast transition
logic is used, a 1k

series resistor between the logic gate

and the DIS input pin will provide adequate bandlimiting

25k

110k

15k

Control

DIS

FIGURE 17. Simplified Disable Control Circuit.

OPA3690

SBOS237B

www.ti.com

using just the parasitic input capacitance on the DIS pin
while still ensuring adequate logic level swing.

THERMAL ANALYSIS

Due to the high output power capability of the OPA3690,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation, as
described below. In no case should the maximum junction
temperature be allowed to exceed 175

Operating junction temperature (T

) is given by T

+ P

The total internal power dissipation (P

) is the sum of

quiescent power (P

) and additional power dissipated in the

output stage (P

) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total
supply voltage across the part. P

will depend on the

required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition, P

= V

/(4 · R

)

where R

includes feedback network loading.

Note that it is the power in the output stage and not into the
load that determines internal power dissipation.

As a worst-case example, compute the maximum T

using an

OPA3690IDBQ in the circuit of Figure 1 operating at the
maximum specified ambient temperature of +85

C and driv-

ing a grounded 100

load.

= 10V · 18.6mA + 3 · [5

/(4 · (100

|| 804

))] = 397mW

Maximum T

= +85

C + (0.40W · 100

C/W) = 125

This worst-case condition is still well within rated maximum
T

for this 100

load. Heavier loads may, however, exceed

the 175

C maximum junction temperature rating. Careful

attention to internal power dissipation is required and per-
haps airflow considered under extreme conditions.

Time (20ns/div)

Output Voltage (20mV/div)

Output Voltage

(0V Input)

DIS

0.2V

4.8V

FIGURE 18. Disable/Enable Glitch.

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency am-
plifier like the OPA3690 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Other-
wise, ground and power planes should be unbroken else-
where on the board.

b) Minimize the distance (< 0.25") from the power-supply
pins to high frequency 0.1

F decoupling capacitors. At the

device pins, the ground and power-plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections should always be decoupled with these capaci-
tors. An optional supply decoupling capacitor (0.1

F) across

the two power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2

F to 6.8

decoupling capacitors, effective at lower frequencies, should
also be used on the main supply pins. These may be placed
somewhat farther from the device and may be shared among
several devices in the same area of the PC board.

c) Careful selection and placement of external compo-
nents will preserve the high-frequency performance of
the OPA3690. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal film or carbon composition axially-
leaded resistors can also provide good high-frequency per-
formance. Again, keep their leads and PC board traces as
short as possible. Never use wirewound type resistors in a
high-frequency application. Since the output pin and invert-
ing input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as noninverting input termination resis-
tors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feed-
back resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resis-
tors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values > 1.5k

this parasitic capacitance can add a pole and/or zero below
500MHz that can affect circuit operation. Keep resistor val-
ues as low as possible, consistent with load driving consid-
erations. The 402

feedback used in the typical performance

specifications is a good starting point for design. Note that
a 25

feedback resistor, rather than a direct short, is

OPA3690

SBOS237B

www.ti.com

suggested for the unity-gain follower application. This effec-
tively isolates the inverting input capacitance from the output
pin that would otherwise cause an additional peaking in the
gain of +1 frequency response.

d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R

from the

plot of "Recommended R

vs Capacitive Load". Low parasitic

capacitive loads (< 5pF) may not need an R

since the

OPA3690 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an R

are allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated transmission
line is acceptable, implement a matched impedance trans-
mission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline layout
techniques). A 50

environment is normally not necessary

on board, and in fact, a higher impedance environment will
improve distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance defined
(based on board material and trace dimensions), a matching
series resistor into the trace from the output of the OPA3690
is used as well as a terminating shunt resistor at the input of
the destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device;
this total effective impedance should be set to match the
trace impedance. The high output voltage and current capa-
bility of the OPA3690 allows multiple destination devices to
be handled as separate transmission lines, each with their
own series and shunt terminations. If the 6dB attenuation of
a doubly-terminated transmission line is unacceptable, a

long trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case and set the
series resistor value as shown in the plot of "Recommended
R

vs Capacitive Load". This will not preserve signal integrity

as well as a doubly-terminated line. If the input impedance of
the destination device is low, there will be some signal
attenuation due to the voltage divider formed by the series
output into the terminating impedance.

INPUT AND ESD PROTECTION

The OPA3690 is built using a very high-speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry devices.
These breakdowns are reflected in the Absolute Maximum
Ratings table. All device pins are protected with internal ESD
protection diodes to the power supplies, as shown in Figure 19.

External

Internal
Circuitry

FIGURE 19. Internal ESD Protection.

These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with

15V supply parts

driving into the OPA3690), current-limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products

Applications

Amplifiers

amplifier.ti.com

Audio

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

www.ti.com/broadband

Interface

interface.ti.com

Digital Control

www.ti.com/digitalcontrol

Logic

logic.ti.com

Military

www.ti.com/military

Power Mgmt

power.ti.com

Optical Networking

www.ti.com/opticalnetwork

Microcontrollers

microcontroller.ti.com

Security

www.ti.com/security

Telephony

www.ti.com/telephony

Video & Imaging

www.ti.com/video

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

2003, Texas Instruments Incorporated

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OPA3690ID

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OPA3690ID