Burr Brown Products
from Texas Instruments
FEATURES
DESCRIPTION
APPLICATIONS
Switching
Stage
Sampling
Comparator (SC)
OPA615
Biasing
OTA
Hold
Control
Emitter
2
Collector
(I
OUT
)
12
1
S/H
In+
S/H
In
-
+V
CC
-
V
CC
I
Q
Adjust
SOTA
Base
C
HOLD
Ground
3
4
9
7
10
11
13
5
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
Wide-Bandwidth, DC Restoration Circuit
PROPAGATION DELAY: 1.9ns
The OPA615 is a complete subsystem for very fast
and precise DC restoration, offset clamping, and
BANDWIDTH:
low-frequency hum suppression of wideband ampli-
OTA: 710MHz
fiers or buffers. Although it is designed to stabilize the
Comparator: 730MHz
performance of video signals, the circuit can also be
LOW INPUT BIAS CURRENT:
1A
used as a sample-and-hold amplifier, high-speed
SAMPLE-AND-HOLD SWITCHING
integrator, or peak detector for nanosecond pulses.
TRANSIENTS:
5mV
The
device
features
a
wideband
Operational
Transconductance
Amplifier
(OTA)
with
a
SAMPLE-AND-HOLD FEEDTHROUGH
high-impedance cascode current source output and
REJECTION: 100dB
fast and precise sampling comparator that together
CHARGE INJECTION: 40fC
set a new standard for high-speed applications. Both
HOLD COMMAND DELAY TIME: 2.5ns
the OTA and the sampling comparator can be used
as stand-alone circuits or combined to form a more
TTL/CMOS HOLD CONTROL
complex signal processing stage. The self-biased,
bipolar OTA can be viewed as an ideal volt-
age-controlled current source and is optimized for low
BROADCAST/HDTV EQUIPMENT
input bias current. The sampling comparator has two
TELECOMMUNICATIONS EQUIPMENT
identical high-impedance inputs and a current source
output optimized for low output bias current and offset
HIGH-SPEED DATA ACQUISITION
voltage; it can be controlled by a TTL-compatible
CAD MONITORS/CCD IMAGE PROCESSING
switching stage within a few nanoseconds. The
NANOSECOND PULSE INTEGRATOR/PEAK
transconductance
of
the
OTA
and
sampling
DETECTOR
comparator can be adjusted by an external resistor,
PULSE CODE MODULATOR/DEMODULATOR
allowing bandwidth, quiescent current, and gain
COMPLETE VIDEO DC LEVEL RESTORATION
trade-offs to be optimized.
SAMPLE-AND-HOLD AMPLIFIER
The OPA615 is available in both an SO-14 sur-
SHC615 UPGRADE
face-mount and an MSOP-10 package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 20042005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
TRANSPORT MEDIA,
PRODUCT
PACKAGE
DESIGNATOR
RANGE
MARKING
ORDERING NUMBER
QUANTITY
OPA615ID
Rails, 50
OPA615
SO-14
D
40
C to +85
C
OPA615ID
OPA615IDR
Tape and Reel, 2500
OPA615IDGST
Tape and Reel, 250
OPA615
MSOP-10
(2)
DGS
40
C to +85
C
BJT
OPA615IDGSR
Tape and Reel, 2500
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at
www.ti.com
.
(2)
Available Q1 2006.
Supply Voltage
6.5V
Differential Input Voltage
V
S
Common-Mode Input Voltage Range
V
S
Hold Control Pin Voltage
V
S
+V
S
Storage Temperature Range
40
C to +125
C
Lead Temperature (10s soldering)
+260
C
Junction Temperature (T
J
)
+150
C
ESD Ratings:
Human Body Model (HBM)
(2)
1000V
Charge Device Model (CDM)
1000V
Machine Model (MM)
150V
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2)
Pin 2 for the SO-14 package and pin 1 for the MSOP-10 package > 500V HBM.
2
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Switching
Stage
Sampling
Comparator (SC)
OPA615
Biasing
OTA
Hold
Control
Emitter
2
Collector
(I
O UT
)
12
1
S/H
In+
S/H
In
-
+V
CC
-
V
C C
I
Q
Adjust
SOTA
Base
C
HO LD
Ground
3
4
9
7
10
11
13
5
Switching
Stage
Sampling
Comparator (SC)
OPA615
Biasing
OTA
Hold
Control
Emitter
1
Collector
(I
O U T
)
9
S/H
In+
S/H
In
-
+V
CC
-
V
C C
SOTA
Base
C
HO LD
Ground
2
3
6
5
7
8
10
4
MSOP-10
SO-14
1
2
3
4
5
10
9
8
7
6
+V
CC
I
OUT
, Collector, C
S/H In
-
S/H In+
Ground
Emitter, E
Base, B
C
HOLD
-
V
CC
Hold Control
BJT
MSOP-10
NOTE: (1) No Connection.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
(1)
+V
CC
I
OUT
, Collector, C
S/H In
-
S/H In+
Ground
NC
(1)
I
Q
Adjust
Emitter, E
Base, B
C
HOLD
-
V
CC
NC
(1)
Hold Control
OPA615
SO-14
Top View
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
BLOCK DIAGRAMS
PIN CONFIGURATIONS
3
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ELECTRICAL CHARACTERISTICS: V
S
=
5V
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
R
L
= 100
, R
Q
= 300
, and R
IN
= 50
, unless otherwise noted.
OPA615ID, OPA615IDGS
TYP
MIN/MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(2)
70
C
(3)
+85
C
(3)
UNITS
MAX
LEVEL
(1)
AC PERFORMANCE (OTA)
See
Figure 36
b
Small Signal Bandwidth (B to E)
V
O
= 200mV
PP
, R
L
= 500
710
MHz
min
C
V
O
= 1.4V
PP
, R
L
= 500
770
MHz
min
C
V
O
= 2.8V
PP
, R
L
= 500
230
MHz
min
C
Large Signal Bandwidth (B to E)
V
O
= 5V
PP
, R
L
= 500
200
MHz
min
C
Small Signal Bandwdith (B to C)
G= +1, V
O
= 200mV
PP
, R
L
= 100
440
MHz
min
C
G= +1, V
O
= 1.4V
PP
, R
L
= 100
475
MHz
min
C
G= +1, V
O
= 2.8V
PP
, R
L
= 100
230
MHz
min
C
Large Signal Bandwidth (B to C)
G= +1, V
O
= 5V
PP
, R
L
= 100
230
MHz
min
C
Rise-and-Fall Time (B to E)
V
O
= 2V
PP
, R
L
= 500
2
ns
max
C
Rise-and-Fall Time (B to C)
G = +1, V
O
= 2V
PP
, R
L
= 100
2
ns
max
C
Harmonic Distortion (B to E)
R
E
= 100
2nd-Harmonic
V
O
= 1.4V
PP
, f = 30MHz
62
50
48
47
dBc
min
B
3rd-Harmonic
V
O
= 1.4V
PP
, f = 30MHz
47
40
35
33
dBc
min
B
Input Voltage Noise
Base Input, f > 100kHz
4.6
6.2
6.9
7.4
nV/
Hz
max
B
Input Current Noise
Base Input, f > 100kHz
2.5
3.1
3.6
3.9
pA/
Hz
max
B
Input Current Noise
Emitter Input, f > 100kHz
21
23
25
27
pA/
Hz
max
B
DC PERFORMANCE (OTA)
See
Figure 37
b
Transconductance (V-base to I-collector)
V
B
=
5mV
PP
, R
C
= 0
, R
E
= 0
72
65
63
58
mA/V
min
A
B-Input Offset Voltage
V
B
= 0V, R
C
= 0V, R
E
= 100
4
40
47
50
mV
max
A
B-Input Offset Voltage Drift
V
B
= 0V, R
C
= 0V, R
E
= 100
160
160
V/
C
max
B
B-Input Bias Current
V
B
= 0V, R
C
= 0V, R
E
= 100
0.5
0.9
1.5
1.7
A
max
A
B-Input Bias Current Drift
V
B
= 0V, R
C
= 0V, R
E
= 100
12
12
nA/
C
max
B
E-Input Bias Current
V
B
= 0V, V
C
= 0V
35
110
120
135
A
min
A
E-Input Bias Current Drift
V
B
= 0V, V
C
= 0V
200
250
nA/
C
max
B
C-Output Bias Current
V
B
= 0V, V
C
= 0V
35
100
110
125
A
max
A
C-Output Bias Current
V
B
= 0V, V
C
= 0V
200
250
nA/
C
max
B
INPUT (OTA Base)
See
Figure 37
b
Input Voltage Range
R
E
= 100
3.4
3.2
3.1
3.0
V
min
B
Input Impedance
B-Input
7 || 1.5
M
|| pF
typ
C
OTA Power-Supply Rejection Ratio
V
S
to V
IO
at E-Input
54
49
47
46
dB
min
A
(PSRR)
OUTPUT (OTA Collector)
See
Figure 37
b
Output Voltage Compliance
I
E
= 2mA
3.5
3.4
3.4
3.4
V
min
A
Output Current
V
C
= 0V
20
18
17
17
mA
min
A
Output Impedance
V
C
= 0V
1.2 || 2
M
|| pF
typ
C
COMPARATOR PERFORMANCE
AC Performance
Output Current Bandwidth
I
O
< 4mA
PP
730
520
480
400
MHz
min
B
Output Current Rise and Fall Time
I
IO
=
2mA
PP
, R
L
= 50
at C
HOLD
1.4
1.5
1.7
2
ns
max
B
Control Propagation Delay Time
Hold
Track and Track
Hold
2.5
ns
typ
C
Signal Propagation Delay Time
S/H In+ S/H In to C
HOLD
Current
1.9
ns
typ
C
Input Differential Voltage Noise
S/H In+ S/H In
6
7.5
8
9
nV/
Hz
max
B
Charge Injection
Track-to-Hold
40
fC
typ
C
Feedthrough Rejection
Hold Mode, V
IN
= 1V
PP
, f < 20MHz
100
dB
typ
C
(1)
Test levels: (A) 100% tested at +25
C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2)
Junction temperature = ambient for +25
C tested specifications.
(3)
Junction temperature = ambient at low temperature limit; junction temperature = ambient +23
C at high temperature limit for over
temperature specifications.
4
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OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
ELECTRICAL CHARACTERISTICS: V
S
=
5V (continued)
R
L
= 100
, R
Q
= 300
, and R
IN
= 50
, unless otherwise noted.
OPA615ID, OPA615IDGS
TYP
MIN/MAX OVER TEMPERATURE
0
C to
40
C to
MIN/
TEST
PARAMETER
CONDITIONS
+25
C
+25
C
(2)
70
C
(3)
+85
C
(3)
UNITS
MAX
LEVEL
(1)
DC Performance
Input Bias Current
S/H In+ = S/H In = 0V
1
3
3.5
4.0
A
max
A
Output Offset Current
S/H In+ = S/H In = 0V, Track Mode
10
50
70
80
A
max
A
Input Impedance
S/H In+ and S/H In
200 || 1.2
k
|| pF
typ
C
Input Differential Voltage Range
S/H In+ S/H In
3.0
V
typ
C
Input Common-Mode Voltage Range
S/H In+ and S/H In
3.2
V
typ
C
Common-Mode Rejection Ratio (CMRR)
2
50
55
60
A/V
max
A
Output Voltage Compliance
C
HOLD
Pin
3.5
V
typ
C
Output Current
C
HOLD
Pin
5
3
2.5
2.0
mA
min
A
Output Impedance
C
HOLD
Pin
0.5 || 1.2
M
|| pF
typ
C
Transconductance
S/H In+ S/H In to C
HOLD
Current
35
21
20
19
mA/V
min
A
V
IN
= 300mV
PP
Minimum Hold Logic High Voltage
Tracking High
2
2
2
V
max
A
Maximum Hold Logic Low Voltage
Holding Low
0.8
0.8
0.8
V
min
A
Logic High Input Current
V
HOLD
= +5V
0.5
1
1
1.2
A
max
A
Logic Low Input Current
V
HOLD
= 0V
140
200
220
230
A
max
A
Comparator Power-Supply Rejection
S/H In+ = S/H In = 0V, Track Mode
2
50
55
60
A/V
max
A
Ratio (PSRR)
POWER SUPPLY
Specified Operating Voltage
5
V
typ
C
Minimum Operating Voltage
4
4
4
V
min
B
Maximum Operating Voltage
6.2
6.2
6.2
V
max
A
Maximum Quiescent Current
R
Q
= 300
(4)
13
14
16
17
mA
max
A
Minimum Quiescent Current
R
Q
= 300
(4)
13
12
11
9
mA
min
A
THERMAL CHARACTERISTICS
Specified Operating Range D Package
40 to +85
C
typ
C
Thermal Resistance
JA
Junction-to-Ambient
DGS
MSOP-10
150
C/W
typ
C
D
SO-14
100
C/W
typ
C
(4)
SO-14 package only.
5
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TYPICAL CHARACTERISTICS
OTA
120
100
80
60
40
20
0
Frequency (Hz)
T
r
a
n
s
c
o
n
d
u
c
t
a
n
c
e
(
m
A
/
V
)
10k
1M
10M
100M
1G
I
OUT
V
IN
50
50
I
Q
= 14.3mA (89mA/V), R
Q
= 0
I
Q
= 13mA (72mA/V), R
Q
= 300
I
Q
= 9.6mA (28mA/V), R
Q
= 2k
V
IN
= 10mV
PP
120
100
80
60
40
30
0
Quiescent Current (mA)
T
r
a
n
s
c
o
n
d
u
c
t
a
n
c
e
(
m
A
/
V
)
8
9
10
11
12
13
14
15
V
IN
= 100mV
PP
I
OUT
V
IN
50
50
100
90
80
70
60
50
40
30
20
Input Voltage (mV)
T
r
a
n
s
c
o
n
d
u
c
t
a
n
c
e
(
m
A
/
V
)
-
50
-
40
-
30
-
20
-
10
0
10
20
30
40
50
Small-Signal Around Input Voltage
I
Q
= 9.6mA
I
Q
= 14.3mA
I
Q
= 13mA
20
15
10
5
0
-
5
-
10
-
15
-
20
OTA Input Voltage (mV)
O
T
A
O
u
t
p
u
t
C
u
r
r
e
n
t
(
m
A
)
-
200
0
200
-
150
-
100
-
50
50
100
150
I
Q
= 9.6mA
I
Q
= 14.3mA
I
Q
= 13mA
I
O UT
V
IN
50
50
0.15
0.10
0.05
0
-
0.05
-
0.10
-
0.15
Time (10ns/div)
O
u
t
p
u
t
V
o
l
t
a
g
e
(
V
)
f
IN
= 10MHz
G = +1V/V
V
IN
= 0.2V
PP
3
2
1
0
-
1
-
2
-
3
Time (10ns/div)
O
u
t
p
u
t
V
o
l
t
a
g
e
(
V
)
f
IN
= 10MHz
G = +1V/V
V
IN
= 4V
PP
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
T
A
= +25
C, I
Q
= 13mA, unless otherwise noted.
OTA TRANSCONDUCTANCE vs FREQUENCY
OTA TRANSCONDUCTANCE vs QUIESCENT CURRENT
Figure 1.
Figure 2.
OTA TRANSCONDUCTANCE vs INPUT VOLTAGE
OTA TRANSFER CHARACTERISTICS
Figure 3.
Figure 4.
OTA-C SMALL SIGNAL PULSE RESPONSE
OTA-C LARGE SIGNAL PULSE RESPONSE
Figure 5.
Figure 6.
6
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140
120
100
80
60
40
20
0
Quiescent Current (mA)
O
T
A
B
-
I
n
p
u
t
R
e
s
i
s
t
a
n
c
e
(
M
)
8
9
10
12
11
13
14
15
18
16
14
12
10
8
6
4
2
0
Quiescent Current (mA)
O
T
A
C
-
O
u
t
p
u
t
R
e
s
i
s
t
a
n
c
e
(
M
)
8
9
10
11
12
13
14
15
180
160
140
120
100
80
60
40
20
0
Quiescent Current (mA)
O
T
A
E
-
O
u
t
p
u
t
R
e
s
i
s
t
a
n
c
e
(
)
8
9
10
11
12
13
14
15
100
10
1
Frequency (Hz)
V
o
l
t
a
g
e
N
o
i
s
e
D
e
n
s
i
t
y
(
n
V
/
H
z
)
C
u
r
r
e
n
t
N
o
i
s
e
D
e
n
s
i
t
y
(
p
A
/
H
z
)
100
1k
10k
100k
1M
10M
B-Input Current Noise (2.5pA/
Hz)
B-Input Voltage Noise (4.6nV/
Hz)
E-Input Current Noise (21.0pA/
Hz)
2.0
1.5
1.0
0.5
0
-
0.5
-
1.0
-
1.5
-
2.0
Ambient Temperature (
_
C)
B
-
I
n
p
u
t
O
f
f
s
e
t
V
o
l
t
a
g
e
(
m
V
)
0.10
0.05
0
-
0.05
-
0.10
B
-
I
n
p
u
t
B
i
a
s
C
u
r
r
e
n
t
(
V
)
-
40
-
20
120
0
20
40
60
80
100
B-Input Bias Current
B-Input Offset Voltage
35
30
25
20
15
10
5
0
-
5
-
10
-
15
-
20
-
25
-
30
-
35
OTA-B Input Voltage (mV)
O
T
A
-
C
O
u
t
p
u
t
C
u
r
r
e
n
t
(
m
A
)
-
3.5
-
3
-
2.5
-
2
-
1.5
-
1
-
0.5 0 0.5
1 1.5 2 2.5
3 3.5
I
O UT
V
IN
Degenerated E-Input
R
E
= R
L
= 100
100
100
I
Q
= 14.3mA
I
Q
= 13mA
I
Q
= 9.6mA
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
T
A
= +25
C, I
Q
= 13mA, unless otherwise noted.
OTA B-INPUT RESISTANCE vs QUIESCENT CURRENT
OTA C-OUTPUT RESISTANCE vs QUIESCENT CURRENT
Figure 7.
Figure 8.
OTA E-OUTPUT RESISTANCE vs QUIESCENT CURRENT
OTA INPUT VOLTAGE AND CURRENT NOISE DENSITY
Figure 9.
Figure 10.
OTA B-INPUT OFFSET VOLTAGE AND BIAS CURRENT
OTA TRANSFER CHARACTERISTICS vs INPUT VOLTAGE
vs TEMPERATURE
Figure 11.
Figure 12.
7
www.ti.com
200
160
120
80
40
0
-
40
-
80
-
120
-
160
-
200
Time (20ns/div)
O
u
t
p
u
t
V
o
l
t
a
g
e
(
m
V
)
2.0
1.6
1.2
0.8
0.4
0
-
0.4
-
0.8
-
1.2
-
1.6
-
2.0
O
u
t
p
u
t
V
o
l
t
a
g
e
(
V
)
V
IN
V
O
50
100
500
Small-Signal
80mV
Left Scale
Large-Signal
1.6V
Right Scale
3
0
-
3
-
6
-
9
-
12
-
15
Frequency (Hz)
G
a
i
n
(
d
B
)
1M
10M
100M
1G
V
IN
V
O
50
100
500
V
O
= 0.6V
PP
V
O
= 1.4V
PP
V
O
= 5V
PP
V
O
= 2.8V
PP
V
O
= 0.2V
PP
-
40
-
45
-
50
-
55
-
60
-
65
-
70
Frequency (MHz)
H
a
r
m
o
n
i
c
D
i
s
t
o
r
t
i
o
n
(
d
B
c
)
1
10
100
V
OUT
= 1.4V
PP
2nd-Harmonic
3rd-Harmonic
V
IN
V
OUT
50
10 0
3
0
-
3
-
6
-
9
-
12
-
15
Frequency (Hz)
G
a
i
n
(
d
B
)
1M
10M
100M
1G
V
O
= 0.6V
PP
V
O
= 1.4V
PP
V
O
= 0.2V
PP
V
O
= 2.8V
PP
V
O
= 5V
PP
V
IN
V
O
50
100
100
-
20
-
25
-
30
-
35
-
40
-
45
-
50
-
55
-
60
Frequency (MHz)
H
a
r
m
o
n
i
c
D
i
s
t
o
r
t
i
o
n
(
d
B
c
)
1
10
100
V
OUT
= 1.4V
PP
V
O U T
V
IN
50
100
100
3rd-Harmonic
2nd-Harmonic
16
15
14
13
12
11
10
9
8
Q
u
i
e
s
c
e
n
t
C
u
r
r
e
n
t
(
m
A
)
0.1
1
10
100
1k
10k
100k
R
Q
(
)
+I
Q
-
I
Q
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
T
A
= +25
C, I
Q
= 13mA, unless otherwise noted.
OTA-E OUTPUT FREQUENCY RESPONSE
OTA-E OUTPUT PULSE RESPONSE
Figure 13.
Figure 14.
OTA-C OUTPUT FREQUENCY RESPONSE
OTA-E OUTPUT HARMONIC DISTORTION vs FREQUENCY
Figure 15.
Figure 16.
OTA-C OUTPUT HARMONIC DISTORTION vs FREQUENCY
OTA QUIESCENT CURRENT vs R
Q
Figure 17.
Figure 18.
8
www.ti.com
SOTA (Sampling Operational Transconductance Amplifier)
40
30
20
10
0
Frequency (Hz)
T
r
a
n
s
c
o
n
d
u
c
t
a
n
c
e
(
m
A
/
V
)
1M
10M
100M
1G
V
IN
50
I
O UT
+5V
SOTA
Hold Control
50
V
IN
= 10mV
PP
40
30
20
10
0
Quiescent Current (mA)
T
r
a
n
s
c
o
n
d
u
c
t
a
n
c
e
(
m
A
/
V
)
8
9
10
11
12
13
14
15
R
Q
Adjusted
45
40
35
30
25
20
15
10
5
0
Input Voltage (mV)
T
r
a
n
s
c
o
n
d
u
c
t
a
n
c
e
(
m
A
/
V
)
-
100
-
80
-
60
-
40
-
20
0
20
40
60
80
100
Small-Signal Around Input Voltage
8
6
4
2
0
-
2
-
4
-
6
-
8
SOTA Input Voltage (mV)
S
O
T
A
O
u
t
p
u
t
C
u
r
r
e
n
t
(
m
A
)
-
200
-
150
-
100
-
50
0
50
100
150
200
150
100
50
0
-
50
-
100
-
150
Time (10ns/div)
O
u
t
p
u
t
V
o
l
t
a
g
e
(
m
V
)
f
IN
= 20MHz
R
L
= 50
I
OUT
= 4mA
PP
t
RISE
= 2ns
Hold Control = +5V
150
100
50
0
-
50
-
100
-
150
Time (10ns/div)
O
u
t
p
u
t
V
o
l
t
a
g
e
(
m
V
)
f
IN
= 20MHz
R
L
= 50
I
OUT
= 4mA
PP
t
RISE
= 10ns
Hold Control = +5V
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
T
A
= +25
C, I
Q
= 13mA, unless otherwise noted.
SOTA TRANSCONDUCTANCE vs FREQUENCY
SOTA TRANSCONDUCTANCE vs QUIESCENT CURRENT
Figure 19.
Figure 20.
SOTA TRANSCONDUCTANCE vs INPUT VOLTAGE
SOTA TRANSFER CHARACTERISTICS
Figure 21.
Figure 22.
SOTA PULSE RESPONSE
SOTA PULSE RESPONSE
Figure 23.
Figure 24.
9
www.ti.com
1.3
1.2
1.1
1.0
0.9
0.8
Input Voltage (mV)
T
r
a
n
s
c
o
n
d
u
c
t
a
n
c
e
(
m
A
/
V
)
0
400
600
200
800
1000
1200
V
OD
100
100
V
OD
GND
SOTA
V
OD
Negative
Positive
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Temperature (
_
C)
P
r
o
p
a
g
a
t
i
o
n
D
e
l
a
y
(
n
s
)
-
40
-
20
120
0
20
40
60
80
100
Falling Edge
Rising Edge
10
5
0
-
5
-
10
Time (10ns/div)
S
w
i
t
c
h
i
n
g
T
r
a
n
s
i
e
n
t
(
m
V
)
100
100
TTL
50
V
OUT
ON -OFF
OFF -ON
1.4
1.3
1.2
1.1
1.0
0.9
0.8
Rise Time (ns)
P
r
o
p
a
g
a
t
i
o
n
D
e
l
a
y
(
n
s
)
0
3
4
5
1
2
6
7
8
9
10
Positive
Negative
V
IN
= 1.2V
pp
-
0.6V
+0.6V
0V
150
100
50
0
-
50
-
100
-
150
Time (10ns/div)
O
u
t
p
u
t
V
o
l
t
a
g
e
(
m
V
)
2.5
2.0
1.5
1.0
0.5
0
-
50
H
o
l
d
C
o
m
m
a
n
d
(
V
)
6
3
0
-
3
-
6
-
9
-
12
-
15
Frequency (Hz)
G
a
i
n
(
d
B
)
1M
10M
100M
2G
1G
I
OUT
= 0.5mA
PP
I
OUT
= 4mA
PP
I
OUT
= 2mA
PP
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
T
A
= +25
C, I
Q
= 13mA, unless otherwise noted.
SOTA PROPAGATION DELAY vs OVERDRIVE
SOTA PROPAGATION DELAY vs TEMPERATURE
Figure 25.
Figure 26.
SOTA PROPAGATION DELAY vs SLEW RATE
SOTA SWITCHING TRANSIENTS
Figure 27.
Figure 28.
SOTA HOLD COMMAND DELAY TIME
SOTA BANDWIDTH vs OUTPUT CURRENT SWING
Figure 29.
Figure 30.
10
www.ti.com
0
-
20
-
40
-
60
-
80
-
100
-
120
Frequency (Hz)
F
e
e
d
t
h
r
o
u
g
h
R
e
j
e
c
t
i
o
n
(
d
B
)
1M
10M
100M
1G
Hold Control = 0V
(Off-Isolation)
0
-
20
-
40
-
60
-
80
-
100
-
120
Frequency (Hz)
C
o
m
m
o
n
-
M
o
d
e
R
e
j
e
c
t
i
o
n
(
d
B
)
100k
1M
10M
1G
100M
Hold Control = 5V
V+ = V
-
50
40
30
20
10
0
-
10
-
20
-
30
-
40
-
50
Temperature (
_
C)
O
u
t
p
u
t
B
i
a
s
C
u
r
r
e
n
t
(
A
)
-
40
-
20
120
0
20
40
60
80
100
Hold Control = 5V
V+ = V
-
= 0V
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
Temperature (
_
C)
I
n
p
u
t
B
i
a
s
C
u
r
r
e
n
t
(
A
)
-
40
-
20
120
0
20
40
60
80
100
Positive Input
Negative Input
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
TYPICAL CHARACTERISTICS (continued)
T
A
= +25
C, I
Q
= 13mA, unless otherwise noted.
SOTA FEEDTHROUGH REJECTION vs FREQUENCY
SOTA COMMON-MODE REJECTION vs FREQUENCY
Figure 31.
Figure 32.
SOTA INPUT BIAS CURRENT vs TEMPERATURE
SOTA OUTPUT BIAS CURRENT vs TEMPERATURE
Figure 33.
Figure 34.
11
www.ti.com
DISCUSSION OF PERFORMANCE
OPERATIONAL TRANSCONDUCTANCE
SECTION and OVERVIEW
I
C
+
V
IN
r
E
)
R
E
or
R
E
+
V
IN
I
C
*
r
E
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
The OPA615, which contains a wideband Operational
Transconductance Amplifier (OTA) and a fast sam-
AMPLIFIER (OTA) SECTION AND OVERVIEW
pling comparator (SOTA), represents a complete
subsystem for very fast and precise DC restoration,
offset clamping and correction to GND or to an
adjustable reference voltage, and low frequency hum
The symbol for the OTA section is similar to that of a
suppression of wideband operational or buffer ampli-
bipolar transistor, and the self-biased OTA can be
fiers.
viewed as either a quasi-ideal transistor or as a
Although the IC was designed to improve or stabilize
voltage-controlled current source. Application circuits
the performance of complex, wideband video signals,
for the OTA look and operate much like transistor
it can also be used as a sample-and-hold amplifier,
circuits--the
bipolar
transistor
is
also
a
volt-
high-speed integrator, peak detector for nanosecond
age-controlled current source. Like a transistor, it has
pulses, or as part of a correlated double sampling
three
terminals:
a
high-impedance
input
(base)
system. A wideband Operational Transconductance
optimized for a low input bias current of 0.3
A, a
Amplifier (OTA) with a high-impedance cascode cur-
low-impedance
input/output
(emitter),
and
the
rent source output and a fast and precise sampling
high-impedance current output (collector).
comparator sets a new standard for high-speed
The OTA consists of a complementary buffer ampli-
sampling applications.
fier and a subsequent complementary current mirror.
Both the OTA and the sampling comparator can be
The buffer amplifier features a Darlington output
used as stand-alone circuits or combined to create
stage and the current mirror has a cascoded output.
more complex signal processing stages such as
The addition of this cascode circuitry increases the
sample-and-hold amplifiers. The OPA615 simplifies
current source output resistance to 1.2M
. This
the design of input amplifiers with high hum sup-
feature improves the OTA linearity and drive capabili-
pression; clamping or DC-restoration stages in pro-
ties. Any bipolar input voltage at the high impedance
fessional broadcast equipment, high-resolution CAD
base has the same polarity and signal level at the low
monitors and information terminals; and signal pro-
impedance buffer or emitter output. For the open-loop
cessing stages for the energy and peak value of
diagrams, the emitter is connected to GND; the
nanoseconds pulses. This device also eases the
collector current is then determined by the voltage
design of high-speed data acquisition systems behind
between
base
and
emitter
times
the
a CCD sensor or in front of an analog-to-digital
transconductance. In application circuits (
Figure 36
b),
converter.
a resistor R
E
between the emitter and GND is used to
set the OTA transfer characteristics.
An external resistor on the SO-14 package, R
Q
,
allows the user to set the quiescent current. R
Q
is
The following formulas describe the most important
connected from Pin 1 (I
Q
adjust) to V
CC
. It deter-
relationships. r
e
is the output impedance of the buffer
mines the operating currents of the OTA section and
amplifier (emitter) or the reciprocal of the OTA
controls the bandwidth and AC behavior as well as
transconductance. Above
5mA, the collector current,
the transconductance of the OTA.
I
C
, will be slightly less than indicated by the formula.
Besides the quiescent current setting feature, a
Proportional-to-Absolute-Temperature (PTAT) supply
current control will increase the quiescent current
The R
E
resistor may be bypassed by a relatively large
versus
temperature.
This
variation
holds
the
capacitor to maintain high AC gain. The parallel
transconductance (g
m
) of the OTA and comparator
combination of R
E
and this large capacitor form a
relatively constant versus temperature. The circuit
high-pass filter, enhancing the high frequency gain.
parameters listed in the specification table are
Other cases may require an RC compensation net-
measured with R
Q
set to 300
, giving a nominal
work in parallel to R
E
to optimize the high-frequency
quiescent current at 13mA. While not always shown
response. The large signal bandwidth (V
O
= 1.4V
PP
)
in the application circuits, this R
Q
= 300
is required
measured at the emitter achieves 770MHz. The
to get the 13mA quiescent operating current.
frequency response of the collector is directly related
to the resistor value between the collector and GND;
it decreases with increasing resistor values, because
of the low-pass filter formed with the OTA C-output
capacitance.
12
www.ti.com
BASIC APPLICATION CIRCUITS
+V
CC
(13)
+V
CC
(5)
C
(12)
B
(3)
E
(2)
+1
R
B
R
L
R
B
R
E
V
-
Single Transistor
V+
V
I
V
O
(a) Common Emitter Amplifier
V
O
100
OTA
V
I
B
E
R
L
R
E
NoninvertingGain
(b) Common-E Amplifier for OTA
Inverting Gain
V
several volts
OS
3
2
C
12
Transconductance varies over temperature.
Transconductance remains constant over temperature.
V
OS
0
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
Figure 35
shows a simplified block diagram of the
While the OTA function and labeling appear similar to
OPA615 OTA. Both the emitter and the collector
those of a transistor, it offers essential distinctive
outputs offer a drive capability of
20mA for driving
differences and improvements: 1) The collector cur-
low impedance loads. The emitter output is not
rent flows out of the C terminal for a positive B-to-E
current-limited or protected. Momentary shorts to
input voltage and into it for negative voltages; 2) A
GND should be avoided, but are unlikely to cause
common emitter amplifier operates in non-inverting
permanent damage.
mode while the common base operates in inverting
mode; 3) The OTA is far more linear than a bipolar
transistor; 4) The transconductance can be adjusted
with an external resistor; 5) As a result of the PTAT
biasing characteristic, the quiescent current increases
as shown in the typical performance curve vs tem-
perature and keeps the AC performance constant; 6)
The OTA is self-biased and bipolar; and 7) The
output current is approximately zero for zero differen-
tial input voltages. AC inputs centered on zero
produce an output current centered on zero.
Most application circuits for the OTA section consist
of a few basic types which are best understood by
analogy to discrete transistor circuits. Just as the
transistor has three basic operating modes--common
emitter, common base, and common collector--the
OTA has three equivalent operating modes; com-
mon-E, common-B, and common-C (see
Figure 36
,
Figure 37
and
Figure 38
).
Figure 36
shows the OTA
connected as a Common-E amplifier, which is equiv-
alent to a common emitter transistor amplifier. Input
and output can be ground-referenced without any
biasing. The amplifier is noninverting because a
Figure 35. Simplified OTA Block Diagram
current flowing out of the emitter will also flow out of
the collector as a result of the current mirror shown in
Figure 35
.
Figure 36. a) Common Emitter Amplifier Using a Discrete Transistor; b) Common-E Amplifier Using the
OTA Portion of the OPA615
13
www.ti.com
V
-
Single Transistor
V+
V
I
V
O
(a) Common Collector Amplifier
(Emitter Follower)
V
O
100
OTA
V
I
(b) Common-C Amplifier for OTA
(Buffer)
OS
G
1
V
0.7V
OS
G
1
V
0
B
3
C
12
R
E
R
E
R
O
=
1
g
m
G =
1
1 +
1
g
m
x R
E
1
E
2
Inverting Gain
V
I
V
O
Single Transistor
(a) Common-Base
Amplifier
OTA
V
I
(b) Common-B Amplifier for OTA
OS
R
L
Noninverting Gain
V
several volts
R
E
V
O
R
L
R
E
B
E
3
2
C
12
G =
-
-
R
L
R
E
+
g
m
1
R
L
R
E
V
OS
0
V+
100
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
Figure 37
shows the Common-C amplifier. It consti-
Figure 38
shows the Common-B amplifier. This con-
tutes an open-loop buffer with low offset voltage. Its
figuration produces an inverting gain, and the input is
gain is approximately 1 and will vary with the load.
low-impedance. When a high impedance input is
needed, it can be created by inserting a buffer
amplifier (such as the BUF602) in series.
Figure 37. a) Common Collector Amplifier Using a
Discrete Transistor; b) Common-C Amplifier
Using the OTA Portion of the OPA615
Figure 38. a) Common Base Amplifier Using a
Discrete Transistor; b) Common-B Amplifier
Using the OTA Portion of the OPA615
14
www.ti.com
SAMPLING COMPARATOR
Offset (V)
+
Charge (pC)
C
H
Total (pF)
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
This innovative circuit achieves the high slew rate
representative of an open-loop design. In addition,
The OPA615 sampling comparator features a very
the acquisition slew current for a hold or storage
short switching (2.5ns) propagation delay and utilizes
capacitor is higher than standard diode bridge and
a new switching circuit architecture to achieve excel-
switch configurations, removing a main contributor to
lent speed and precision.
the limits of maximum sampling rate and input fre-
quency.
It provides high impedance inverting and noninverting
analog inputs, a high-impedance current source out-
The switching circuits in the OPA615 use current
put and a TTL-CMOS-compatible Hold Control Input.
steering (versus voltage switching) to provide im-
proved isolation between the switch and analog
The sampling comparator consists of an operational
sections. This design results in low aperture time
transconductance amplifier (OTA), a buffer amplifier,
sensitivity to the analog input signal, reduced power
and a subsequent switching circuit. This combination
supply and analog switching noise. Sample-to-hold
is subsequently referred to as the Sampling Oper-
peak switching charge injection is 40fC.
ational Transconductance Amplifier (SOTA). The
OTA and buffer amplifier are directly tied together at
The additional offset voltage or switching transient
the buffer outputs to provide the two identical
induced on a capacitor at the current source output
high-impedance
inputs
and
high
open-loop
by the switching charge can be determined by the
transconductance. Even a small differential input
following formula:
voltage multiplied with the high transconductance
results in an output current--positive or nega-
tive--depending upon the input polarity. This charac-
teristic is similar to the low or high status of a
The switching stage input is insensitive to the low
conventional comparator. The current source output
slew rate performance of the hold control command
features high output impedance, output bias current
and compatible with TTL/CMOS logic levels. With
compensation, and is optimized for charging a ca-
TTL logic high, the comparator is active, comparing
pacitor in DC restoration, nanosecond integrators,
the two input voltages and varying the output current
peak
detectors
and
S/H
circuits.
The
typical
accordingly. With TTL logic low, the comparator
comparator output current is
5mA and the output
output is switched off, showing a very high im-
bias current is minimized to typically
10
A in the
pedance to the hold capacitor.
sampling mode.
15
www.ti.com
APPLICATION INFORMATION
BASIC CONNECTIONS
SOTA
OTA
R
Q
R
Q
GND
9
3
4
Switching Stage
Sampling Comparator
(SC)
7
10
11
S/H In+
S/H In
-
Hold
Control
C
HOLD
Base
R
B
(25
to 200
)
2
12
Biasing
5
13
-
V
CC
+V
CC
-
5V
+5V
1
2.2
F
10nF
470pF
10nF
2.2
F
470pF
Solid Tantalum
+
+
R
Q
I
Q
Adjust
Collector
Emitter
R
Q
= 300
sets approximately
I
Q
= 13mA
(20
to
200
)
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
The OPA615 operates from
5V power supplies
Power-supply bypass capacitors should be located as
(
6.2V maximum). Absolute maximum is
6.5V . Do
close as possible to the device pins. Solid tantalum
not attempt to operate with larger power supply
capacitors are generally best. See
Board Layout
at
voltages or permanent damage may occur.
the end of the applications discussion for further
suggestions on layout.
Figure 39
shows the basic connections required for
operation. These connections are not shown in sub-
sequent circuit diagrams.
Figure 39. Basic Connections
16
www.ti.com
DC-RESTORE SYSTEM
H
CL
V
IN
C
HOLD
V
OUT
OTA
OPA615
10
11
7
4
2
3
12
100
100
SOTA
100
SOTA
H
CL
V
IN
C
HOLD
V
OUT
OTA
R
1
R
2
R
2
R
1
= V
IN
x
OPA615
3
12
2
4
7
10
11
100
100
100
G
+ )
R
2
R
1
7.5
BLANKING
BACK PORCH
100
89
70
59
41
30
11
0
W
Y
CY
GRN MAG
R
BLU BLK
FRONT PORCH
SYNC TIP
BREEZEWAY
COLOR BURST
LUMINANCE + CHROMINANCE
100
80
60
40
20
10
0
-
20
-
40
I
R
E
U
N
I
T
S
4
0
I
R
E
1
V
P
P
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
Figure
40
and
Figure
41
offer
two
possible
DC-restore systems using the OPA615.
Figure 41
implements a DC-restore function as a unity-gain
amplifier. As can be expected from its name, this
DC-restore circuit does not provide any amplification.
In applications where some amplification is needed,
consider using the circuit design shown in
Figure 40
.
Figure 41. DC Restoration of a Buffer Amplifier
For either of these circuits to operate properly, the
source impedance needs to be low, such as the one
provided by the output of a closed-loop amplifier or
buffer. Consider the video input signal shown in
Figure 42
, and the complete DC restoration system
shown in
Figure 40
. This signal is amplified by the
OTA section of the OPA615 by a gain of:
Figure 40. Complete DC Restoration System
Figure 42. NTSC Horizontal Scan Line
17
www.ti.com
Sample
0V
7.5
100
80
60
40
20
10
0
-
20
-
40
0V
Hold
H
C
L
O
u
t
p
u
t
V
o
l
t
a
g
e
I
n
p
u
t
V
o
l
t
a
g
e
I
R
E
U
N
I
T
S
7.5
100
80
60
40
20
10
0
-
20
-
40
I
R
E
U
N
I
T
S
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
The DC restoration is done by the SOTA section by
When the SOTA is sampling, it is charging or
sampling the output signal at an appropriate time.
discharging the C
HOLD
capacitor depending on the
The sampled section of the signal is then compared
level of the output signal sampled. The detail of an
to
a
reference
voltage
that
appears
on
the
appropriate timing is illustrated in
Figure 43
.
non-inverting input of the SOTA (pin 10), or ground in
Figure 40
.
Figure 43. DC-Restore Timing
18
www.ti.com
CLAMPED VIDEO/RF AMPLIFIER
OPA656
R
2
300
R
E
OTA
V
IN
R
B
V
OUT
H
CL
C
HOLD
Current Control
Non-Inverting
OPA615
100
2
3
4
7
11
10
12
100
V
REF
100
R
1
300
SOTA
C
B
SAMPLE-AND-HOLD AMPLIFIER
Hold /Track
50
100
150
100
OTA
2
12
3
4
300
50
C
HOLD
22pF
V
IN
10
11
7
300
V
OUT
SOTA
OPA615
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
Another circuit example for the preamplifier and the
clamp circuit is shown in
Figure 44
. The preamplifier
uses the wideband, low noise OPA656, again con-
figured in a gain of +2V/V. Here, the OPA656 has a
typical bandwidth of 200MHz with a settling time of
about 21ns (0.02%) and offers a low bias current
JFET input stage.
The video signal passes through the capacitor C
B
,
blocking the DC component. To restore the DC level
to the desired baseline, the OPA615 is used. The
inverting input (pin 11) is connected to a reference
voltage. During the high time of the clamp pulse, the
switching comparator (SOTA) will compare the output
of the op amp to the reference level. Any voltage
difference between those pins will result in an output
current that either charges or discharges the hold
capacitor, C
HOLD
. This charge creates a voltage
across the capacitor, which is buffered by the OTA.
Multiplied by the transconductance, the voltage will
cause a current flow in the collector, C, terminal of
Figure 44. Clamped Video/RF Amplifier
the OTA. This current will level-shift the OPA656 up
to the point where its output voltage is equal to the
reference voltage. This level-shift also closes the
control loop. Because of the buffer, the voltage
With a control propagation delay of 2.5ns and
across the C
HOLD
stays constant and maintains the
730MHz bandwidth, the OPA615 can be used advan-
baseline correction during the off-time of the clamp
tageously in a high-speed sample-and-hold amplifier.
pulse.
Figure 45
illustrates this configuration.
The external capacitor (C
HOLD
) allows for a wide
range of flexibility. By choosing small values, the
circuit can be optimized for a short clamping period or
with high values for a low droop rate. Another
advantage of this circuit is that small clamp peaks at
the output of the switching comparator are integrated
and do not cause glitches in the signal path.
Figure 45. Sample-and-Hold Amplifier
19
www.ti.com
Fast Pulse Peak Detector
+2.5
+1.5
+0.5
-
0.5
-
1.5
-
2.5
1MHz SAMPLE-AND- HOLD OF A 100kHz SINEWAVE
Time (1
s/div)
O
u
t
p
u
t
V
o
l
t
a
g
e
(
V
)
5
4
3
2
1
0
H
o
l
d
-
a
n
d
-
T
r
a
c
k
S
i
g
n
a
l
(
V
)
Hold Control
+V
OUT
50
100
150
100
100
50
+1
OTA
8
4
2
12
3
4
-
V
OUT
300
50
27pF
27pF
V
IN
10
11
7
BUF602
OPA615
SOTA
Phase Detector for Fast PLL Systems
Integrator for ns-Pulses
150
50
V
IN
Hold Control
27pF
100
820
1
F
620
50
O T A
V
OUT
12
2
3
4
11
10
7
SOTA
SOTA
f
R EF
f
IN
C
IN T
+5V
V
O UT
f
R EF
f
IN
f
O UT
f
O UT
= f
RE F
x N
V
OU T
f
IN
f
R EF
I
OU T
V
OU T
75
N
Phase
VCO
OTA
OPA615
75
75
11
10
3
2
12
4
100
7
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
To illustrate how the digitization is realized in the
Figure 45
circuit,
Figure 46
shows a 100kHz
A circuit similar to that shown in
Figure 47
(the
sinewave being sampled at a rate of 1MHz. The
integrator for ns-pulses) can be devised to detect and
output signal used here is the I
OUT
output driving a
isolate positive pulses from negative pulses. This
50
load.
circuit, shown in
Figure 48
, uses the OPA615 as well
as the BUF602. This circuit makes use of diodes to
isolate the positive-going pulses from the nega-
tive-going pulses and charge-different capacitors.
Figure 46. 1MHz Sample-and-Hold of a 100kHz
Figure 48. Fast Bipolar Peak Detector
Sine Wave
Figure 49
shows the circuit for a phase detector for
The integrator for ns-pulses using the OPA615
fast PLL systems. Given a reference pulse train f
REF
(shown in
Figure 47
) makes use of the fast
and a pulse train input signal f
IN
out of phase, the
comparator and its current-mode output. Placing the
SOTA of the OPA615 acts in this circuit as a
hold-control high, a narrow pulse charges the capaci-
comparator, either charging or discharging the ca-
tor, increasing the average output
voltage.
To
pacitor. This voltage is then buffered by the OTA and
minimize ripples at the inverting input and maximize
fed to the VCO.
the capacitor charge, a T-network is used in the
feedback path.
Figure 47. Integrator for ns-Pulses
Figure 49. Phase Detector For Fast PLL-Systems
20
www.ti.com
CORRELATED DOUBLE SAMPLER
V
OUT
V
IN1
OPA694
SOTA
7
10
11
4
V
HOLD1
27pF
402
50
100
100
300
300
402
402
402
O T A
12
2
3
V
IN2
SOTA
7
10
11
4
V
HOLD2
27pF
50
100
100
300
300
O T A
12
2
3
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
The signal coming from the CCD is applied to the two
sample-and-hold amplifiers, with their outputs con-
Noise is the limiting factor for the resolution in a CCD
nected to the difference amplifier. The timing diagram
system, where the kT/C noise is dominant (see
clarifies the operation (see
Figure 52
). At time t
1
, the
Figure 51
). To reduce this noise, imaging systems
sample and hold (S/H
1
) goes into the hold mode,
use a circuit called a Correlated Double Sampler
taking a sample of the reset level including the noise.
(CDS). The name comes from the double sampling
This voltage (V
RESET
) is applied to the noninverting
technique of the CCD charge signal. A CDS using
input of the difference amplifier. At time t
2
, the
two OPA615s and one OPA694 is shown in
Fig-
sample-and-hold (S/H
2
) will take a sample of the
ure 50
. The first sample (S
1
) is taken at the end of the
video level, which is V
RESET
V
VIDEO
. The output
reset period. When the reset switch opens again, the
voltage of the difference amplifier is defined by the
effective noise bandwidth changes because of the
equation V
OUT
= V
IN+
V
IN
. The sample of the reset
large difference in the switch R
ON
and R
OFF
resist-
voltage contains the kT/C noise, which is eliminated
ance. This difference causes the dominating kT/C
by the subtraction of the difference amplifier.
noise essentially to freeze in its last point.
The double sampling technique also reduces the
The other sample (S
2
) is taken during the video
white noise. The white noise is part of the reset
portion of the signal. Ideally, the two samples differ
voltage (V
RESET
) as well as of the video amplitude
only by a voltage corresponding to the transferred
(V
RESET
V
VIDEO
). With the assumption that the noise
charge signal. This is the video level minus the noise
of the noise of the second sample was unchanged
(
V).
from the instant of the first sample, the noise ampli-
tudes are the same and are correlated in time.
The CDS function will eliminate the kT/C noise as
Therefore, the noise can be reduced by the CDS
well as much of the 1/f and white noise.
function.
Figure 52
is a block diagram of a CDS circuit. Two
sample-and-hold amplifiers and one difference ampli-
fier constitute the correlated double sampler.
Figure 50. Correlated Double Sampler
21
www.ti.com
Reset Level
Simplified CCD Output Signal
NOTE: Signals are out of scale.
Video Level
S
2
S
1
V
kT/C -Noise
PP
S/H
1
V
IN
t
2
Video Hold
S
2
S
1
V
IN
t
1
t
2
Video Out
0V
S/H
2
V
RESET
V
RESET
-
V
VIDEO
Difference
Amplifier
V
OUT
= V
IN+
-
V
IN
-
t
1
Reset Hold
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
Figure 51. Improving SNR with Correlated Double Sampling
Figure 52. CDS - Circuit Concept
22
www.ti.com
BOARD LAYOUT GUIDELINES
INPUT AND ESD PROTECTION
External
Pin
+V
CC
-
V
CC
Internal
Circuitry
OPA615
SBOS299B FEBRUARY 2004 REVISED JULY 2005
d) Connections to other wideband devices on the
board may be made with short direct traces or
Achieving optimum performance with a high- fre-
through onboard transmission lines. For short
quency amplifier like the OPA615 requires careful
connections, consider the trace and the input to the
attention to printed circuit board (PCB) layout para-
next device as a lumped capacitive load. Relatively
sitics and external component types. Recommen-
wide traces (50mils to 100mils) should be used,
dations that will optimize performance include:
preferably with ground and power planes opened up
around them.
a) Minimize parasitic capacitance to any AC
ground for all of the signal I/O pins. Parasitic
e) Socketing a high-speed part like the OPA615 is
capacitance on the output and inverting input pins
not recommended. The additional lead length and
can cause instability; on the non-inverting input, it can
pin-to-pin capacitance introduced by the socket can
react with the source impedance to cause uninten-
create an extremely troublesome parasitic network
tional bandlimiting. To reduce unwanted capacitance,
which can make it almost impossible to achieve a
a window around the signal I/O pins should be
smooth, stable frequency response. Best results are
opened in all of the ground and power planes around
obtained by soldering the OPA615 directly onto the
those pins. Otherwise, ground and power planes
PCB.
should be unbroken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power
supply pins to high frequency 0.1
F decoupling
The OPA615 is built using a very high-speed, comp-
capacitors. At the device pins, the ground and power
lementary bipolar process. The internal junction
plane layout should not be in close proximity to the
breakdown voltages are relatively low for these very
signal I/O pins. Avoid narrow power and ground
small geometry devices. These breakdowns are re-
traces to minimize inductance between the pins and
flected in the
Absolute Maximum Ratings
table where
the decoupling capacitors. The power-supply connec-
an absolute maximum
6.5V supply is reported. All
tions should always be decoupled with these capaci-
device pins have limited ESD protection using internal
tors. An optional supply-decoupling capacitor across
diodes to the power supplies, as shown in
Figure 53
.
the two power supplies (for bipolar operation) will
improve 2nd-harmonic distortion performance. Larger
(2.2
F to 6.8
F) decoupling capacitors, effective at a
lower frequency, should also be used on the main
supply pins. These may be placed somewhat farther
from the device and may be shared among several
devices in the same area of the PCB.
c) Careful selection and placement of external
components will preserve the high frequency
performance of the OPA615. Resistors should be a
very low reactance type. Surface-mount resistors
Figure 53. Internal ESD Protection
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
These diodes also provide moderate protection to
Again, keep these leads and PCB trace length as
input overdrive voltages above the supplies. The
short as possible. Never use wirewound-type re-
protection diodes can typically support 30mA continu-
sistors in a high frequency application. Other network
ous current. Where higher currents are possible (for
components, such as noninverting input termination
example, in systems with
15V supply parts driving
resistors, should also be placed close to the package.
into the OPA615), current-limiting series resistors
should be added into the two inputs. Keep these
resistor values as low as possible since high values
degrade both noise performance and frequency re-
sponse.
23
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
OPA615ID
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA615IDG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA615IDR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA615IDRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco
Plan
-
The
planned
eco-friendly
classification:
Pb-Free
(RoHS)
or
Green
(RoHS
&
no
Sb/Br)
-
please
check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
Addendum-Page 1
IMPORTANT NOTICE
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