THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
WIDEBAND, FET-INPUT OPERATIONAL AMPLIFIER
1
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FEATURES
D
Gain Bandwidth Product: 180 MHz
D
Slew Rate: 100 V/
s
D
Maximum Input Bias Current: 100 pA
D
Input Voltage Noise: 5.4 nV/
Hz
D
Maximum Input Offset Voltage: 4 mV
D
Input Impedance: 10
9
|| 10 pF
D
Power Supply Voltage Range:
5 to
15 V
D
Unity Gain Stable
APPLICATIONS
D
Wideband Photodiode Amplifier
D
High-Speed Transimpedance Gain Stage
D
Test and Measurement Systems
D
Current-DAC Output Buffer
D
Active Filtering
D
High-Speed Signal Integrator
D
High-Impedance Buffer
DESCRIPTION
The THS4601 is a high-speed, FET-input operational
amplifier designed for applications requiring wideband
operation, high-input impedance, and high-power
supply voltages. By providing a 180-MHz gain-
bandwidth product,
15-V supply operation, and
100-pA input bias current, the THS4601 is capable of
wideband transimpedance gain and large output signal
swing simultaneously. Low current and voltage noise
allow amplification of extremely low-level input signals
while still maintaining a large signal-to-noise ratio.
The characteristics of the THS4601 ideally suit it for use
as a wideband photodiode amplifier. Photodiode output
current is a prime candidate for transimpedance
amplification, an application of which is illustrated in
Figure 1. Other potential applications include test and
measurement systems requiring high-input impedance,
digital-to-analog converter output buffering, high-speed
integration, and active filtering.
A SELECTION OF RELATED OPERATIONAL AMPLIFIER PRODUCTS
DEVICE
VS
(V)
BW
(MHz)
SLEW RATE
(V/
s)
VOLTAGE NOISE
(nV
Hz)
DESCRIPTION
OPA627
15
16
55
4.5
Unity-gain stable FET-input amplifier
OPA637
15
80
135
4.5
Gain of +5 stable FET-input amplifier
OPA655
5
400
290
6
Unity-gain stable FET-input amplifier
_
+
THS4601
CF
= 0.7 pF
RL = 1 k
60
65
70
75
80
85
90
95
100
105
0.1
1
10
100
Frequency MHz
T
ransimpedance Gain dB
100 k
TRANSIMPEDANCE BANDWIDTH
Diode Capacitance: 18 pF
3 dB Bandwidth: 4 MHz
Figure 1. Wideband Photodiode
Transimpedance Amplifier
RF
= 100 k
VBias
18 pF
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
2
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1
2
3
4
8
7
6
5
NC
IN
IN +
V
S
NC
V
S+
OUT
NC
THS4601
D AND DDA PACKAGE
(TOP VIEW)
NC No internal connection
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
DESCRIPTION
NC
1, 5, 8
These pins have no internal connection.
IN
2
Inverting input of the amplifier
IN+
3
Noninverting input of the amplifier
VS
4
Negative power supply
OUT
6
Output of the amplifier
VS+
7
Positive power supply
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
S+
16.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, V
S
16.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, I
O
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, V
ID
4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, T
J
150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, T
A:
C-suffix
0
C to 70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-suffix
40
C to 85
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
stg
65
C to 125
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds
300
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE AND ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE RANGE
PACKAGE MARKING
THS4601CD
SOIC surface mount
8D
0
C to 70
C
4601C
THS4601ID
SOIC surface mount
8D
40
C to 85
C
4601I
THS4601CDDA
SOIC surface mount with PowerPAD
8DDA
0
C to 70
C
4601C
THS4601IDDA
SOIC surface mount with PowerPAD
8DDA
40
C to 85
C
4601I
NOTE: The THS4601 is available taped and reeled. Add an R suffix to the device type when ordering (e.g., THS4601IDR).
PowerPAD is a trademark of Texas Instruments.
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
3
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electrical specifications: V
S
=
15 V: R
F
= 250
, R
L
= 1 k
and G = +2 (unless otherwise noted)
THS4601
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
25
C
25
C
0
C to
70
C
40
C
to 85
C
MIN/
MAX
UNIT
AC PERFORMANCE
G = +1, VO = 20 mVpp, RF = 0
440
Typ
MHz
G = +2, VO = 40 mVpp, RF = 62
95
Typ
MHz
Small-signal bandwidth
G = +5, VO = 100 mVpp, RF = 500
36
Typ
MHz
g
G = +10, VO = 200 mVpp,
RF = 1 k
18
Typ
MHz
Gain-bandwidth product
G > +10
180
Typ
MHz
Bandwidth for 0.1 dB flatness
G = +2, VO = 200 mVpp
5
Typ
MHz
Large-signal bandwidth
G = +5, VO = 10 Vpp
3
Typ
MHz
Slew rate, SR
G = +5, 10 V Step
100
Typ
V/
s
Rise/fall time, tr/tf
1.0 V Step
7
Typ
ns
Settling time t
0.01%
G = +5, VO = 5 V Step
170
Typ
ns
Settling time, ts
0.1%
G = +5, VO = 5 V Step
135
Typ
ns
Harmonic distortion
G = +2, f = 1 MHz, VO = 2Vpp
2nd Harmonic
RL = 100
65
Typ
dBc
2nd Harmonic
RL = 1 k
77
Typ
dBc
3rd Harmonic
RL = 100
73
Typ
dBc
3rd Harmonic
RL = 1 k
96
Typ
dBc
Input voltage noise, Vn
f > 10 kHz
5.4
Typ
nV/
Hz
Input current noise, In
f > 10 kHz
5.5
Typ
fA/
Hz
Differential gain (NTSC, PAL)
G = +2, RL = 150
0.02%
Typ
Differential phase (NTSC, PAL)
G = +2, RL = 150
0.08
Typ
_
DC PERFORMANCE
Open-loop voltage gain
G = 10, RL = 1 k
105
94
92
90
Min
dB
Input offset voltage, VIO
VCM = 0 V
1.0
4.0
4.5
5.0
Max
mV
Average offset voltage drift
VCM = 0 V
10
10
Typ
V/
_
C
Input bias current, IIB
VCM = 0 V
30
100
550
1100
Max
pA
Average bias current drift
VCM = 0 V
50
50
Typ
pA/
C
Input offset current, IIO
VCM = 0 V
2
100
200
300
Max
pA
Average offset current drift
VCM = 0 V
5
5
Typ
pA/
C
INPUT
Common-mode input range, VIC
13.0
12.6
to
12.0
12.5 to
11.9
12.4 to
11.8
Min
V
Common-mode rejection ratio, CMRR
110
100
95
90
Min
dB
Input impedance, Zid
Differential
109 || 3.5
Typ
|| pF
Input impedance, Zic
Common-mode
109 || 6.5
Typ
|| pF
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
4
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electrical specifications: V
S
=
15 V: R
F
= 250
, R
L
= 1k
and G = +2 (unless otherwise noted)
(continued)
THS4601
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
25
C
25
C
0
C to
70
C
40
C
to 85
C
MIN/
MAX
UNIT
OUTPUT
Voltage output swing
RL = 1 k
12.8 to
13.4
12.4 to
13.1
12.3 to
13.0
12.1 to
12.8
Min
V
Current output I
Sourcing
R
20
80
60
60
59
Min
mA
Current output, IO
Sinking
RL = 20
50
35
35
34
Min
mA
Closed-loop output impedance, Zo
G = +1, f = 1 MHz
0.1
Typ
POWER SUPPLY
Specified operating voltage
15
16.5
16.5
16.5
Max
V
Maximum quiescent current
10.0
11.5
11.7
12.0
Max
mA
Minimum quiescent current
10.0
8.5
8.3
8.0
Min
mA
Power supply rejection
+PSRR
115
90
88
86
Min
dB
Power supply rejection
PSRR
115
90
88
86
Min
dB
TEMPERATURE
Specified operating range, TA
40 to 85
Typ
C
Thermal resistance,
JA
Junction-to-ambient
8D: SO8
170
Typ
C/W
8DDA: SO8 with PowerPAD
66.6
Typ
C/W
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
5
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electrical specifications: V
S
=
5 V: R
F
= 250
, R
L
= 1 k
and G = +2 (unless otherwise noted)
THS4601
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
25
C
25
C
0
C to
70
C
40
C
to 85
C
MIN/
MAX
UNIT
AC PERFORMANCE
G = +1, VO = 20 mVpp
400
Typ
MHz
Small signal bandwidth
G = +2, VO = 40 mVpp
100
Typ
MHz
Small-signal bandwidth
G = +5, VO = 100 mVpp
50
Typ
MHz
G = +10, VO = 200 mVpp
18
Typ
MHz
Gain-bandwidth product
G > +10
180
Typ
MHz
Bandwidth for 0.1 dB flatness
G = +2, VO = 200 mVpp
5
Typ
MHz
Large-signal bandwidth
G = +5, VO = 5 Vpp
6
Typ
MHz
Slew rate, SR
G = +5, 5 V Step
100
Typ
V/
s
Rise/fall time, tr/tf
1.0 V Step
8
Typ
ns
Settling time t
0.01%
G = +5, VO = 2 V Step
140
Typ
ns
Settling time, ts
0.1%
G = +5, VO = 2 V Step
170
Typ
ns
Harmonic distortion
G = +2, f = 1 MHz, VO = 2Vpp
2nd Harmonic
RL = 100
74
Typ
dBc
2nd Harmonic
RL = 1 k
84
Typ
dBc
3rd Harmonic
RL = 100
79
Typ
dBc
3rd Harmonic
RL = 1 k
94
Typ
dBc
Input voltage noise, Vn
f > 10 kHz
5.4
Typ
nV/
Hz
Input current noise, In
f > 10 kHz
5.5
Typ
fA/
Hz
Differential gain (NTSC and PAL)
G = +2, RL = 150
0.02%
Typ
Differential phase (NTSC and PAL)
G = +2, RL = 150
0.08
Typ
_
DC PERFORMANCE
Open-loop voltage gain
G = 10, RL = 1 k
105
94
92
90
Min
dB
Input offset voltage, VIO
VCM = 0 V
1.0
4.0
4.5
5.0
Max
mV
Average offset voltage drift
VCM = 0 V
10
10
Typ
V/
_
C
Input bias current, IIB
VCM = 0 V
20
100
550
1100
Max
pA
Average bias current drift
VCM = 0 V
50
50
Typ
pA/
C
Input offset current, IIO
VCM = 0 V
1
100
200
300
Max
pA
Average offset current drift
VCM = 0 V
5
5
Typ
pA/
C
INPUT
Common-mode input range, VIC
2.2
2.7 to
2.0
2.6 to
1.9
2.5 to
1.8
Min
V
Common-mode rejection ratio, CMRR
110
100
95
90
Min
dB
Input impedance, Zid
Differential
109 || 3.5
Typ
|| pF
Input impedance, Zic
Common-mode
109 || 6.5
Typ
|| pF
OUTPUT
Voltage output swing
RL = 1 k
2.9 to
3.5
2.6 to
3.3
2.5 to
3.2
2.3 to
3.1
Min
V
Current output I
Sourcing
R
20
65
48
48
47
Min
mA
Current output, IO
Sinking
RL = 20
45
30
30
29
Min
mA
Closed-loop output impedance, Zo
G = +1, f = 1 MHz
0.1
Typ
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
6
www.ti.com
electrical specifications: V
S
=
5 V; R
F
= 250
, R
L
= 1 k
and G = +2 (unless otherwise noted)
(continued)
THS4601
PARAMETER
TEST CONDITIONS
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
25
C
25
C
0
C to
70
C
40
C
to 85
C
MIN/
MAX
UNIT
POWER SUPPLY
Specified operating voltage
5
16.5
16.5
16.5
Max
V
Maximum quiescent current
9.6
11.2
11.4
11.7
Max
mA
Minimum quiescent current
9.6
8.2
8.0
7.7
Min
mA
Power supply rejection
+PSRR
110
90
88
86
Min
dB
Power supply rejection
PSRR
110
90
88
86
Min
dB
TEMPERATURE
Specified operating range, TA
40 to 85
Typ
C
Thermal resistance,
JA
Junction-to-ambient
8D: SO8
170
Typ
C/W
8DDA: SO8 with PowerPAD
67
Typ
C/W
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
7
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Small-Signal Unity Gain Frequency Response
2
Large-Signal Unity Gain Frequency Response
3
Small-Signal Frequency Response, Gain = +2
4
Small-Signal Frequency Response, Gain = +5
5
Small-Signal Frequency Response, Gain = +10
6
Small-Signal Frequency Response, Gain = +100
7
Open-Loop Gain and Phase vs Frequency
8
Voltage Noise vs Frequency
9
Rejection Ratios vs Frequency
10
Closed-Loop Output Impedance vs Frequency
11
Large-Signal Pulse Response
12
Harmonic Distortion vs Frequency
13
Harmonic Distortion vs Output Voltage Swing
14
Slew Rate vs Output Voltage Step
15
Input Bias Current vs Input Common-Mode Range
16
Common-Mode Rejection Ratio vs Input Common-Mode Range
17
Open-Loop Gain vs Temperature
18
Input Bias Current vs Temperature
19
Input Offset Current vs Temperature
20
Offset Voltage vs Temperature
21
Quiescent Current vs Temperature
22
Output Current vs Temperature
23
Output Voltage Swing vs Temperature
24
Rejection Ratios vs Temperature
25
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
8
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TYPICAL CHARACTERISTICS
measurement conditions: T
A
= 25
C, R
L
= 1 k
, V
S
=
15 V (unless otherwise noted)
Figure 2
8
6
4
2
0
2
4
6
8
100 k
1 M
10 M
100 M
1 G
Gain
dB
Frequency Hz
SMALL-SIGNAL UNITY GAIN
FREQUENCY RESPONSE
Gain = 1,
RF = 0
,
RL = 1 k
,
PIN = 30 dBm
Figure 3
25
20
15
10
5
0
5
100 k
1 M
10 M
100 M
Gain
dB
LARGE-SIGNAL UNITY GAIN
FREQUENCY RESPONSE
Gain = 1,
RF = 0
,
RL = 1 k
,
PIN = 0 dBm
Frequency Hz
Figure 4
10
8
6
4
2
0
2
4
6
8
10
100 k
1 M
10 M
100 M
1 G
Gain
dB
Frequency Hz
SMALL-SIGNAL FREQUENCY RESPONSE,
GAIN = +2
Gain = 2,
RF = 62
,
RL = 1 k
,
PIN = 30 dBm
Figure 5
15
10
5
0
5
10
15
20
100 k
1 M
10 M
100 M
1 G
Gain
dB
Frequency Hz
SMALL-SIGNAL FREQUENCY RESPONSE,
GAIN = +5
Gain = 5,
RF = 500
,
RL = 1 k
,
PIN = 30 dBm
Figure 6
15
10
5
0
5
10
15
20
25
100 k
1 M
10 M
100 M
1 G
Gain
dB
Frequency Hz
SMALL-SIGNAL FREQUENCY RESPONSE,
GAIN = +10
Gain = 10,
RF = 1 k
,
RL = 1 k
,
PIN = 30 dBm
Figure 7
10
0
10
20
30
40
50
100 k
1 M
10 M
100 M
1 G
Gain
dB
Frequency Hz
SMALL-SIGNAL FREQUENCY RESPONSE,
GAIN = +100
Gain = 100,
RF = 5 k
,
RL = 1 k
,
PIN = 30 dBm
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
9
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TYPICAL CHARACTERISTICS
measurement conditions: T
A
= 25
C, R
L
= 1 k
, V
S
=
15 V (unless otherwise noted)
Figure 8
10
0
10
20
30
40
50
60
70
80
90
100
110
10
100
1 k
10 k 100 k 1 M 10 M 100 M 1 G
270
240
210
180
150
120
90
60
30
0
30
60
90
Frequency Hz
Gain
dB
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
Phase
Figure 9
0
10
20
30
40
50
60
10
100
1 k
10 k
100 k
Frequency Hz
V
oltage Noise
VOLTAGE NOISE
vs
FREQUENCY
nV/
Hz
Figure 10
0
20
40
60
80
100
120
100
1 k
10 k
100 k
1 M
10 M
100 M
Rejection Ratio
dB
REJECTION RATIOS
vs
FREQUENCY
CMRR
PSRR+
PSRR
Frequency Hz
Figure 11
0.01
0.1
1
10
100
100 k
1 M
10 M
100 M
Frequency Hz
Output Impedance
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
Figure 12
3
2
1
0
1
2
3
0
0.2
0.4
0.6
0.8
1
t Time
s
Output V
oltage
V
LARGE-SIGNAL PULSE RESPONSE
Figure 13
100
90
80
70
60
50
40
30
20
100 k
1 M
10 M
Frequency Hz
Distortion
dBc
HARMONIC DISTORTION
vs
FREQUENCY
2nd Harmonic
3rd Harmonic
Gain = 2,
RF = 250
,
RL = 1 k
,
VO = 2 VPP
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
10
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TYPICAL CHARACTERISTICS
measurement conditions: T
A
= 25
C, R
L
= 1 k
, V
S
=
15 V (unless otherwise noted)
Figure 14
100
95
90
85
80
75
70
65
60
55
50
0
2
4
6
8
10
12
Peak-to-Peak Output Swing V
Distortion
dBc
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
2nd Harmonic
3rd Harmonic
Gain = 2,
RF = 250
,
RL = 1 k
,
f = 1 MHz
Figure 15
60
70
80
90
100
110
120
130
0
5
10
15
20
SR
SR+
Output Voltage Step V
Slew Rate
SLEW RATE
vs
OUTPUT VOLTAGE STEP
s
V/
Gain = 5,
RL = 1 k
Figure 16
1
10
100
1 k
10 k
15
10
5
0
5
10
15
Input Common-Mode Range V
Input Bias Current
pA
INPUT BIAS CURRENT
vs
INPUT COMMON-MODE RANGE
Figure 17
0
20
40
60
80
100
120
15
10
5
0
5
10
15
Input Common-Mode Range V
CMRR
dB
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
Figure 18
92
94
96
98
100
102
104
106
108
110
40 20
0
20
40
60
80
100 120
Case Temperature
C
Open-Loop Gain
dB
OPEN-LOOP GAIN
vs
TEMPERATURE
Figure 19
1
10
100
1 k
10 k
100 k
40 20
0
20
40
60
80
100 120
IIB+
IIB
Case Temperature
C
Input Bias Current
pA
INPUT BIAS CURRENT
vs
TEMPERATURE
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
11
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TYPICAL CHARACTERISTICS
measurement conditions: T
A
= 25
C, R
L
= 1 k
, V
S
=
15 V (unless otherwise noted)
Figure 20
40
35
30
25
20
15
10
5
0
5
10
15
40 20
0
20
40
60
80
100 120
Case Temperature
C
Input Offset Current
pA
INPUT OFFSET CURRENT
vs
TEMPERATURE
Figure 21
0
0.50
1
1.50
2
2.50
40 20
0
20
40
60
80
100 120
Case Temperature
C
Offset V
oltage
mV
OFFSET VOLTAGE
vs
TEMPERATURE
Figure 22
9
9.2
9.4
9.6
9.8
10
10.2
40 20
0
20
40
60
80
100 120
Case Temperature
C
Quiescent Current
mA
QUIESCENT CURRENT
vs
TEMPERATURE
Figure 23
40
45
50
55
60
65
70
75
80
85
90
40 20
0
20
40
60
80
100 120
Sourcing Current
Sinking Current
Case Temperature
C
Output Current
mA
OUTPUT CURRENT
vs
TEMPERATURE
Figure 24
12.4
12.6
12.8
13
13.2
13.4
13.6
13.8
14
40 20
0
20
40
60
80
100 120
14
13.8
13.6
13.4
13.2
13
12.8
12.6
12.4
Case Temperature
C
Positive Output V
oltage Sling
V
OUTPUT VOLTAGE SWING
vs
TEMPERATURE
Negative Output V
oltage Swing
V
VO
VO+
Figure 25
70
75
80
85
90
95
100
105
110
115
120
125
130
40 20
0
20
40
60
80
100 120
PSRR+
CMRR
PSRR
Case Temperature
C
Rejection Ratios
dB
REJECTION RATIOS
vs
TEMPERATURE
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
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APPLICATION INFORMATION
introduction
The THS4601 is a high-speed, FET-input operational amplifier. The combination of its high frequency
capabilities and its DC precision make it a design option for a wide variety of applications, including test and
measurement, optical monitoring, transimpedance gain circuits, and high-impedance buffers. The applications
section of the data sheet discusses these particular applications in addition to general information about the
device and its features.
transimpedance fundamentals
FET-input amplifiers are often used in transimpedance applications because of their extremely high input
impedance. A transimpedance block accepts a current as an input and converts this current to a voltage at the
output. The high-input impedance associated with FET-input amplifiers minimizes errors in this process caused
by the input bias currents, I
IB
, of the amplifier.
designing the transimpedance circuit
Typically, design of a transimpedance circuit is driven by the characteristics of the current source that provides
the input to the gain block. A photodiode is the most common example of a capacitive current source that would
interface with a transimpedance gain block. Continuing with the photodiode example, the system designer
traditionally chooses a photodiode based on two opposing criteria: speed and sensitivity. Faster photodiodes
cause a need for faster gain stages, and more sensitive photodiodes require higher gains in order to develop
appreciable signal levels at the output of the gain stage.
These parameters affect the design of the transimpedance circuit in a few ways. First, the speed of the
photodiode signal determines the required bandwidth of the gain circuit. However, the required gain, based on
the sensitivity of the photodiode, limits the bandwidth of the circuit. Additionally, the larger capacitance
associated with a more sensitive signal source also detracts from the achievable speed of the gain block. The
dynamic range of the input signal also places requirements on the amplifier's dynamic range. Knowledge of the
source's output current levels, coupled with a desired voltage swing on the output, dictates the value of the
feedback resistor, R
F
. The transfer function from input to output is V
OUT
= I
IN
R
F
.
The large gain-bandwidth product of the THS4601 provides the capability for achieving both high trans-
impedance gain and wide bandwidth simultaneously. In addition, the high power supply rails provide the
potential for a very wide dynamic range at the output, allowing for the use of input sources which possess wide
dynamic range. The combination of these characteristics makes the THS4601 a design option for systems that
require transimpedance amplification of wideband, low-level input signals. A standard transimpedance circuit
is shown in Figure 26.
_
+
CF
RL
RF
VBias
Figure 26. Wideband Photodiode Transimpedance Amplifier
THS4601
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APPLICATION INFORMATION
designing the transimpedance circuit (continued)
As indicated, the current source typically sets the requirements for gain, speed, and dynamic range of the
amplifier. For a given amplifier and source combination, achievable performance is dictated by the following
parameters: the amplifier's gain-bandwidth product, the amplifier's input capacitance, the source capacitance,
the transimpedance gain, the amplifier's slew rate, and the amplifier's output swing. From this information, the
optimal performance of a transimpedance circuit using a given amplifier can be determined. Optimal is defined
here as providing the required transimpedance gain with a maximally flat frequency response.
For the circuit shown in Figure 26, all but one of the design parameters is known; the feedback capacitor must
be determined. Proper selection of the feedback capacitor prevents an unstable design, controls pulse
response characteristics, provides maximally flat transimpedance bandwidth, and limits broadband integrated
noise. The maximally flat frequency response results with C
F
calculated as shown in equation 1, where C
F
is
the feedback capacitor, R
F
is the feedback resistor, C
S
is the total source capacitance (including amplifier input
capacitance and parasitic capacitance at the inverting node), and GBP is the gain-bandwidth product of the
amplifier in hertz.
C
F
+
1
p
R
F
GBP
)
1
p
R
F
GBP
2
)
4C
S
p
R
F
GBP
2
Once the optimal feedback capacitor has been selected, the transimpedance bandwidth can be calculated with
equation 2.
F
3 dB
+
GBP
2
p
R
F
C
S
)
C
F
_
+
CIDIFF
CICM
CP
RF
CF
CD
IDIODE
NOTE: The total source capacitance is the sum of several distinct capacitances.
C
s
= C
ICM
+ C
IDIFF
+ C
P
+ C
D
Where: C
ICM
is the common-mode input capacitance.
C
IDIFF
is the differential input capacitance.
C
D
is the diode capacitance.
C
P
is parasitic capacitance at the inverting node.
Figure 27. Transimpedance Analysis Circuit
(1)
(2)
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
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APPLICATION INFORMATION
designing the transimpedance circuit (continued)
The feedback capacitor provides a pole in the noise gain of the circuit, counteracting the zero in the noise gain
caused by the source capacitance. The pole is set such that the noise gain achieves a 20 dB per decade
rate-of-closure with the open-loop gain response of the amplifier, resulting in a stable circuit. As indicated, the
formula given provides the feedback capacitance for maximally flat bandwidth. Reduction in the value of the
feedback capacitor can increase the signal bandwidth, but this occurs at the expense of peaking in the AC
response.
20 dB/Decade
Rate-of-Closure
GBP
20 dB/
Decade
20 dB/
Decade
AOL
Noise Gain
0
Gain
Zero
Pole
f
Figure 28. Transimpedance Circuit Bode Plot
The performance of the THS4601 has been measured for a variety of transimpedance gains with a variety of
source capacitances. The achievable bandwidths of the various circuit configurations are summarized
numerically in the table. The frequency responses are presented in the Figures 27, 28, and 29.
Note that the feedback capacitances do not correspond exactly with the values predicted by the equation. They
have been tuned to account for the parasitic capacitance of the feedback resistor (typically 0.2 pF for 0805
surface mount devices) as well as the additional capacitance associated with the PC board. The equation
should be used as a starting point for the design, with final values for C
F
optimized in the laboratory.
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
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APPLICATION INFORMATION
designing the transimpedance circuit (continued)
Table 1. Transimpedance Performance Summary for Various Configurations
SOURCE CAPACITANCE
(pF)
TRANSIMPEDANCE GAIN
(
)
FEEDBACK CAPACITANCE
(pF)
3 dB FREQUENCY
(MHz)
18
10k
2.2
10.4
18
100k
0.6
3.3
18
1M
0
1.1
47
10k
3.3
7.6
47
100k
0.6
2.8
47
1M
0
0.88
100
10k
3.9
5.9
100
100k
1.5
1.3
100
1M
0
0.62
220
10k
5.6
3.8
220
100k
1.8
1.1
220
1M
0.4
0.36
Figure 29
65
70
75
80
85
90
10 k
100 k
1 M
10 M
100 M
Frequency Hz
T
ransimpedance Gain
dB
10 k
TRANSIMPEDANCE BANDWIDTH
FOR VARIOUS SOURCE CAPACITANCES
CS = 18 pF, CF = 2.2 pF
CS = 47 pF,
CF = 3.3 pF
CS = 100 pF,
CF = 3.9 pF
CS = 220 pF,
CF = 5.6 pF
Figure 30
60
65
70
75
80
85
90
95
100
105
10 k
100 k
1 M
10 M
CS = 18 pF,
CF = 0.6 pF
CS = 47 pF,
CF = 0.6 pF
CS = 100 pF,
CF = 1.5 pF
CS = 220 pF,
CF = 1.8 pF
Frequency Hz
T
ransimpedance Gain
dB
100 k
TRANSIMPEDANCE BANDWIDTH
FOR VARIOUS SOURCE CAPACITANCES
Figure 31
90
95
100
105
110
115
120
125
130
10 k
100 k
1 M
10 M
CS = 18 pF, CF = 0
CS = 47 pF,
CF = 0
CS = 100 pF,
CF = 0
CS = 220 pF,
CF = 0.4 pF
Frequency Hz
T
ransimpedance Gain
dB
1 M
TRANSIMPEDANCE BANDWIDTH
FOR VARIOUS SOURCE CAPACITANCES
measuring transimpedance bandwidth
While there is no substitute for measuring the performance of a particular circuit under the exact conditions that
are used in the application, the complete system environment often makes measurements harder. For
transimpedance circuits, it is difficult to measure the frequency response with traditional laboratory equipment
because the circuit requires a current as an input rather than a voltage. Also, the capacitance of the current
source has a direct effect on the frequency response. A simple interface circuit can be used to emulate a
capacitive current source with a network analyzer. With this circuit, transimpedance bandwidth measurements
are simplified, making amplifier evaluation easier and faster.
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
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APPLICATION INFORMATION
measuring transimpedance bandwidth (continued)
VS
50
50
RS
C1
C2
Network Analyzer
IO
I
O
V
S
+
1
2R
S
1
)
C
1
C
2
(above the pole frequency)
NOTE: This interface network creates a capacitive, constant current source from a network analyzer and properly terminates the network analyzer
at high frequencies.
Figure 32. Emulating a Capacitive Current Source With a Network Analyzer
The transconductance transfer function of the interface circuit is
I
O
Vs
(s)
+
s
2R
S
1
)
C
1
C
2
s
)
1
2R
S
C
1
)
C
2
.
This transfer function contains a zero at DC and a pole at s
+
1
2R
S
C
1
)
C
2
. The transconductance is
constant at
1
2R
S
1
)
C
1
C
2
, above the pole frequency, providing a controllable AC current source. This circuit
also properly terminates the network analyzer with 50
at high frequencies. The second requirement for this
current source is to provide the desired output impedance, emulating the output impedance of a photodiode or
other current source. The output impedance of this circuit is given by
Z
O
(s)
+
C
1
)
C
2
C
1
C
2
s
)
1
2R
s
C
1
)
C
2
s s
)
1
2R
s
C
1
.
Assuming C
1
>> C
2
, the equation reduces to Z
O
[
1
sC
2
,
giving the appearance of a capacitive source at higher
frequency.
Capacitor values should be chosen to satisfy two requirements. First, C
2
should represent the anticipated
capacitance of the true source. C
1
should then be chosen such that the corner frequency of the
transconductance network is much less than the transimpedance bandwidth of the circuit. Choosing this corner
frequency properly leads to more accurate measurements of the transimpedance bandwidth. If the interface
circuit's corner frequency is too close to the bandwidth of the circuit, determining the power level in the flatband
is difficult. A decade or more of flat bandwidth provides a good basis for determining the proper transimpedance
bandwidth.
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
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APPLICATION INFORMATION
alternative transimpedance configurations
Other transimpedance configurations are possible. Three possibilities are shown below.
The first configuration is a slight modification of the basic transimpedance circuit. By splitting the feedback
resistor, the feedback capacitor value becomes more manageable and easier to control. This type of
compensation scheme is useful when the feedback capacitor required in the basic configuration becomes so
small that the parasitic effects of the board and components begin to dominate the total feedback capacitance.
By reducing the resistance across the capacitor, the capacitor value can be increased. This mitigates the
dominance of the parasitic effects.
_
+
CF
RF2
RL
RF1
VBias
NOTE: Splitting the feedback resistor enables use of a larger, more manageable feedback
capacitor.
Figure 33. Alternative Transimpedance Configuration #1
The second configuration uses a resistive T-network to achieve very high transimpedance gains using relatively
small resistor values. This topology can be very useful when the desired transimpedance gain exceeds the
value of available resistors. The transimpedance gain is given by equation 3.
R
EQ
+
R
F1
1
)
R
F2
R
F3
_
+
CF
RF2
RL
RF1
VBias
RF3
NOTE: A resistive T-network enables high transimpedance gain with reasonable resistor values.
Figure 34. Alternative Transimpedance Configuration #2
(3)
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
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APPLICATION INFORMATION
alternative transimpedance configurations (continued)
The third configuration uses a capacitive T-network to achieve fine control of the compensation capacitance.
The capacitor C
F3
can be used to tune the total effective feedback capacitance to a very fine degree. This circuit
behaves the same as the basic transimpedance configuration, with the effective C
F
given by equation 4.
1
C
FEQ
+
1
C
F1
1
)
C
F3
C
F2
_
+
CF2
RL
RF
VBias
CF1
CF3
NOTE: A capacitive T-network enables fine control of the effective
feedback capacitance using relatively large capacitor values.
Figure 35. Alternative Transimpedance Configuration #3
summary of key decisions in transimpedance design
The following is a quick, simplified process for basic transimpedance circuit design. This process gives a quick
start to the design process, though it does ignore some aspects that may be critical to the circuit.
Step 1:
Determine the capacitance of the source.
Step 2:
Calculate the total source capacitance, including the amplifier input capacitance, C
ICM
and C
IDIFF
.
Step 3:
Determine the magnitude of the possible current output from the source, including the minimum
signal current anticipated and maximum signal current anticipated.
Step 4:
Choose a feedback resistor value such that the input current levels create the desired output signal
voltages, and ensure that the output voltages can accommodate the dynamic range of the input
signal.
Step 5:
Calculate the optimum feedback capacitance using equation 1.
Step 6:
Calculate the bandwidth given the resulting component values.
Step 7:
Evaluate the circuit to see if all design goals are satisfied.
(4)
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
19
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APPLICATION INFORMATION
selection of feedback resistors
Feedback resistor selection can have a significant effect on the performance of the THS4601 in a given
application, especially in configurations with low closed-loop gain. If the amplifier is configured for unity gain,
the output should be directly connected to the inverting input. Any resistance between these two points interacts
with the input capacitance of the amplifier and causes an additional pole in the frequency response. For
non-unity gain configurations, low resistances are desirable for flat frequency response. However, care must
be taken not to load the amplifier too heavily with the feedback network if large output signals are expected. In
most cases, a tradeoff will be made between the frequency response characteristics and the loading of the
amplifier. For a gain of 2, a 250
feedback resistor is a suitable operating point from both perspectives.
If resistor values are chosen too large, the THS4601 is subject to oscillation problems. For example, an inverting
amplifier configuration with a 1-k
gain resistor and a 1-k
feedback resistor develops an oscillation due to the
interaction of the large resistors with the input capacitance. In low gain configurations, avoid feedback resistors
this large or anticipate using an external compensation scheme to stabilize the circuit.
overdrive recovery
The THS4601 has an overdrive recovery period when the output is driven close to one power supply rail or the
other. The overdrive recovery time period is dependent upon the magnitude of the overdrive and whether the
output is driven towards the positive or the negative power supply. The four graphs shown here depict the
overdrive recovery time in two cases, an attempted 28 V
PP
signal on the output and an attempted 30 V
PP
signal
on the output. Note that in both of these cases, the output does not achieve these levels as the output voltage
swing is limited to less than these values, but these values are representative of the desired signal swing on
the output for the given inputs. As shown in the figures, the recovery period increases as the magnitude of the
overdrive increases, with the worst case recovery occurring with the negative rail. The recovery times are
summarized in Table 2.
Table 2. Overdrive Recovery Characteristics
VOLTAGE RAIL
IDEAL OUTPUT SWING
(VPP)
OVERDRIVE RECOVERY TIME
(ns)
+VS
28
320
VS
28
340
+VS
30
540
VS
30
680
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
20
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APPLICATION INFORMATION
overdrive recovery (continued)
Figure 36
3
20
15
10
5
0
5
10
15
20
0
1
2
3
4
4
2
1
0
1
2
3
4
Time
s
Output V
oltage
V
RISING EDGE OVERDRIVE RECOVERY
Input V
oltage
V
Gain = 5,
VIN = 5.57 VPP,
Recovery Time = 340 ns
Input
Output
Figure 37
3
20
15
10
5
0
5
10
15
20
0
1
2
3
4
4
2
1
0
1
2
3
4
Time
s
Output V
oltage
V
FALLING EDGE OVERDRIVE RECOVERY
Input V
oltage
V
Gain = 5,
VIN = 5.57 VPP,
Recovery Time = 320 ns
Input
Output
Figure 38
3
20
15
10
5
0
5
10
15
20
0
1
2
3
4
4
2
1
0
1
2
3
4
Time
s
Output V
oltage
V
FALLING EDGE OVERDRIVE RECOVERY
Input V
oltage
V
Gain = 5,
VIN = 6 VPP,
Recovery Time = 540 ns
Input
Output
Figure 39
3
20
15
10
5
0
5
10
15
20
0
1
2
3
4
4
2
1
0
1
2
3
4
Time
s
Output V
oltage
V
RISING EDGE OVERDRIVE RECOVERY
Input V
oltage
V
Gain = 5,
VIN = 6 VPP,
Recovery Time = 680 ns
Input
Output
high frequency continuous wave amplification
When presented with high frequency sinusoids in low-gain configurations (G < 5), the THS4601 experiences
a relatively large differential input voltage between the two input terminals of the amplifier. As this differential
input voltage increases, the internal slew-boosting circuitry can cause some transistors in the signal path to
enter the cutoff region of operation. As the derivative of the signal changes signs, these transistors suffer from
a short recovery time period, generating appreciable levels of distortion. This behavior is depicted in the graph
Harmonic Distortion vs Frequency. At 2 MHz with a 2 V
PP
output signal, the distortion rises significantly. For most
high-gain configurations including transimpedance applications, this phenomena is not problematic.
slew rate performance with varying input step amplitude and rise/fall time
Some FET input amplifiers exhibit the peculiar behavior of having a larger slew rate when presented with smaller
input voltage steps and slower edge rates due to a change in bias conditions in the input stage of the amplifier
under these circumstances. This phenomena is most commonly seen when FET input amplifiers are used as
voltage followers. As this behavior is typically undesirable, the THS4601 has been designed to avoid these
issues. Larger amplitudes lead to higher slew rates, as would be anticipated, and fast edges do not degrade
the slew rate of the device.
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
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APPLICATION INFORMATION
power dissipation and thermal characteristics
The THS4601 does not incorporate automatic thermal shutoff protection, so the designer must take care to
ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may
result if the absolute maximum junction temperature of 150
C is exceeded.
The thermal characteristics of the device are dictated by the package and the PC board. Maximum power
dissipation for a given package can be calculated using the following formula.
P
Dmax
+
TmaxTA
q
JA
Where:
P
Dmax
is the maximum power dissipation (W)
T
max
is the absolute maximum junction temperature (
C)
T
A
is the ambient temperature (
C)
JA
is the thermal coefficient from the silicon junctions to the ambient air (
C/W)
For systems where heat dissipation is more critical, the THS4601 is offered in an 8-pin SOIC with PowerPAD.
The thermal coefficient for the SOIC PowerPAD is substantially improved over the traditional SOIC. Maximum
power dissipation levels are depicted in the graph for the two packages. The data for the 8DDA package
assumes a board layout that follows the PowerPAD layout guidelines.
0
0.5
1
1.5
2
2.5
3
40
20
0
20
40
60
80
8DDA Package
8D Package
JA = 170
C/W for 8D,
JA = 66.6
C/W for 8DDA
Ambient Temperature
C
Maximum Power Dissipation
W
MAXIMUM POWER DISSIPATION
vs
TEMPERATURE
Figure 40
When determining whether or not the device satisfies the maximum power dissipation requirement, it is
important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times,
this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power
dissipation can provide visibility into a possible problem.
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
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APPLICATION INFORMATION
PC board layout guidelines
Achieving optimum performance with a high frequency amplifier requires careful attention to board layout
parasitics and external component selection. Recommendations that optimize performance include the
following.
D
Use of a ground plane--It is highly recommended that a ground plane be used on the board to provide all
components with a low impedance connection to ground. However, the ground plane should be cleared
around the amplifier inputs and outputs to minimize parasitic capacitance. A solid ground plane is
recommended wherever possible.
D
Proper power supply decoupling--A 6.8
F tantalum capacitor and a 0.1
F ceramic capacitor should be
used on each power supply node. Good performance is possible if the 6.8
F capacitor is shared among
several amplifiers, but each amplifier should have a dedicated 0.1
F capacitor for each supply. The 0.1
F capacitor should be placed as close to the power supply pins as possible. As the distance from the device
increases, the trace inductance rises and decreases the effectiveness of the capacitor. A good design has
less than 2.5 mm separating the ceramic capacitor and the power supply pin. The tantalum capacitors can
be placed significantly further away from the device.
D
Avoid sockets--Sockets are not recommended for high-speed amplifiers. The lead inductance associated
with the socket pins often leads to stability problems. Direct soldering to a printed-circuit board yields the
best performance.
D
Minimize trace length and place parts compactly--Shorter traces minimize stray parasitic elements of the
design and lead to better high-frequency performance.
D
Use of surface mount passive components--Surface mount passive components are recommended due
to the extremely low lead inductance and the small component footprint. These characteristics minimize
problems with stray series inductance and allow for a more compact circuit layout. Compact layout reduces
both parasitic inductance and capacitance in the design.
D
Minimize parasitic capacitance on the signal input and output pins--Parasitic capacitance on the input and
output pins can degrade high frequency behavior or cause instability in the circuit. Capacitance on the
inverting input or the output is a common cause of instability in high performance amplifiers, and
capacitance on the noninverting input can react with the source impedance to cause unintentional
band-limiting. To reduce unwanted capacitance around these pins, a window should be opened up in the
signal/power layers that are underneath those pins. Power and ground planes should otherwise be
unbroken.
PowerPAD design considerations
The THS4601 is available in a thermally-enhanced PowerPAD package. This package is constructed using a
downset leadframe upon which the die is mounted (see Figure 39). This arrangement results in the lead frame
exposed as a thermal pad on the underside of the package. Because this thermal pad has direct thermal contact
with the die, excellent thermal performance can be achieved by providing a good thermal path away from the
thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device. The
PowerPAD is electrically insulated from the amplifier circuitry, but connection to the ground plane is
recommended due to the high thermal mass typically associated with a ground plane.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
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APPLICATION INFORMATION
PowerPAD design considerations (continued)
DIE
Side View (a)
End View (b)
Bottom View (c)
DIE
Thermal
Pad
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 41. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 42. PowerPAD PCB Etch and Via Pattern
PowerPAD PCB LAYOUT CONSIDERATIONS
1.
Prepare the PCB with a top side etch pattern as shown in Figure 42. There should be etch for the leads as
well as etch for the thermal pad.
2.
Place five vias in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes does not occur during reflow.
3.
Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the IC. These additional vias may be larger than the 13-mil diameter vias
directly under the thermal pad. Larger vias are permissible here because they are not susceptible to solder
wicking as the vias underneath the device.
4.
Connect all vias to the internal ground plane for best thermal characteristics
5.
When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the PowerPAD package should make their connection to the internal ground plane with a
complete connection around the entire circumference of the plated-through hole.
6.
The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7.
Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8.
With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow
operation as any standard surface-mount component. This results in a part that is properly installed.
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
24
www.ti.com
APPLICATION INFORMATION
evaluation module and applications support
An evaluation board is available for quick laboratory verification of performance. An evaluation module can be
ordered from Texas Instruments' web site (www.ti.com) or from your local TI sales representative. Applications
support is also available for designers. The Product Information Center (PIC) can put designers in touch with
applications engineers at Texas Instruments. The PIC be contacted via the web site as well.
additional reference material
D
PowerPAD Made Easy, application brief, Texas Instruments Literature Number SLMA004.
D
PowerPAD Thermally Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002.
D
Noise Analysis of FET Transimpedance Amplifiers, application bulletin, Texas Instruments Literature
Number SBOA060.
D
Tame Photodiodes With Op Amp Bootstrap, application bulletin, Texas Instruments Literature Number
SBBA002.
D
Designing Photodiode Amplifier Circuits With OPA128, application bulletin, Texas Instruments Literature
Number SBOA061.
D
Photodiode Monitoring With Op Amps, application bulletin, Texas Instruments Literature Number
SBOA035.
D
Comparison of Noise Performance Between a FET Transimpedance Amplifier and a Switched Integrator,
Application Bulletin, Texas Instruments Literature Number SBOA034.
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
25
www.ti.com
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN
(4,80)
0.189
0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1
4
8
5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0
8
Gage Plane
A
0.004 (0,10)
0.010 (0,25)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
THS4601
SLOS388B OCTOBER 2001 REVISED JUNE 2002
26
www.ti.com
MECHANICAL DATA
DDA (SPDSOG8)
Power PAD
t
PLASTIC SMALL-OUTLINE
6,20
5,84
3,81
3,99
4202561/A 02/01
8
5
1
4
1,68 MAX
0,13
4,98
4,80
0
8
0,41
0,89
0,25
0,20 NOM
Seating Plane
0,49
0,35
0,03
1,40
1,55
Thermal Pad
(See Note D)
M
0,10
0,10
1,27
Gage Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
PowerPAD is a trademark of Texas Instruments.
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2002, Texas Instruments Incorporated
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