OPA650
1
FEATURES
q
LOW POWER: 50mW
q
UNITY GAIN STABLE BANDWIDTH:
560MHz
q
LOW HARMONICS: 77dBc at 5MHz
q
FAST SETTLING TIME: 20ns to 0.01%
q
LOW INPUT BIAS CURRENT: 5
A
q
DIFFERENTIAL GAIN/PHASE ERROR:
0.01%/0.03
q
HIGH OUTPUT CURRENT: 85mA
DESCRIPTION
The OPA650 is a low power, wideband voltage feed-
back operational amplifier. It features a high band-
width of 560MHz as well as a 12-bit settling time of
only 20ns. The low distortion allows its use in commu-
nications applications, while the wide bandwidth and
true differential input stage make it suitable for use in
a variety of active filter applications. Its low distortion
gives exceptional performance for telecommunica-
tions, medical imaging and video applications.
The OPA650 is internally compensated for unity-gain
stability. This amplifier has a fully symmetrical differ-
ential input due to its "classical" operational amplifier
circuit architecture. Its unusual combination of speed,
accuracy and low power make it an outstanding choice
for many portable, multi-channel and other high speed
applications, where power is at a premium.
The OPA650 is also available in dual (OPA2650) and
quad (OPA4650) configurations.
Wideband, Low Power Voltage Feedback
OPERATIONAL AMPLIFIER
OPA650
APPLICATIONS
q
HIGH RESOLUTION VIDEO
q
BASEBAND AMPLIFIER
q
CCD IMAGING AMPLIFIER
q
ULTRASOUND SIGNAL PROCESSING
q
ADC/DAC GAIN AMPLIFIER
q
ACTIVE FILTERS
q
HIGH SPEED INTEGRATORS
q
DIFFERENTIAL AMPLIFIER
OPA650
OPA650
Current
Mirror
Output
Stage
C
C
Inverting
Input
Non-Inverting
Input
+V
S
Output
V
S
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111
Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1994 Burr-Brown Corporation
PDS-1264F
Printed in U.S.A. March, 1998
SBOS041
2
OPA650
NOTES: (1) An asterisk (
T
) specifies the same value as the grade to the left. (2) Frequency response can be strongly influenced by PC board parasitics. The OPA650
is nominally compensated assuming 2pF parasitic load. The demonstration boards show low parasitic layouts for the different package styles.
SPECIFICATIONS
At T
A
= +25
C, V
S
=
5V, R
L
= 100
, and R
FB
= 402
,
unless otherwise noted. R
FB
= 25
for a gain of +1.
OPA650P, U, N
OPA650UB, NB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
FREQUENCY RESPONSE
Closed-Loop Bandwidth
(2)
G = +1
560
T
(1)
MHz
G = +2
140
T
MHz
G = +5
37
T
MHz
G = +10
18
T
MHz
Gain Bandwidth Product
180
T
MHz
Slew Rate
G = +1, 2V Step
240
T
V/
s
Over Specified Temperature
220
T
V/
s
Rise Time
0.2V Step
1
T
ns
Fall Time
0.2V Step
1
T
ns
Settling Time
0.01%
G = +1, 2V Step
19.6
T
ns
0.1%
G = +1, 2V Step
10.2
T
ns
1%
G = +1, 2V Step
6.3
T
ns
Spurious Free Dynamic Range
G = +1, f = 5.0 MHz, V
O
= 2Vp-p
R
L
= 100
73
T
dBc
R
L
= 200
77
T
dBc
Differential Gain
G = +1, NTSC, V
O
= 1.4Vp, R
L
= 150
0.01
T
%
Differential Phase
G = +1, NTSC, V
O
= 1.4Vp, R
L
= 150
0.03
T
Degrees
Bandwidth for 0.1dB Gain Flatness
G = +2
25
T
MHz
INPUT OFFSET VOLTAGE
Input Offset Voltage
1
5
0.6
2.5
mV
Average Drift
3
T
V/
C
Power Supply Rejection (+V
S
)
|V
S
| = 4.5V to 5.5V
60
76
70
T
dB
(V
S
)
47
53
50
T
dB
INPUT BIAS CURRENT
Input Bias Current
V
CM
= 0V
5
20
T
10
A
Over Temperature
30
20
A
Input Offset Current
V
CM
= 0V
0.5
1
0.2
0.5
A
Over Temperature
3
2
A
NOISE
Input Voltage Noise
Noise Density, f = 100Hz
43
T
nV/
Hz
f = 10kHz
9.4
T
nV/
Hz
f = 1MHz
8.4
T
nV/
Hz
f = 1MHz to 100MHz
8.4
T
nV/
Hz
Integrated Noise, BW = 10Hz to 100MHz
84
T
Vrms
Input Bias Current Noise
Current Noise Density, f = 0.1MHz to 100MHz
1.2
T
pA/
Hz
Noise Figure (NF)
R
S
= 10k
4
T
dB
R
S
= 50
19.5
T
dB
INPUT VOLTAGE RANGE
Common-Mode Input Range
2.8
T
V
Over Specified Temperature
2.2
T
V
Common-Mode Rejection
V
CM
=
0.5V
65
90
70
T
dB
INPUT IMPEDANCE
Differential
15 || 1
T
k
|| pF
Common-Mode
16 || 1
T
M
|| pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain
V
O
=
2V, R
L
= 100
45
51
46
T
dB
Over Specified Temperature
V
O
=
2V, R
L
= 100
43
44
dB
OUTPUT
Voltage Output
Over Specified Temperature
No Load
2.2
3.0
2.4
T
V
R
L
= 250
2.2
2.5
2.4
T
V
R
L
= 100
2.0
2.3
2.2
T
V
Current Output, Sourcing
75
110
T
T
mA
Over Specified Temperature
65
T
mA
Current Output, Sinking
65
85
T
T
mA
Over Specified Temperature
35
T
mA
Short Circuit Current
150
T
mA
Output Resistance
0.1MHz, G = +1
0.08
T
POWER SUPPLY
Specified Operating Voltage
5
T
V
Derated Voltage Range
4.5
5.5
T
T
V
Quiescent Current
5.1
7.75
5.1
6.5
mA
Over Specified Temperature
8.75
7.5
mA
TEMPERATURE RANGE
Specification: P, U, N, UB, NB
40
+85
T
T
C
Thermal Resistance,
JA
P
8-Pin DIP
100
T
C/W
U
SO-8
125
T
C/W
N
SOT23-5
150
T
C/W
OPA650
3
1
2
3
5
4
+V
S
Input
Output
V
S
+Input
1
2
3
4
8
7
6
5
NC
+V
S
Output
NC
NC
Input
+Input
V
S
Supply ...............................................................................................
5.5V
Internal Power Dissipation .................................. See Thermal Conditions
Differential Input Voltage ..................................................................
1.2V
Input Voltage Range ............................................................................
V
S
Storage Temperature Range: P, U, UB, N, NB ............ 40
C to +125
C
Lead Temperature (soldering, 10s) .............................................. +300
C
(soldering, SOIC 3s) ....................................... +260
C
Junction Temperature (T
J
) ............................................................ +175
C
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Top View
DIP/SO-8
SOT23-5
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or
licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support
devices and/or systems.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci-
fications.
PACKAGE
DRAWING
TEMPERATURE
PACKAGE
ORDERING
PRODUCT
PACKAGE
NUMBER
(1)
RANGE
MARKING
(2)
NUMBER
(3)
OPA650U
SO-8 Surface Mount
182
40
C to +85
C
OPA650U
OPA650U
OPA650UB
SO-8 Surface Mount
182
40
C to +85
C
OPA650UB
OPA650UB
OPA650N
5-pin SOT23-5
331
40
C to +85
C
A50
OPA650N-250
OPA650N-3k
OPA650NB
5-pin SOT23-5
331
40
C to +85
C
A50B
OPA650NB-250
OPA650NB-3k
OPA650P
8-Pin Plastic DIP
006
40
C to +85
C
OPA650P
OPA650P
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) The "B" grade of the SO-8 package
will be marked with a "B" by pin 8. The "B" grade of the SOT23-5 will be marked with a "B" near pins 3 and 4. (3) The SOT23-5 is only available on a 7" tape and reel
(e.g. ordering 250 pieces of "OPA650N-250" will get a single 250 piece tape and reel. Ordering 3000 pieces of "OPA650N-3k" will get a single 3000 piece tape and reel).
Please refer to Appendix B of Burr-Brown IC Data Book for detailed Tape and Reel Mechanical information.
PACKAGE/ORDERING INFORMATION
4
OPA650
TYPICAL PERFORMANCE CURVES
At T
A
= +25
C, V
S
=
5V, R
L
= 100
, and R
FB
= 402
,
unless otherwise noted. R
FB
= 25
for Gain of +1.
INPUT BIAS CURRENT AND OFFSET VOLTAGE
vs TEMPERATURE
7
6
5
4
2
1
0
1
50
25
0
25
50
75
100
Input Bias Current (mA)
Offset Voltage (mV)
Temperature (C)
V
OS
I
B
INPUT VOLTAGE AND CURRENT NOISE
vs FREQUENCY
Frequency (Hz)
100
1k
10k
100k
1M
100
10
1
Input Current Noise (pA/
Hz)
Input Voltage Noise (nV/
Hz)
Non-inverting and
Inverting Current Noise
Voltage Noise
SUPPLY CURRENT vs TEMPERATURE
7
6
5
4
3
60
40
20
0
20
40
60
80
100
Supply Current (mA)
Temperature (C)
OUTPUT CURRENT vs TEMPERATURE
110
100
90
80
50
25
0
25
50
75
100
Output Current (mA)
Temperature (C)
I
O
+
I
O
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
100
90
80
70
60
4
3
2
1
0
1
2
3
4
Common Mode-Rejection (dB)
Common-Mode Voltage (V)
A
OL
, PSR AND CMRR vs TEMPERATURE
100
90
80
70
60
50
40
50
25
0
25
50
75
125
A
OL
, PSR and CMRR (dB)
Temperature (C)
A
OL
PSR
CMRR
PSR+
OPA650
5
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25
C, V
S
=
5V, R
L
= 100
, and R
FB
= 402
,
unless otherwise noted. R
FB
= 25
for Gain of +1.
LARGE SIGNAL TRANSIENT RESPONSE
(G = +1)
Time (5ns/div)
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
2.0
Output Voltage (V)
CLOSED-LOOP BANDWIDTH (G = +1)
Frequency (Hz)
6
3
0
3
6
9
1M
10M
100M
1G
Gain (dB)
DIP Bandwidth
= 520MHz
SO-8 Bandwidth
= 560MHz
CLOSED-LOOP BANDWIDTH (G = +5)
Frequency (Hz)
20
17
14
11
8
5
2
1
1M
10M
100M
1G
Gain (dB)
SO-8/DIP Bandwidth = 37MHz
CLOSED-LOOP BANDWIDTH (G = +2)
Frequency (Hz)
12
9
6
3
0
3
6
9
12
1M
10M
100M
1G
Gain (dB)
SO-8/DIP Bandwidth = 140MHz
RECOMMENDED ISOLATION RESISTANCE
vs CAPACITIVE LOAD
40
30
20
10
0
0
20
40
60
80
100
Isolation Resistance, R
ISO
(
)
Capacitive Load, C
L
(pF)
OPA650
C
L
1k
R
ISO
25
SMALL SIGNAL TRANSIENT RESPONSE
(G = +1)
Time (5ns/div)
200
160
120
80
40
0
40
80
120
160
200
Output Voltage (mV)
6
OPA650
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25
C, V
S
=
5V, R
L
= 100
, and R
FB
= 402
,
unless otherwise noted. R
FB
= 25
for Gain of +1.
HARMONIC DISTORTION vs FREQUENCY
(G = +1, V
O
= 2Vp-p, R
L
= 100
)
Frequency (Hz)
Harmonic Distortion (dBc)
40
50
60
70
80
90
100k
10M
1M
100M
3f
O
2f
O
HARMONIC DISTORTION vs TEMPERATURE
(f
O
= 5MHz, V
O
= 2Vp-p, G = +1)
50
60
70
80
90
60
40
20
0
20
40
60
80
3f
O
2f
O
100
Harmonic Distortion (dBc)
Temperature (C)
5MHz HARMONIC DISTORTION
vs OUTPUT SWING
Output Swing (Vp-p)
60
70
80
90
100
0.1
1
10
Harmonic Distortion (dBc)
3f
O
2f
O
G = +2
10MHz HARMONIC DISTORTION
vs OUTPUT SWING
Output Swing (Vp-p)
50
60
70
80
90
0.1
1
10
Harmonic Distortion (dBc)
3f
O
2f
O
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
60
50
40
30
20
10
0
+45
0
45
90
135
180
225
1k
10k
100k
1M
10M
100M
1G
Gain (dB)
Phase ()
Frequency (Hz)
Phase
Gain
CLOSED LOOP BANDWIDTH (G = +10)
Frequency (Hz)
1M
10M
100M
1G
SO-8/DIP Bandwidth = 18MHz
26
23
20
17
14
11
8
5
2
Gain (dB)
OPA650
7
the ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2
F to 6.8
F) decoupling
capacitors, effective at lower frequencies, should also be
used. These may be placed somewhat farther from the
device and may be shared among several devices in the same
area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of the
OPA650. Resistors should be a very low reactance type.
Surface mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads as short as possible. Never use
wirewound type resistors in a high frequency application.
Since the output pin and the inverting input pin are most
sensitive to parasitic capacitance, always position the feed-
back and series output resistor, if any, as close as possible to
the package pins. Other network components, such as non-
inverting input termination resistors, should also be placed
close to the package.
Even with a low parasitic capacitance shunting external
resistors, excessively high resistor values can create signifi-
cant time constants and degrade performance. Good metal
film or surface mount resistors have approximately 0.2pF in
shunt with the resistor. For resistor values > 1.5k
, this adds
a pole and/or zero below 500MHz that can affect circuit
operation. Keep resistor values as low as possible consistent
with output loading considerations. The 402
feedback
used for the Typical Performance Plots is a good starting
point for design. Note that a 25
feedback resistor, rather
than a direct short, is suggested for a unity gain follower.
This effectively reduces the Q of what would otherwise be
a parasitic inductance (the feedback wire) into the parasitic
capacitance at the inverting input.
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25
C, V
S
=
5V, R
L
= 100
, and R
FB
= 402
,
unless otherwise noted. R
FB
= 25
for Gain of +1.
HARMONIC DISTORTION vs GAIN
(f
O
= 5MHz, V
O
= 2Vp-p)
40
50
60
70
80
1
2
3
4
5
6
7
8
9
10
Harmonic Distortion (dBc)
Non-Inverting Gain (V/V)
3f
O
2f
O
DISCUSSION OF
PERFORMANCE
The OPA650 is a low power, wideband voltage feedback
operational amplifier. Each channel is internally compen-
sated to provide unity gain stability. The OPA650's voltage
feedback architecture features true differential and fully sym-
metrical inputs. This minimizes offset errors, making the
OPA650 well suited for implementing filter and instrumen-
tation designs. The OPA650's AC performance is optimized
to provide a gain bandwidth product of 180MHz and a fast
0.1% settling time of 10.2ns, which is an important consid-
eration in high speed data conversion applications. Along
with its excellent settling characteristics, the low DC input
offset of
1mV and drift of
3
V/
C support high accuracy
requirements. In applications requiring a higher slew rate and
wider bandwidth, such as video and high bit rate digital
communications, consider the current feedback OPA658.
CIRCUIT LAYOUT AND BASIC OPERATION
Achieving optimum performance with a high frequency am-
plifier like the OPA650 requires careful attention to layout
parasitics and selection of external components. Recommen-
dations for PC board layout and component selection include:
a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability; on the non-
inverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the two power pins
to high frequency 0.1
F decoupling capacitors. At the pins,
8
OPA650
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100 mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
ISO
from
the plot of recommended R
ISO
vs capacitive load. Low
parasitic loads may not need an R
ISO
since the OPA650 is
nominally compensated to operate with a 2pF parasitic load.
If a long trace is required and the 6dB signal loss intrinsic to
doubly terminated transmission lines is acceptable, imple-
ment a matched impedance transmission line using microstrip
or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50
environ-
ment is not necessary on board, and in fact a higher imped-
ance environment will improve distortion as shown in the
distortion vs load plot. With a characteristic impedance
defined based on board material and desired trace dimen-
sions, a matching series resistor into the trace from the
output of the amplifier is used as well as a terminating shunt
resistor at the input of the destination device. Remember
also that the terminating impedance will be the parallel
combination of the shunt resistor and the input impedance of
the destination device; the total effective impedance should
match the trace impedance. Multiple destination devices are
best handled as separate transmission lines, each with their
own series and shunt terminations.
If the 6dB attenuation loss of a doubly terminated line is
unacceptable, a long trace can be series-terminated at the
source end only. This will help isolate the line capacitance
from the op amp output, but will not preserve signal integrity
as well as a doubly terminated line. If the shunt impedance
at the destination end is finite, there will be some signal
attenuation due to the voltage divider formed by the series
and shunt impedances.
e) Socketing a high speed part like the OPA650 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely
troublesome parasitic network which can make it almost
impossible to achieve a smooth, stable response. Best results
are obtained by soldering the part onto the board. If socket-
ing for the DIP package is desired, high frequency flush
mount pins (e.g., McKenzie Technology #710C) can give
good results.
The OPA650 is nominally specified for operation using
5V
power supplies. A 10% tolerance on the supplies, or an ECL
5.2V for the negative supply, is within the maximum speci-
fied total supply voltage of 11V. Higher supply voltages can
break down internal junctions possibly leading to catastrophic
failure. Single supply operation is possible as long as com-
mon mode voltage constraints are observed. The common
mode input and output voltage specifications can be inter-
preted as a required headroom to the supply voltage. Observ-
ing this input and output headroom requirement will allow
non-standard or single supply operation. Figure 1 shows one
approach to single-supply operation.
402
OPA650
V
AC
402
R
L
+V
S
+V
S
V
S
2
R
OUT
V
S
2
V
OUT
= + 2V
AC
FIGURE 1. Single Supply Operation.
OFFSET VOLTAGE ADJUSTMENT
If additional offset adjustment is needed, the circuit in
Figure 2 can be used without degrading offset drift with
temperature. Avoid external adjustment whenever possible
since extraneous noise, such as power supply noise, can be
inadvertently coupled into the amplifier's inverting input
terminal. Remember that additional offset errors can be
created by the amplifier's input bias currents. Whenever
possible, match the impedance seen by both inputs as is
shown with R
3
. This will reduce input bias current errors to
the amplifier's offset current.
R
2
OPA650
(1)
R
3
= R
1
|| R
2
R
1
R
Trim
+V
S
V
S
20k
V
IN
or Ground
Output Trim Range +V
S
to V
S
R
Trim
47k
R
2
R
2
R
Trim
0.1F
NOTE: (1) R
3
is
optional and can
be used to cancel
offset errors due
to input bias currents.
ESD PROTECTION
ESD damage has been well recognized for MOSFET de-
vices, but any semiconductor device is vulnerable to this
potentially damaging source. This is particularly true for
very high speed, fine geometry processes.
ESD damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
precision operational amplifiers, this may cause a noticeable
degradation of offset voltage and drift. Therefore, ESD
handling precautions are strongly recommended when han-
dling the OPA650.
FIGURE 2. Offset Voltage Trim.
OPA650
9
DRIVING CAPACITIVE LOADS
The OPA650's output stage has been optimized to drive low
resistive loads. Capacitive loads, however, will decrease the
amplifier's phase margin which may cause high frequency
peaking or oscillations. Capacitive loads greater than 10pF
should be isolated by connecting a small resistance, usually
15
to 30
, in series with the output as shown in Figure 4.
This is particularly important when driving high capacitance
loads such as flash A/D converters. Increasing the gain from
+1 will improve the capacitive load drive due to increased
phase margin.
In general, capacitive loads should be minimized for opti-
mum high frequency performance. Coax lines can be driven
if the cable is properly terminated. The capacitance of coax
cable (29pF/foot for RG-58) will not load the amplifier
when the coaxial cable or transmission line is terminated in
its characteristic impedance.
THERMAL CONSIDERATIONS
The OPA650 will not require heatsinking under most oper-
ating conditions. Maximum desired junction temperature
will limit the maximum allowed internal power dissipation
as described below. In no case should the maximum junction
temperature be allowed to exceed +175
C.
Operating junction temperature (T
J
) is given by T
A
+
P
D
JA
. The total internal power dissipation (P
D
) is a com-
bination of the total quiescent power (P
DQ
) and the power
dissipated in of the output stage (P
DL
) to deliver load
power. Quiescent power is simply the specified no-load
supply current times the total supply voltage across the
part. P
DL
will depend on the required output signal and load
but would, for a grounded resistive load, be at a maximum
when the output is a fixed DC voltage equal to 1/2 of either
supply voltage (assuming equal bipolar supplies). Under
this condition, P
DL
= V
S
2
/(4R
L
) where R
L
includes feed-
back network loading. Note that it is the power dissipated
in the output stage and not in the load that determines
internal power dissipation. As an example, compute the
maximum T
J
for an OPA650N at A
V
= +2, R
L
= 100
, R
FB
= 402
,
V
S
=
5V, with the output at |V
S
/2|, and the
specified maximum T
A
= +85
C. P
D
= 10V8.75mA + (5
2
)/
(4(100
||804
)) = 158mW. Maximum T
J
= +85
C +
0.158W150
C/W = 109
C.
OUTPUT DRIVE CAPABILITY
The OPA650 has been optimized to drive 75
and 100
resistive loads. The device can drive a 2Vp-p into a 75
load.
This high-output drive capability makes the OPA650 an ideal
choice for a wide range of RF, IF, and video applications. In
many cases, additional buffer amplifiers are unneeded.
Many demanding high-speed applications such as driving
A/D converters require op amps with low wideband output
impedance. For example, low output impedance is essential
when driving the signal-dependent capacitances at the inputs
of flash A/D converters. As shown in Figure 3, the OPA650
maintains very low-closed loop output impedance over fre-
quency. Closed-loop output impedance increases with fre-
quency since loop gain is decreasing.
FIGURE 3. Small-Signal Output Impedance vs Frequency.
SMALL-SIGNAL OUTPUT IMPEDANCE
vs FREQUENCY
Frequency (Hz)
1k
100
10
1
0.1
0.01
10k
100k
1M
100M
10M
Output Impedance (
)
G = +1
OPA650
C
L
R
L
R
ISO
(R
ISO
typically 15
to 30
)
25
FIGURE 4. Driving Capacitive Loads.
FREQUENCY RESPONSE COMPENSATION
The OPA650 is internally compensated and is stable in unity
gain with a phase margin of approximately 60
. However,
the unity gain buffer is the most demanding circuit configu-
ration for loop stability and oscillations are most likely to
occur in this gain. If possible, use the device in a noise gain
greater than one to improve phase margin and reduce the
susceptibility to oscillation. (Note that, from a stability
standpoint, an inverting gain of 1V/V is equivalent to a
noise gain of 2.) Frequency response for other gains are
shown in the Typical Performance Curves.
The high frequency response of the OPA650 in a good
layout is very flat with frequency. However, some circuit
configurations such as those where large feedback resis-
tances are used, can produce high-frequency gain peaking.
This peaking can be minimized by connecting a small
capacitor in parallel with the feedback resistor. This capaci-
tor compensates for the closed-loop, high-frequency, trans-
fer function zero that results from the time constant formed
by the input capacitance of the amplifier (typically 2pF after
PC board mounting), and the input and feedback resistors.
The selected compensation capacitor may be a trimmer, a
fixed capacitor, or a planned PC board capacitance. The
capacitance value is strongly dependent on circuit layout and
closed-loop gain. Using small resistor values will preserve
10
OPA650
Load Resistance (
)
Harmonic Distortion (dBc)
60
70
80
90
10
100
1k
3f
O
2f
O
the phase margin and avoid peaking by keeping the break
frequency of this zero sufficiently high. When high closed-
loop gains are required, a three-resistor attenuator (tee-
network) is recommended to avoid using large value resis-
tors with large time constants.
PULSE SETTLING TIME
High speed amplifiers like the OPA650 are capable of
extremely fast settling time with a pulse input. Excellent
frequency response flatness and phase linearity are required
to get the best settling times. As shown in the specifications
table, settling time for a
1V step at a gain of +1 for the
OPA650 is extremely fast. The specification is defined as
the time required, after the input transition, for the output to
settle within a specified error band around its final value. For
a 2V step, 1% settling corresponds to an error band of
20mV, 0.1% to an error band of
2mV, and 0.01% to an
error band of
0.2mV. For the best settling times, particu-
larly into an ADC capacitive load, little or no peaking in the
frequency response can be allowed. Using the recommended
R
ISO
for capacitive loads will limit this peaking and reduce
the settling times. Fast, extremely fine scale settling (0.01%)
requires close attention to ground return currents in the
supply decoupling capacitors. For highest performance, con-
sider the OPA642 which isolates the output stage decoupling
from the rest of the amplifier.
DIFFERENTIAL GAIN AND PHASE
Differential Gain (DG) and Differential Phase (DP) are
among the more important specifications for video applica-
tions. The percentage change in closed-loop gain over a
specified change in output voltage level is defined as DG.
DP is defined as the change in degrees of the closed-loop
phase over the same output voltage change. DG and DP are
both specified at the NTSC sub-carrier frequency of 3.58MHz.
DG and DP increase closed-loop gain and output voltage
transition. All measurements were performed using a
Tektronix model VM700 Video Measurement Set.
DISTORTION
The OPA650's harmonic distortion characteristics into a
100
load are shown versus frequency and power output in
the typical performance curves. Distortion can be signifi-
cantly improved by increasing the load resistance as illus-
trated in Figure 5. Remember to include the contribution of
the feedback network when calculating the effective load
resistance seen by the amplifier.
NOISE FIGURE
The OPA650 voltage noise spectral density is specified in
the Typical Performance Curves. For RF applications, how-
ever, Noise Figure (NF) is often the preferred noise specifi-
cation since it allows system noise performance to be more
easily calculated. The OPA650's Noise Figure vs Source
Resistance is shown in Figure 6.
SPICE MODELS AND EVALUATION BOARD
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and induc-
tance can have a major effect on circuit performance. SPICE
models are available on a disk from the Burr-Brown Appli-
cations Department.
Demonstration boards are available for each OPA650 pack-
age style. These boards implement a very low parasitic
layout that will produce the excellent frequency and pulse
responses shown in the Typical Performance Curves. For
each package style, the recommended demonstration board
is:
Contact your local Burr-Brown sales office or distributor to
order demonstration boards.
DEM-OPA65xP
8-Pin DIP for the OPA650P
DEM-OPA65xU
SO-8 for the OPA650U
DEM-OPA6xxN
SOT23 for the OPA650N
FIGURE 6. Noise Figure vs Source Resistance.
NOISE FIGURE vs SOURCE RESISTANCE
Source Resistance (
)
30
25
20
15
10
5
0
10
100
1k
100k
10k
Noise Figure (dB)
NF = 10 LOG 1 +
e
n
2
+ (I
n
R
S
)
2
4KTR
S
FIGURE 5. 5MHz Harmonic Distortion vs Load Resistance.
OPA650
11
TYPICAL APPLICATION
FIGURE 7. Low Distortion Video Amplifier.
OPA650
V
OUT
402
402
Video
Input
75
75
75
Transmission Line
75
FIGURE 8. Layout Detail For DEM-OPA65xP Demonstration Board.
R
6
R
1
OPA650
Out
J
1
1
2
GND
5V
P2
R
7
R
5
+In
R
3
R
4
R
2
In
J
1
J
2
2
7
4
6
3
C
2
0.1F
C
4
2.2F
402
C
1
2.2F
C
3
0.1F
1
2
GND
+5V
P1
R
8
+
+
NOTE: Values for R
1
, R
3
, R
5
, R
6
, and R
7
are chosen according to desired gain.
12
OPA650
(C)
(D)
(A)
(B)
DEM-OPA65xP Demonstration Board Layout
FIGURE 9a. Evaluation Board Silkscreen (Bottom). 9b. Evaluation Board Silkscreen (Top). 9c. Evaluation Board Layout
(Solder Side). 9d. Evaluation Board Layout (Layout Side).
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
OPA650N/250
ACTIVE
SOP
DBV
5
250
OPA650N/3K
ACTIVE
SOP
DBV
5
3000
OPA650P
OBSOLETE
PDIP
P
8
OPA650U
ACTIVE
SOIC
D
8
100
OPA650U/2K5
ACTIVE
SOIC
D
8
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
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