OPA683

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SBOS221B NOVEMBER 2001 -- REVISED JUNE 2002

Very Low-Power, Current Feedback

OPERATIONAL AMPLIFIER With Disable

FEATURES

REDUCED BANDWIDTH CHANGE VERSUS GAIN

150MHz BANDWIDTH G = +2

> 90MHz BANDWIDTH TO GAIN > +10

LOW DISTORTION: < 69dBc at 5MHz

HIGH OUTPUT CURRENT: 110mA

SINGLE +5V TO +12V SUPPLY OPERATION

DUAL

2.5V TO

6V SUPPLY OPERATION

LOW SUPPLY CURRENT: 0.94mA

LOW SHUTDOWN CURRENT: 100

V+

ERR

Patent Pending

(S)

ERR

Low-Power

Amplifier

Normalized Gain (dB)

200

100

= 1.2k

Frequency (MHz)

OPA683 BANDWIDTH vs GAIN

G = 10

G = 20

G = 50

G = 100

G = 2

G = 5

DESCRIPTION

The OPA683 provides a new level of performance in very low-
power, wideband, current feedback amplifiers. This CFB

plus

ampli-

fier is among the first to use an internally closed-loop input buffer
stage that enhances performance significantly over earlier low-
power CFB amplifiers. While retaining the benefits of very low
power operation, this new architecture provides many of the
advantages of a more ideal CFB amplifier. The closed-loop input
stage buffer gives a very low and linearized impedance path at the
inverting input to sense the feedback error current. This improved
inverting input impedance gives exceptional bandwidth retention
to much higher gains and improved harmonic distortion over earlier
solutions limited by inverting input linearity. Beyond simple high
gain applications, the OPA683 CFB

plus

amplifier can allow the gain

setting element to be set with considerable freedom from amplifier
bandwidth interaction. This allows frequency response peaking
elements to be added, multiple input inverting summing circuits to

OPA6

APPLICATIONS

LOW POWER BROADCAST VIDEO DRIVERS

EQUALIZING FILTERS

SAW FILTER HIGH GAIN POST AMPLIFIERS

SHORT LOOP ADSL CO DRIVERS

MULTICHANNEL SUMMING AMPLIFIERS

PROFESSIONAL CAMERAS

ADC INPUT DRIVERS

have greater bandwidth, and low-power line drivers to meet the
demanding requirements of studio cameras and broadcast video.

The output capability for the OPA683 also sets a new mark in
performance for very low-power current feedback amplifiers. De-
livering a full

4Vp-p swing on

5V supplies, the OPA683 also has

the output current to support this swing into a 100

load. This

minimal output headroom requirement is complemented by a
similar 1.2V input stage headroom giving exceptional capability for
single +5V operation.

The OPA683's low 0.94mA supply current is precisely trimmed at
25

C. This trim, along with low shift over temperature and supply

voltage, gives a very robust design over a wide range of operating
conditions. System power may be further reduced by using the
optional disable control pin. Leaving this disable pin open, or holding
it HIGH, gives normal operation. If pulled LOW, the OPA683 supply
current drops to less than 100

A while the I/O pins go to a high

impedance state.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

OPA683

SBOS221B

www.ti.com

ABSOLUTE MAXIMUM RATINGS

(1)

Power Supply ...............................................................................

6.5V

Internal Power Dissipation ................................. See Thermal Information
Differential Input Voltage ..................................................................

1.2V

Input Voltage Range ............................................................................

Storage Temperature Range: ID, IDBV ......................... 40

C to +125

Lead Temperature (soldering, 10s) .............................................. +300

Junction Temperature (T

) ........................................................... +175

NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

SPECIFIED

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE-LEAD

DESIGNATOR

(1)

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

OPA683

SO-8

C to +85

OPA683D

OPA683ID

Rails,100

OPA683IDR

Tape and Reel, 2500

OPA683

SOT23-6

DBV

C to +85

A83

OPA683IDBVT

Tape and Reel, 250

OPA683IDBVR

Tape and Reel, 3000

PACKAGE/ORDERING INFORMATION

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.

Output

Noninverting Input

DIS

Inverting Input

A83

Pin Orientation/Package Marking

Inverting Input

Noninverting Input

DIS

Output

NC = No Connection

PIN CONFIGURATION

OPA683 RELATED PRODUCTS

SINGLES

DUALS

TRIPLES

QUADS

FEATURES

OPA684

OPA2683

OPA3684

OPA4684

Low-Power CFB

plus

OPA691

OPA2691

OPA3691

High Slew Rate CFB

OPA685

> 500MHz CFB

Top View

SO-8

Top View

SOT23-6

NOTES: (1) For the most current specifications, and package information, refer to our web site at www.ti.com.

OPA683

SBOS221B

www.ti.com

AC PERFORMANCE (See Figure 1)
Small-Signal Bandwidth (V

= 0.5Vp-p)

G = +1, R

= 1.2k

200

MHz

typ

G = +2, R

= 1.2k

150

124

121

117

MHz

min

G = +5, R

= 1.2k

121

MHz

typ

G = +10, R

= 1.2k

MHz

typ

G = +20, R

= 1.2k

MHz

typ

Bandwidth for 0.1dB Gain Flatness

G = +2, V

= 0.5Vp-p, R

= 1.2k

MHz

min

Peaking at a Gain of +1

= 1.2k

, V

= 0.5Vp-p

1.8

6.5

7.7

8.0

max

Large-Signal Bandwidth

G = +2, V

= 4Vp-p

MHz

typ

Slew Rate

G = 1, V

= 4V Step (see Figure 2)

540

450

430

min

G = +2,V

= 4V Step

400

345

338

336

min

Rise-and-Fall Time

G = +2, V

= 0.5V Step

4.6

typ

G = +2, V

= 4VStep

7.8

typ

Harmonic Distortion

G = +2, f = 5MHz, V

= 2Vp-p

2nd-Harmonic

= 100

dBc

max

dBc

max

3rd-Harmonic

= 100

dBc

max

dBc

max

Input Voltage Noise

f > 1MHz

4.4

5.0

5.5

5.8

nV/

max

Noninverting Input Current Noise

f > 1MHz

5.1

5.8

6.4

6.7

pA/

max

Inverting Input Current Noise

f > 1MHz

11.6

11.9

12.3

12.4

pA/

max

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.06

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.03

deg

typ

DC PERFORMANCE

(4)

Open-Loop Transimpedance Gain (Z

)

= 0V, R

= 1k

700

360

270

250

min

Input Offset Voltage

= 0V

1.5

3.5

4.1

4.3

max

Average Offset Voltage Drift

= 0V

max

Noninverting Input Bias Current

= 0V

2.0

4.0

4.6

4.8

max

Average Noninverting Input Bias Current Drift

= 0V

nA/

max

Inverting Input Bias Current

= 0V

3.0

11.5

max

Average Inverting Input Bias Current Drift

= 0V

max

INPUT
Common-Mode Input Range

(5)

(CMIR)

3.75

3.65

3.60

min

Common-Mode Rejection Ratio (CMRR)

= 0V

min

Noninverting Input Impedance

|| pF

typ

Inverting Input Resistance (R

)

Open-Loop, DC

4.5

typ

OUTPUT
Voltage Output Swing

Load

4.1

4.0

3.9

min

Current Output, Sourcing

= 0

150

130

125

120

min

Current Output, Sinking

= 0

110

100

min

Closed-Loop Output Impedance

G = +2, f = 100kHz

0.007

typ

DISABLE (Disabled LOW)
Power-Down Supply Current (+V

)

DIS

= 0

100

150

170

180

typ

Disable Time

= +1, See Figure 1

typ

Enable Time

= +1, See Figure 1

typ

Off Isolation

G = +2, 5MHz

typ

Output Capacitance in Disable

1.7

typ

Turn On Glitch

G = +2, R

= 150

, V

= 0

typ

Turn Off Glitch

G = +2, R

= 150

, V

= 0

typ

Enable Voltage

3.4

3.5

3.6

3.7

min

Disable Voltage

1.8

1.7

1.6

1.5

max

Control Pin Input Bias Current (DIS)

DIS

= 0V

120

130

135

max

POWER SUPPLY
Specified Operating Voltage

typ

Maximum Operating Voltage Range

max

Max Quiescent Current

0.94

1.03

1.04

1.05

max

Min Quiescent Current

0.94

0.85

0.80

0.77

min

Power-Supply Rejection Ratio (PSRR)

Input Referred

typ

TEMPERATURE RANGE
Specification: D, DBV

40 to +85

typ

Thermal Resistance,

Junction-to-Ambient

SO-8

125

C/W

typ

DBV SOT-23-6

150

C/W

typ

NOTES: (1) Junction temperature = ambient for 25

C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient

C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25

C. Over temperature limits by characterization and

simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V

is the input

common-mode voltage. (5) Tested < 3dB below minimum specified CMR at

CMIR limits.

ELECTRICAL CHARACTERISTICS: V

= 1.2k

, R

= 1k

, and G = +2

(see Figure 1 for AC performance only), unless otherwise noted.

OPA683ID, IDBV

TYP

MIN/MAX OVER TEMPERATURE

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

OPA683

SBOS221B

www.ti.com

AC PERFORMANCE (See Figure 3)
Small-Signal Bandwidth (V

= 0.2Vp-p)

G = +1, R

= 1.4k

145

MHz

typ

G = +2, R

= 1.4k

119

MHz

min

G = +5, R

= 1.4k

MHz

typ

G = +10, R

= 1.4k

MHz

typ

G = +20, R

= 1.4k

MHz

typ

Bandwidth for 0.1dB Gain Flatness

G = +2, V

< 0.5Vp-p, R

= 1.2k

MHz

min

Peaking at a Gain of +1

= 1.4k

, V

< 0.5Vp-p

max

Large-Signal Bandwidth

G = +2, V

= 2Vp-p

MHz

typ

Slew Rate

G = +2, V

= 2V Step

210

180

175

170

min

Rise-and-Fall Time

G = +2, V

= 0.5V Step

5.9

typ

G = +2, V

= 2VStep

7.8

typ

Harmonic Distortion

G = 2, f = 5MHz, V

= 2Vp-p

2nd-Harmonic

= 100

to V

dBc

max

to V

dBc

max

3rd-Harmonic

= 100

to V

dBc

max

to V

dBc

max

Input Voltage Noise

f > 1MHz

4.4

5.0

5.5

5.8

nV/

max

Noninverting Input Current Noise

f > 1MHz

5.1

5.8

6.4

6.7

pA/

max

Inverting Input Current Noise

f > 1MHz

11.6

11.9

12.3

12.4

pA/

max

Differential Gain

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.24

typ

Differential Phase

G = +2, NTSC, V

= 1.4Vp, R

= 150

0.19

deg

typ

DC PERFORMANCE

(4)

Open-Loop Transimpedance Gain (Z

)

= V

/2, R

= 1k

to V

700

300

270

250

min

Input Offset Voltage

= V

1.0

3.0

3.6

3.8

max

Average Offset Voltage Drift

= V

max

Noninverting Input Bias Current

= V

4.6

4.8

max

Average Noninverting Input Bias Current Drift

= V

nA/

max

Inverting Input Bias Current

= V

8.7

8.9

max

Average Inverting Input Bias Current Drift

= V

max

INPUT
Least Positive Input Voltage

(5)

1.1

1.25

1.29

1.34

max

Most Positive Input Voltage

(5)

3.9

3.75

3.73

3.67

min

Common-Mode Refection Ratio (CMRR)

= V

min

Noninverting Input Impedance

|| pF

typ

Inverting Input Resistance (R

)

Open-Loop

4.8

typ

OUTPUT
Most Positive Output Voltage

= 1k

to V

4.2

4.1

4.0

min

Least Positive Output Voltage

= 1k

to V

0.8

0.9

1.00

min

Current Output, Sourcing

= V

min

Current Output, Sinking

= V

min

Closed-Loop Output Impedance

G = +2, f = 100kHz

0.009

typ

DISABLE (Disabled LOW)
Power-Down Supply Current (+V

)

DIS

= 0

100

typ

Off Isolation

G = +2, 5MHz

typ

Output Capacitance in Disable

1.7

typ

Turn On Glitch

G = +2, R

= 150

, V

= V

typ

Turn Off Glitch

G = +2, R

= 150

, V

= V

typ

Enable Voltage

3.4

3.5

3.6

3.7

min

Disable Voltage

1.8

1.7

1.6

1.5

max

Control Pin Input Bias Current (DIS)

DIS

= 0V

120

130

135

max

POWER SUPPLY
Specified Single-Supply Operating Voltage

typ

Max Single-Supply Operating Voltage

max

Max Quiescent Current

= +5V

0.82

0.91

max

Min Quiescent Current

= +5V

0.82

0.71

0.69

0.67

min

Power-Supply Rejection Ratio (+PSRR)

Input Referred

typ

TEMPERATURE RANGE
Specification: D, DBV

40 to +85

typ

Thermal Resistance,

Junction-to-Ambient

SO-8

125

C/W

typ

DBV SOT-23-6

150

C/W

typ

NOTES: (1) Junction temperature = ambient for 25

C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient

C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25

C. Over temperature limits by characterization and

simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. V

is the input

common-mode voltage. (5) Tested < 3dB below minimum specified CMR at

CMIR limits.

ELECTRICAL CHARACTERISTICS: V

= +5V

= 1.4k

, R

= 1k

, and G = +2

(see Figure 3 for AC performance only), unless otherwise noted.

OPA683ID, IDBV

TYP

MIN/MAX OVER TEMPERATURE

C to

40

C to

MIN/

TEST

PARAMETER

CONDITIONS

+25

(1)

(2)

+85

(2)

UNITS

MAX

LEVEL

(3)

OPA683

SBOS221B

www.ti.com

TYPICAL CHARACTERISTICS: V

= 25

C, R

= 1.2k

, R

= 1k

, and G = +2

(see Figure 1 for AC performance only), unless otherwise noted.

INVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (200mV/div)

Output V

oltage (800mV/div)

0.8

0.6

0.4

0.2

0.4

0.6

0.8

3.2

2.4

1.6

0.8

1.6

2.4

3.2

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 2

G = 1

Frequency (MHz)

200

100

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Gain (dB)

G = +2

= 1k

See Figure 1

= 0.5Vp-p

= 1Vp-p

= 5Vp-p

= 2Vp-p

Frequency (MHz)

200

100

INVERTING LARGE-SIGNAL FREQUENCY RESPONSE

Gain (dB)

G = 1

= 1k

= 0.5Vp-p

See Figure 2

= 2Vp-p

= 1Vp-p

= 5Vp-p

NONINVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (200mV/div)

Output V

oltage (800mV/div)

0.8

0.6

0.4

0.2

0.4

0.6

0.8

3.2

2.4

1.6

0.8

1.6

2.4

3.2

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 1

G = +2

Frequency (MHz)

200

100

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (3dB/div)

= 0.5Vp-p

= 1.2k

G = 100

See Figure 1

G = 50

G = 10

G = 1

G = 2

G = 5

Frequency (MHz)

200

100

INVERTING SMALL-SIGNAL FREQUENCY RESPONSE

Normalized Gain (3dB/div)

= 0.5Vp-p

= 1.2k

See Figure 2

G = 10

G = 24

G = 5

G = 1

G = 2

OPA683

SBOS221B

www.ti.com

TYPICAL CHARACTERISTICS: V

(Cont.)

= 25

C, R

= 1.2k

, R

= 1k

, and G = +2

(see Figure 1 for AC performance only), unless otherwise noted.

HARMONIC DISTORTION vs LOAD RESISTANCE

100

Load Resistance (

)

Harmonic Distortion (dBc)

= 2Vp-p

f = 5MHz

G = +2

See Figure 1

2nd-Harmonic

3rd-Harmonic

Frequency (MHz)

0.1

HARMONIC DISTORTION vs FREQUENCY

Harmonic Distortion (dBc)

= 2Vp-p

= 1k

See Figure 1

2nd-Harmonic

3rd-Harmonic

HARMONIC DISTORTION vs OUTPUT VOLTAGE

0.5

Output Voltage (Vp-p)

Harmonic Distortion (dBc)

f = 5MHz
R

= 1k

2nd-Harmonic

3rd-Harmonic

See Figure 1

HARMONIC DISTORTION vs NONINVERTING GAIN

Gain (V/V)

Harmonic Distortion (dBc)

See Figure 1

= 2Vp-p

f = 5MHz
R

= 1k

2nd-Harmonic

3rd-Harmonic

HARMONIC DISTORTION vs INVERTING GAIN

Inverting Gain (V/V)

Harmonic Distortion (dBc)

3rd-Harmonic

2nd-Harmonic

= 2Vp-p

f = 5MHz
R

= 1k

See Figure 2

5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE

2.5

3.5

4.5

5.5

Supply Voltage (

Harmonic Distortion (dBc)

= 2Vp-p

= 1k

2nd-Harmonic

3rd-Harmonic

See Figure 1

OPA683

SBOS221B

www.ti.com

TYPICAL CHARACTERISTICS: V

(Cont.)

= 25

C, R

= 1.2k

, R

= 1k

, and G = +2

(see Figure 1 for AC performance only), unless otherwise noted.

100

Frequency (Hz)

INPUT VOLTAGE AND CURRENT NOISE DENSITY

Voltage Noise (nV/

Hz)

Current Noise (pA/

Hz)

Noninverting Current Noise

5.2pA/

Voltage Noise

4.4nV/

Inverting Current Noise

11.6pA/

160

140

120

100

LOAD

(pF)

100

vs C

LOAD

(

)

0.5dB Peaking

2-TONE, 3RD-ORDER

INTERMODULATION DISTORTION

Vp-p at 1k

Load (each tone)

3rd-Order Spurious Level (dBc)

1MHz

20MHz

0.1

0.4

5MHz

10MHz

+5V

1.2k

OPA684

Time (ms)

100

DISABLE TIME

DIS

OUT

and V

DIS

(V)

See Figure 1

100

Frequency (MHz)

0.1

100

DISABLED FEEDTHRU

Feedthru (dB)

G = +2

DIS

= 0V

See Figure 1

Frequency (MHz)

200

100

SMALL-SIGNAL BANDWIDTH vs C

LOAD

Normalized Gain (dB)

10pF

100pF

47pF

22pF

+5V

1.2k

OPA683

OPA683

SBOS221B

www.ti.com

TYPICAL CHARACTERISTICS: V

(Cont.)

= 25

C, R

= 1.2k

, R

= 1k

, and G = +2

(see Figure 1 for AC performance only), unless otherwise noted.

CMRR and PSRR vs FREQUENCY

Frequency (Hz)

Common-Mode Rejection Ratio (dB)

Power-Supply Rejection Ratio (dB)

CMRR

+PSRR

PSRR

OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE

Frequency (Hz)

Open-Loop

ransimpedance Gain (dB

) 120

100

Open-Loop Phase (

)

120

150

180

20log (Z

)

0.2

0.15

0.1

0.05

Number of 150

Video Loads

COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE

Differential Gain (%)

Differential Phase (

)

Gain = +2

NTSC, Positive Video

TYPICAL DC DRIFT OVER TEMPERATURE

100

125

Ambient Temperature (

Input Bias Currents (

and Of

fset V

oltage (mV)

Input Offset Voltage

Noninverting Input Bias Current

Inverting Input Bias Current

OUTPUT CURRENT AND VOLTAGE LIMITATIONS

150

100

150

(mA)

(V)

1W Power

Limit

= 100

= 500

1W Power

Limit

SUPPLY AND OUTPUT CURRENT

vs TEMPERATURE

100

125

Ambient Temperature (

Output Current (mA)

200

175

150

125

100

0.95

0.9

0.85

0.8

Supply Current (mA)

Sourcing Output Current

Sinking Output Current

Supply Current

Right Scale

OPA683

SBOS221B

www.ti.com

TYPICAL CHARACTERISTICS: V

(Cont.)

= 25

C, R

= 1.2k

, R

= 1k

, and G = +2

(see Figure 1 for AC performance only), unless otherwise noted.

SETTLING TIME

Time (ns)

% Error to Final V

alue

0.05

0.04

0.03

0.02

0.01

0.02

0.03

0.04

0.05

2V Step

See Figure 1

DISABLED SUPPLY CURRENT vs TEMPERATURE

100

125

Ambient Temperature (

Disabled Supply Current (

110

100

Current

NONINVERTING OVERDRIVE RECOVERY

Time (100ns/div)

Input V

oltage (0.8V/div)

Output V

oltage (1.6V/div)

4.0

3.2

2.4

1.6

0.8

1.6

2.4

3.2

4.0

8.0

6.4

4.8

3.2

1.6

3.2

4.8

6.4

8.0

See Figure 1

Input Voltage

Left Scale

Output Voltage

Right Scale

INPUT AND OUTPUT RANGE vs SUPPLY VOLTAGE

Supply Voltage

Input and Output V

oltage Range

Input

Voltage

Range

Output

Voltage

Range

CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY

Frequency (Hz)

100k

10k

100

10M

100M

Output Impedance (

)

100

0.01

0.001

1.2k

OPA683

INVERTING OVERDRIVE RECOVERY

Time (100ns/div)

Input V

oltage (1.6V/div)

Input V

oltage (1.6V/div)

8.0

6.4

4.8

3.2

1.6

3.2

4.8

6.4

8.0

6.4

4.8

3.2

1.6

3.2

4.8

6.4

8.0

Input Voltage

Left Scale

See Figure 2

Output Voltage

Right Scale

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TYPICAL CHARACTERISTICS: V

= +5V

= 25

C, R

= 1.4k

, R

= 1k

, and G = +2

(see Figure 3 for AC performance only), unless otherwise noted.

Frequency (MHz)

200

100

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

Normalized Gain (dB)

See Figure 3

G = 50

= 1.4k

= 0.2Vp-p

= 1k

G = 1

G = 2

G = 20

G = 10

G = 5

Frequency (MHz)

200

100

INVERTING LARGE-SIGNAL FREQUENCY RESPONSE

Gain (dB)

= 0.2Vp-p

See Figure 4

= 1Vp-p

= 0.5Vp-p

= 2Vp-p

G = 1

= 1k

Frequency (MHz)

200

100

NONINVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

Gain (dB)

0.5Vp-p

1Vp-p

0.2Vp-p

2Vp-p

See Figure 3

G = +2

= 1k

Frequency (MHz)

200

100

INVERTING SMALL-SIGNAL FREQUENCY RESPONSE

Normalized Gain (3dB/div)

See Figure 4

= 1.4k

= 0.2Vp-p

= 1k

G = 1

G = 10
G = 28

G = 5

G = 2

NONINVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (100mV/div)

Output V

oltage (400mV/div)

0.4

0.3

0.2

0.1

0.2

0.3

0.4

1.6

1.2

0.8

0.4

0.8

1.2

1.6

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 3

INVERTING PULSE RESPONSE

Time (10ns/div)

Output V

oltage (100mV/div)

Output V

oltage (400mV/div)

0.4

0.3

0.2

0.1

0.2

0.3

0.4

1.6

1.2

0.8

0.4

0.8

1.2

1.6

Large-Signal Right Scale

Small-Signal Left Scale

See Figure 4

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TYPICAL CHARACTERISTICS: V

= +5V

(Cont.)

= 25

C, R

= 1.4k

, R

= 1k

, and G = +2

(see Figure 3 for AC performance only), unless otherwise noted.

HARMONIC DISTORTION vs LOAD RESISTANCE

100

Load Resistance (

)

Harmonic Distortion (dBc)

= 2Vp-p

f = 5MHz

See Figure 3

3rd-Harmonic

2nd-Harmonic

Frequency (MHz)

0.1

HARMONIC DISTORTION vs FREQUENCY

Harmonic Distortion (dBc)

= 2Vp-p

= 1k

See Figure 3

2nd-Harmonic

3rd-Harmonic

Output Voltage (Vp-p)

0.5

HARMONIC DISTORTION vs OUTPUT VOLTAGE

Harmonic Distortion (dBc)

3rd-Harmonic

2nd-Harmonic

See Figure 3

G = +2

= 1k

f = 5MHz

0.3

0.25

0.2

0.15

0.1

0.05

Number of 150

Video Loads

COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE

Differential Gain (%)

Differential Phase (

)

G = +2

NTSC, Positive Video

2-TONE, 3RD-ORDER

INTERMODULATION DISTORTION

0.1

Vp-p at 1

Load (each tone)

3rd-Order Spurious Level (dBc)

See Figure 3

10MHz

20MHz

5MHz

SUPPLY AND OUTPUT CURRENT

vs TEMPERATURE

100

125

Ambient Temperature (

Output Current (mA)

100

0.95

0.9

0.85

0.8

0.75

0.7

Supply Current (mA)

Left Scale

Sinking Output Current

Right Scale

Supply Current

Sourcing Output Current

Left Scale

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APPLICATIONS INFORMATION

VERY LOW POWER CURRENT-FEEDBACK
OPERATION

The OPA683 gives a new level of performance in very low
power current-feedback op amps. Using a new input stage
buffer architecture, the OPA683 CFB

plus

amplifier gives im-

proved bandwidth to higher gains than previous < 1mA
supply current amplifiers. This closed-loop internal buffer
gives a very low and linearized impedance at the inverting
node--isolating the amplifier's AC performance from gain
element variations. This allows both the bandwidth and
distortion to remain nearly constant over gain--moving closer
to the ideal current-feedback performance of Gain Bandwidth
independence. This low power amplifier also delivers excep-
tional output power--it's

4V swing on

5V supplies with

> 100mA output drive gives excellent performance into
standard video loads or doubly-terminated 50

cables. Single

+5V supply operation is also supported with similar band-
widths, but reduced output power capability. For improved
harmonic distortion driving heavier loads, in a low power
CFB

plus

amplifier, consider the OPA684 while, for even

higher output power, consider the OPA691.

Figure 1 shows the DC-coupled, gain of +2, dual power-
supply circuit used as the basis of the

5V Electrical Charac-

teristics and Typical Characteristics. For test purposes, the
input impedance is set to 50

with a resistor to ground while

the output load is a 1k

resistor. Voltage swings reported in

the specifications are taken directly at the input and output
pins while load powers (dBm) are interpreted as the voltage
swing at the output converted to dBm as if the load were
50

. For the circuit of Figure 1, the total effective load will be

|| 2.4k

= 706

. Gain changes are most easily accom-

plished by simply resetting the R

value--holding R

con-

stant at its recommended value of 1.2k

. The disable control

line (DIS) is typically left open to ensure normal amplifier
operation. It may, however, be asserted LOW to reduce the
amplifier quiescent to 100

A typically.

Figure 2 shows the DC-coupled, gain of 1V/V, dual power-
supply circuit used as the basis of the Inverting Typical
Characteristics. Inverting operation offers several perfor-
mance benefits. Since there is no common-mode signal
across the input stage, the slew rate for inverting operation
is higher and the distortion performance is slightly improved.
An additional input resistor, R

, is included in Figure 2 to set

the input impedance equal to the 50

. The parallel combina-

tion of R

and R

set the input impedance. As the desired

gain increases for the inverting configuration, R

is adjusted

to achieved the desired gain and R

is also adjusted to hold

a 50

input match. A point will be reached where R

will

equal 50

, R

is then removed and the input match is set by

only. With R

fixed to achieve an input match to 50

, to

increase gain, R

is simply increased. This will, however,

quickly reduce the achievable bandwidth as the feedback
resistor increases from its recommended value of 1.2k

. If

the source does not require an input match to 50

, either

adjust R

to the get the desired load or remove it and let the

resistor alone provide the input load.

1.2k

OPA683

+5V

DIS

1.2k

0.1

6.8

0.1

6.8

FIGURE 1. DC-Coupled, G = +2V/V, Bipolar Supply, Speci-

fication and Test Circuit.

FIGURE 2. DC-Coupled, G = 1V/V, Bipolar Supply, Speci-

fication and Test Circuit.

1.2k

OPA683

+5V

DIS

52.3

1.2k

0.1

6.8

0.1

6.8

These circuits are showing

5V operation. The same circuit

can be applied with bipolar supplies ranging from

2.5V to

6V. Internal supply independent biasing gives nearly the

same performance for the OPA683 over this wide range of
supplies. Generally, the optimum feedback resistor value (for
nominally flat frequency response at G = +2) will increase in
value as the total supply voltage across the OPA683 is
reduced.

See Figure 3 for the AC-coupled, single +5V supply, gain of
+2V/V circuit configuration used as a basis for the +5V only
Electrical Characteristics and Typical Characteristics. The
key requirement of broadband single-supply operation is to
maintain input and output signal swings within the usable
voltage ranges at both the input and the output. The circuit
of Figure 3 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 12.5k

resistors)

to the noninverting input. The input signal is then AC-coupled

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into this midpoint voltage bias. The input voltage can swing
to within 1.25V of either supply pin, giving a 2.5Vp-p input
signal range centered between the supply pins. The input
impedance of Figure 3 is set to give a 50

input match. If the

source does not require a 50

match, remove this and drive

directly into the blocking capacitor. The source will then see
the 6.25k

load of the biasing network. The gain resistor

) is AC-coupled, giving the circuit a DC gain of +1--which

puts the noninverting input DC bias voltage (2.5V) on the
output as well. The feedback resistor value has been ad-
justed from the bipolar supply condition to re-optimize for a
flat frequency response in +5V only, gain of +2 operation. On
a single +5V supply, the output voltage can swing to within
1.0V of either supply pin while delivering more than 50mA
output current giving 3Vp-p output swing into an AC-coupled
100

load if required (8dBm maximum at the matched load).

The circuit of Figure 3 shows a blocking capacitor driving into
a 1k

load resistor. Alternatively, the blocking capacitor

could be removed if the load is tied to a supply midpoint or
to ground if the DC current required by the load is accept-
able.

Figure 4 shows the AC-coupled, single +5V supply, gain of
1V/V circuit configuration used as a basis for the +5V only
Typical Characteristics. In this case, the midpoint DC bias on
the noninverting input is also decoupled with an additional
0.1

F decoupling capacitor. This reduces the source imped-

ance at higher frequencies for the noninverting input bias
current noise. This 2.5V bias on the noninverting input pin
appears on the inverting input pin and, since R

is DC

blocked by the input capacitor, will also appear at the output
pin. One advantage to inverting operation is that since there
is no signal swing across the input stage, higher slew rates
and operation to even lower supply voltages is possible. To
retain a 1Vp-p output capability, operation down to a 3V
supply is allowed. At a +3V supply, the input stage is
saturated, but for the inverting configuration of a current-
feedback amplifier, wideband operation is retained even
under this condition.

The circuits of Figure 3 and 4 show single-supply operation
at +5V. These same circuits may be used up to single
supplies of +12V with minimal changes in the performance of
the OPA683.

LOW POWER, VIDEO LINE DRIVER
APPLICATIONS

For low power, video line driving, the OPA683 provides the
output current and linearity to support multiple load compos-
ite video signals. Figure 5 shows a typical

5V supply video

line driver application. The improved 2nd-harmonic distortion
of the CFB

plus

architecture, along with the OPA683's high

output current and voltage, gives exceptional differential gain
and phase performance in a very low power solution. As the
Typical Characteristics show, a single video load shows a
dG/dP of 0.06%/0.03

. Multiple loads may also be driven with

< 0.15%/0.1

dG/dP for up to 4 parallel video loads where the

amplifier is driving an equivalent load of 37.5

1.4k

OPA683

+5V

DIS

Source

0.1

6.8

12.5k

2.5V

12.5k

1.4k

0.1

FIGURE 3. AC-Coupled, G = +2V/V, Single-Supply, Specifi-

cation and Test Circuit.

1.4k

OPA683

+5V

DIS

Source

0.1

2.5V

6.8

1.4k

12.5k

0.1

52.3

0.1

FIGURE 4. AC-Coupled, G = 1V/V, Single-Supply, Specifi-

cation and Test Circuit.

1.2k

OPA683

+5V

DIS

1.2k

Load

Supply Decoupling not shown.

Coax

VIDEO

FIGURE 5. Gain of +2 Video Cable Driver.

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VERY LOW POWER ACTIVE FILTER

The OPA683 provides an exceptionally capable gain block
for implementing Sallen-Key type filters. Typically, the band-
width interaction with gain setting for low power amplifiers,
constrain these filters to using unity-gain amplifiers. Since
the OPA683 CFB

plus

design holds very high bandwidth to

high gains, implementations that provide signal gain, as well
as the desired filter shape, are easily implemented. Figure 6
shows an example of a 5MHz 2nd-order low-pass filter where
the amplifier is providing a voltage gain of 4. This single-
supply implementation (applicable to single +12V operation
as well) consumes only 5.1mW quiescent power. The two
12.5k

resistors bias the input and output at the supply

midpoint while the three 0.1

F capacitors block off the DC

current paths to ground for this mid-scale operating point.
The filter resistors and capacitors have been adjusted
to provide a Butterworth (Q = 0.707) response with a
Wo = 2

· 5MHz. This gives a flat passband response with

a 3dB cutoff at 5MHz. Figure 7 shows the small-signal
frequency response for the circuit of Figure 6.

HIGH GAIN HF AMPLIFIER

Where high gains at moderate frequencies are required in an
HF receiver channel, the OPA683 can provide a very low
power solution with moderate input noise figure. Figure 8
shows a technique that can improve the noise figure with no
added power. An input transformer provides a noiseless
voltage gain at the cost of higher source impedance for the
amplifier's noninverting input current noise. The circuit of
Figure 8, using a 1:4 turns ratio (1:16 impedance ratio)
transformer, reduces the input noise figure from about 20dB
for just the amplifier to 10.6dB in combination. The bandwidth
for this circuit will be principally set by the transformer since
the OPA683 will give > 80MHz for the gain of 20V/V shown
in Figure 8. The overall circuit gives a gain to a matched 50

load of 32dB (40V/V) from the transformer input. This ex-
ample circuit provides this gain using only 10mW of quies-
cent power with application from 500kHz to 30MHz.

1.4k

OPA683

+5V

12.5k

467

0.1

446

157

100pF

Supply

De-coupling

Not Shown

150pF

0.1

Frequency (Hz)

20E6

LOW POWER 5MHz LP ACTIVE FILTER

Gain (dB)

FIGURE 6. 5MHz, 2nd-Order Low Pass Filter.

FIGURE 7. Low Power Active Filter Frequency Response.

OPA683

+5V

0.01

800

= 32dB

1.2k

10.6dB

Noise Figure

1:4

FIGURE 8. Low Power, High Gain HF Amplifier.

LOW POWER, ADC DRIVER

Where a low power, single-supply interface to a single-ended
input +5V ADC is required, the circuit of Figure 9 can provide
a very flexible, high performance solution. Running in an AC-
coupled inverting mode allows the noninverting input to be
used for the common-mode voltage from the ADS820 con-
verter. This midpoint reference biases both the noninverting
converter input and the amplifier noninverting input. With an
AC-coupled gain path, this +2.5V DC bias has a gain of +1
to the output putting the output at the DC midpoint for the
converter. The output then drives through an isolating resis-
tor (60

) to the inverting input of the converter which is

further decoupled by a 22pF external capacitance to add to
its 5pF input capacitance. This coupling network provides a
high cutoff low-pass while also giving a low source imped-
ance at high frequencies for the converter. The gain for this
circuit is set by adjusting R

to the desired value. For a 2Vp-p

maximum output driving the light load of Figure 9, the
OPA683 will provide < 80dBc THD through 1MHz as shown
in the Typical Characteristics. One of the important advan-
tages for this CFB

plus

amplifier is that this distortion does not

degrade significantly at higher gains.

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DESIGN-IN TOOLS

DEMONSTRATION BOARDS

Two PC boards are available to assist in the initial evaluation
of circuit performance using the OPA683 in its two package
styles. Both of these are available free as an unpopulated PC
board delivered with descriptive documentation. The sum-
mary information for these boards is shown in Table I.

The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however
set the CMRR for a single op amp differential amplifier
configuration. For the buffer gain

< 1.0, the CMRR =

20 · log(1

). The closed loop input stage buffer used in

the OPA683 gives a buffer gain more closely approaching
1.00 and this shows up in a slightly higher CMRR than any
previous current feedback op amp. The 60dB typical CMRR
shown in the Electrical Characteristics implies a buffer gain
of 0.9990.

, the buffer output impedance, is a critical portion of the

bandwidth control equation. The OPA683 reduces this ele-
ment to approximately 4.5

using the loop-gain of the input

buffer stage. This significant reduction in buffer output im-
pedance, on very low power, contributes significantly to
extending the bandwidth at higher gains.

BOARD

LITERATURE

PART

REQUEST

PRODUCT

PACKAGE

NUMBER

OPA683ID

SO-8

DEM-OPA68xU

SBOU009

OPA683IDBQ

SOT23-6

DEM-OPA6xxN

SBOU010

TABLE I. EVM Boards by Package.

OPERATING SUGGESTIONS

SETTING RESISTOR VALUES TO OPTIMIZE
BANDWIDTH

Any current-feedback op amp like the OPA683 can hold high
bandwidth over signal gain settings with the proper adjust-
ment of the external resistor values. A low-power part like the
OPA683 typically shows a larger change in bandwidth due to
the significant contribution of the inverting input impedance
to loop-gain changes as the signal gain is changed. Figure
10 shows a simplified analysis circuit for any current feed-
back amplifier.

The key elements of this current feedback op amp model are:

Buffer gain from the noninverting input to the inverting input

Buffer output impedance

ERR

Feedback error current signal

Z(s)

Frequency dependent open loop transimpedance gain

from i

ERR

to V

OPA683

+5V

DIS

1.4k

22pF

1.4k

0.1

ADS830

10-Bit

20MSPS

2.5V

+2.5V

2Vp-p

Max

FIGURE 9. Low Power, Single-Supply, ADC Driver.

(S)

ERR

FIGURE 10. Current Feedback Transfer Function Analysis

Circuit.

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A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error volt-
age for a voltage feedback op amp) and passes this on to the
output through an internal frequency dependent transimped-
ance gain. The Typical Characteristics show this open-loop
transimpedance response. This is analogous to the open-
loop voltage gain curve for a voltage feedback op amp.
Developing the transfer function for the circuit of Figure 10
gives Equation 1:

(1)

R NG

( )

This is written in a loop-gain analysis format where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z(s) was infinite over all frequencies, the
denominator of Equation 1 would reduce to 1 and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 1 determines the
frequency response. Equation 2 shows this as the loop-gain
equation.

(2)

R NG

Loop Gain

( )

If 20 · log(R

+ NG · R

) were drawn on top of the open-loop

transimpedance plot, the difference between the two would
be the loop gain at a given frequency. Eventually, Z(s) rolls
off to equal the denominator of Equation 2 at which point the
loop gain has reduced to 1 (and the curves have intersected).
This point of equality is where the amplifier's closed-loop
frequency response given by Equation 1 will start to roll off,
and is exactly analogous to the frequency at which the noise
gain equals the open-loop voltage gain for a voltage feed-
back op amp. The difference here is that the total impedance
in the denominator of Equation 2 may be controlled some-
what separately from the desired signal gain (or NG).

The OPA683 is internally compensated to give a maximally
flat frequency response for R

= 1.2k

at NG = 2 on

supplies. That optimum value goes to 1.4k

on a single +5V

supply. Normally, with a current feedback amplifier, it is
possible to adjust the feedback resistor to hold this band-
width up as the gain is increased. The CFB

plus

architecture

has reduced the contribution of the inverting input impedance
to provide exceptional bandwidth to higher gains without
adjusting the feedback resistor value. The Typical Character-
istics show the small-signal bandwidth over gain with a fixed
feedback resistor.

At very high gains, 2nd-order effects in the buffer output
impedance cause the overall response to peak up. If desired,
it is possible to retain a flatter frequency response at higher
gains by adjusting the feedback resistor to higher values as
the gain is increased. Figure 11 shows the empirically deter-
mined feedback resistor and resulting 3dB bandwidth from
gains of +2 to +100 to hold a < 0.5dB peaked response.
Here, since a slight peaking was allowed, a lower nominal R

is suggested at a gain of +2 giving > 250MHz bandwidth.
This exceeds that shown in the Electrical Characteristics due
to the slightly lower feedback resistor allowing a modest
peaking in the response. Figure 12 shows the measured
frequency response curves with the adjusted feedback resis-
tor value. While the bandwidth for this low-power part does
reduce at higher gains, going over a 50:1 gain range gives
only a factor of 10 bandwidth reduction. The 25MHz band-
width at a gain of 100V/V is equivalent to a 2.5GHz gain
bandwidth product voltage feedback amplifier capability. Even
better bandwidth retention to higher gains can be delivered
by the slightly higher quiescent power OPA684.

3900

3400

2900

2400

1900

1400

900

Voltage Gain (V/V)

100

Feedback Resistor (

)

325

275

225

175

125

Bandwidth (MHz)

3dB Bandwidth

= 0.5Vp-p

Frequency (MHz)

200

100

Normalized Gain (dB)

G = 5

G = 100

G = 2

G = 10

G = 50

G = 20

FIGURE 11. Bandwidth and R

Optimized vs Gain.

FIGURE 12. Small-Signal Frequency Response with Opti-

mized R

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OUTPUT CURRENT AND VOLTAGE

The OPA683 provides output voltage and current capabilities
that can support the needs of driving doubly-terminated 50

lines. Changing the 1k

load in Figure 1 to a 100

will give

a total load that is the parallel combination of the 100

load

and the 2.4k

total feedback network impedance. This 96

load will require no more than 36mA output current to support
a

3.5V output voltage swing. This is within the specified

minimum output current of +58mA/45mA over the full tem-
perature range.

The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage · current, or V-I product,
which is more relevant to circuit operation. Refer to the
"Output Voltage and Current Limitations" plot in the Typical
Characteristics. The X and Y axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA683's output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.

The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
Electrical Specifications. As the output transistors deliver
power, their junction temperatures will increase, decreasing
their V

's (increasing the available output voltage swing)

and increasing their current gains (increasing the available
output current). In steady state operation, the available
output voltage and current will always be greater than that
shown in the over-temperature specifications since the out-
put stage junction temperatures will be higher than the
minimum specified operating ambient.

To maintain maximum output stage linearity, no output short
circuit protection is provided. This will not normally be a
problem since most applications include a series matching
resistor at the output that will limit the internal power dissipa-
tion if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to the adjacent
positive power-supply pin (8-pin packages) will, in most
cases, destroy the amplifier. If additional short-circuit protec-
tion is required, consider a small series resistor in the power-
supply leads. This will, under heavy output loads, reduce the
available output voltage swing. A 5

series resistor in each

power-supply lead will limit the internal power dissipation to
less than 1W for an output short circuit while decreasing the
available output voltage swing only 0.25V for up to 50mA
desired load currents. Always place the 0.1

F power-supply

decoupling capacitors after these supply current limiting
resistors directly on the supply pins.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC--including additional
external capacitance which may be recommended to im-

prove ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA683 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier's open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.

The Typical Characteristics show the recommended "R

Capacitive Load" and the resulting frequency response at the
load. The 1k

resistor shown in parallel with the load

capacitor is a measurement path and may be omitted.
Parasitic capacitive loads greater than 3pF can begin to
degrade the performance of the OPA683. Long PC board
traces, unmatched cables, and connections to multiple de-
vices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA683 output pin
(see Board Layout Guidelines).

DISTORTION PERFORMANCE

The OPA683 provides low distortion in a very low power
amplifier. The CFB

plus

architecture also gives two significant

areas of distortion improvement. First, in operating regions
where the 2nd-harmonic distortion due to output stage
nonlinearities is very low (frequencies < 1MHz, low output
swings into light loads) the linearization at the inverting node
provided by the CFB

plus

design gives 2nd-harmonic distor-

tions that extend into the 90dBc region. Previous current
feedback amplifiers have been limited to approximately
85dBc due to the nonlinearities at the inverting input. The
second area of distortion improvement comes in a distortion
performance that is more gain independent than prior solu-
tions. To the extent that the distortion at a particular output
power is output stage dependent, 2nd-harmonic particularly,
and to a lesser extend 3rd-harmonic distortion, is constant as
the gain is increased. This is due to the constant loop gain
versus signal gain provided by the CFB

plus

design. As shown

in the Typical Characteristics, while the 2nd-harmonic is
constant with gain, the 3rd-harmonic degrades at higher
gains.

Relative to alternative amplifiers with < 1mA supply current,
the OPA683 holds much lower distortion at higher frequen-
cies (> 5MHz) and to higher gains. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with a
lower 3rd-harmonic component. Focusing then on the 2nd-
harmonic, increasing the load impedance improves distortion
slightly for the OPA683. Remember that the total load in-

OPA683

SBOS221B

www.ti.com

cludes the feedback network--in the noninverting configura-
tion (see Figure 1) this is the sum of R

+ R

, while in the

inverting configuration it is just R

. Also, providing an addi-

tional supply decoupling capacitor (0.1

F) between the sup-

ply pins (for bipolar operation) improves the 2nd-order distor-
tion slightly (3dB to 6dB).

In most op amps, increasing the output voltage swing in-
creases harmonic distortion directly. A low-power part like the
OPA683 includes quiescent boost circuits to provide the full-
power bandwidth shown. These act to increase the bias in a
very linear fashion only when high slew rate or output power
are required. The Typical Characteristics show the 2nd-har-
monic increasing slightly from 500mVp-p to 5Vp-p outputs
while the 3rd-harmonics also increase with output power.

The OPA683 has an extremely low 3rd-order harmonic distor-
tion--particularly for light loads and at lower frequencies. This
also gives low 2-tone, 3rd-order intermodulation distortion as
shown in the Typical Characteristics. Since the OPA683
includes internal power boost circuits to retain good full-power
performance at high frequencies and outputs, it does not show
a classical 2-tone, 3rd-order intermodulation intercept charac-
teristic. Instead, it holds relatively low and constant 3rd-order
intermodulation spurious levels over power. The Typical Char-
acteristics show this spurious level as a dBc below the carrier
at fixed center frequencies swept over single-tone voltage
swing at a 1k

load. Very light loads such as ADC inputs for

will see < 85dBc 3rd-order spurious to 1MHz for full-scale
inputs. For much lower 3rd-order intermodulation distortion
through 200MHz, consider the OPA685.

NOISE PERFORMANCE

Wideband current-feedback op amps generally have a higher
output noise than comparable voltage feedback op amps. The
OPA683 offers an excellent balance between voltage and
current noise terms to achieve low output noise in a low- power
amplifier. The inverting current noise (11.6pA/

Hz) is lower

than most other current feedback op amps while the input
voltage noise (4.4nV/

Hz) is lower than any unity-gain stable,

comparable slew rate, voltage feedback op amp. This low input
voltage noise was achieved at the price of higher noninverting
input current noise (5.1pA/

Hz). As long as the AC source

impedance looking out of the noninverting node is less than
300

, this current noise will not contribute significantly to the

total output noise. The op amp input voltage noise and the two
input current noise terms combine to give low output noise
under a wide variety of operating conditions. Figure 13 shows
the op amp noise analysis model with all the noise terms
included. In this model, all noise terms are taken to be noise
voltage or current density terms in either nV/

Hz or pA/

Hz.

The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 3 shows the general form for the
output noise voltage using the terms shown in Figure 13.

(3)

kTR

I R

kTR G

BN S

BI F

(

)

(

)

4kT

OPA683

4kT = 1.6E 20J

at 290

4kTR

Dividing this expression by the noise gain (NG = (1 + R

))

will give the equivalent input referred spot noise voltage at the
noninverting input, as shown in Equation 4.

(4)

kTR

I R

kTR

BN S

BI F

(

)

Evaluating these two equations for the OPA683 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 17.6nV/

Hz and a total equivalent input spot

noise voltage of 8.8nV/

Hz. This total input referred spot

noise voltage is higher than the 4.4nV/

Hz specification for

the op amp voltage noise alone. This reflects the noise
added to the output by the inverting current noise times the
feedback resistor. As the gain is increased, this fixed output
noise power term contributes less to the total output noise
and the total input referred voltage noise given by Equation
3 will approach just the 4.4nV/

Hz of the op amp itself. For

example, going to a gain of +20 in the circuit of Figure 1,
adjusting only the gain resistor to 63.2

, will give a total input

referred noise of 4.6nV/

Hz. A more complete description of

op amp noise analysis can be found in the TI application note
AB-103 (SBOA066). Refer to Texas Instruments' web site
www.ti.com.

DC ACCURACY AND OFFSET CONTROL

A current-feedback op amp like the OPA683 provides excep-
tional bandwidth in high gains, giving fast pulse settling but
only moderate DC accuracy. The Electrical Characteristics
show an input offset voltage comparable to high slew rate
voltage-feedback amplifiers. However, the two input bias
currents are somewhat higher and are unmatched. Whereas
bias current cancellation techniques are very effective with
most voltage feedback op amps, they do not generally
reduce the output DC offset for wideband current-feedback
op amps. Since the two input bias currents are unrelated in
both magnitude and polarity, matching the source imped-
ance looking out of each input to reduce their error contribu-
tion to the output is ineffective. Evaluating the configuration
of Figure 1, using worst case +25

C input offset voltage and

FIGURE 13. Op Amp Noise Analysis Model.

OPA683

SBOS221B

www.ti.com

the two input bias currents, gives a worst case output offset
range equal to:

(NG · V

OS(MAX)

)

· R

/2 · NG)

· R

)

where

NG = noninverting signal gain

(2 · 3.5mV)

A · 25

· 2)

(1.2k

· 10

7mV

0.1mV

12mV

19.1mV

While the last term, the inverting bias current error, is dominant
in this low-gain circuit, the input offset voltage will become the
dominant DC error term as the gain exceeds 4V/V. Where
improved DC precision is required in a high-speed amplifier,
consider the OPA642 single and OPA2822 dual voltage-
feedback amplifiers.

DISABLE OPERATION

The OPA683 provides an optional disable feature that may
be used to reduce system power when channel operation is
not required. If the V

DIS

control pin is left unconnected, the

OPA683 will operate normally. To disable, the control pin
must be asserted LOW. Figure 14 shows a simplified internal
circuit for the disable control feature.

In normal operation, base current to Q1 is provided through
the 250k

resistor while the emitter current through the 40k

resistor sets up a voltage drop that is inadequate to turn on
the two diodes in Q1's emitter. As V

DIS

is pulled LOW,

additional current is pulled through the 40k

resistor eventu-

ally turning on these two diodes (

A). At this point, any

further current pulled out of V

DIS

goes through those diodes

holding the emitter-base voltage of Q1 at approximately 0V.

25k

250k

40k

Control

DIS

FIGURE 14. Simplified Disable Control Circuit.

This shuts off the collector current out of Q1, turning the
amplifier off. The supply current in the disable mode are only
those required to operate the circuit of Figure 14.

When disabled, the output and input nodes go to a high
impedance state. If the OPA683 is operating in a gain of +1
(with a 1.2k

feedback resistor still required for stability), this

will show a very high impedance (1.7pF || 1M

) at the output

and exceptional signal isolation. If operating at a gain greater
than +1, the total feedback network resistance (R

+ R

) will

appear as the impedance looking back into the output, but
the circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the input and
output will be connected through the feedback network
resistance (R

+ R

) giving relatively poor input to output

isolation.

The OPA683 provides very high power gain on low quiescent
current levels. When disabled, internal high impedance nodes
discharge slowly which, with the exceptional power gain
provided, give a self powering characteristic that leads to a
slow turn off characteristic. Typical full turn off times to rated
100

A disabled supply current are 60ms. Turn on times are

very fast--less than 40ns.

THERMAL ANALYSIS

The OPA683 will not require external heat-sinking for most
applications. Maximum desired junction temperature will set
the maximum allowed internal power dissipation as de-
scribed below. In no case should the maximum junction
temperature be allowed to exceed 175

Operating junction temperature (T

) is given by T

+ P

The total internal power dissipation (P

) is the sum of

quiescent power (P

) and additional power dissipated in the

output stage (P

) to deliver load power. Quiescent power is

simply the specified no-load supply current times the total
supply voltage across the part. P

will depend on the

required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition P

= V

/(4 · R

) where R

includes feedback network loading.

Note that it is the power in the output stage and not into the
load that determines internal power dissipation.

As an absolute worst case example, compute the maximum
T

using an OPA683IDBV (SOT23-6 package) in the circuit

of Figure 1 operating at the maximum specified ambient
temperature of +85

C and driving a grounded 100

load.

= 10V · 1.05mA + 5

/(4 · (100

|| 2.4k

)) = 76mW

Maximum T

= +85

C + (0.076W · 150

C/W) = 96

This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
than this since an absolute worst case output stage power
was assumed in this calculation.

OPA683

SBOS221B

www.ti.com

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high frequency am-
plifier like the OPA683 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for

all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on
the noninverting input, it can react with the source imped-
ance to cause unintentional band-limiting.. To reduce
unwanted capacitance, a window around the signal I/O
pins should be opened in all of the ground and power
planes around those pins. Otherwise, ground and power
planes should be unbroken elsewhere on the board.

b) Minimize the distance (< 0.25") from the power-supply

pins to high frequency 0.1

F decoupling capacitors.

At the device pins, the ground and power-plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize induc-
tance between the pins and the decoupling capacitors.
The power-supply connections should always be decoupled
with these capacitors. An optional supply decoupling
capacitor across the two power supplies (for bipolar op-
eration) will improve 2nd-harmonic distortion performance.
Larger (2.2

F to 6.8

F) decoupling capacitors, effective at

lower frequency, should also be used on the main supply
pins. These may be placed somewhat farther from the
device and may be shared among several devices in the
same area of the PC board.

c) Careful selection and placement of external compo-

nents will preserve the high frequency performance
of the OPA683. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a
tighter overall layout. Metal film and carbon composition
axially-leaded resistors can also provide good high fre-
quency performance. Again, keep their leads and PC
board trace length as short as possible. Never use wire-
wound type resistors in a high-frequency application.
Since the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input termination resistors, should
also be placed close to the package. Where double side
component mounting is allowed, place the feedback resis-
tor directly under the package on the other side of the
board between the output and inverting input pins. The
frequency response is primarily determined by the feed-
back resistor value as described previously. Increasing its
value will reduce the peaking at higher gains, while
decreasing it will give a more peaked frequency response
at lower gains. The 1.2k

feedback resistor used in the

Electrical Characteristics at a gain of +2 on

5V supplies

is a good starting point for design. Note that a 1.2k

feedback resistor, rather than a direct short, is required for
the unity-gain follower application. A current-feedback op
amp requires a feedback resistor even in the unity-gain
follower configuration to control stability.

d) Connections to other wideband devices on the board

may be made with short direct traces or through
onboard transmission lines. For short connections, con-
sider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the total
capacitive load and set R

from the plot of recommended

versus capacitive load. Low parasitic capacitive loads

(< 5pF) may not need an R

since the OPA683 is

nominally compensated to operate with a 2pF parasitic
load. If a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is ac-
ceptable, implement a matched impedance transmission
line using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline layout
techniques). A 50

environment is normally not neces-

sary on board, and in fact a higher impedance environ-
ment will improve distortion as shown in the distortion
versus load plots. With a characteristic board trace imped-
ance defined based on board material and trace dimen-
sions, a matching series resistor into the trace from the
output of the OPA683 is used as well as a terminating
shunt resistor at the input of the destination device.
Remember also that the terminating impedance will be
the parallel combination of the shunt resistor and the input
impedance of the destination device: this total effective
impedance should be set to match the trace impedance.
The high output voltage and current capability of the
OPA683 allows multiple destination devices to be handled
as separate transmission lines, each with their own series
and shunt terminations. If the 6dB attenuation of a doubly-
terminated transmission line is unacceptable, a long trace
can be series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the series
resistor value as shown in the plot of "R

vs Capacitive

Load". This will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is LOW, there will be some signal
attenuation due to the voltage divider formed by the series
output into the terminating impedance.

e) Socketing a high-speed part like the OPA683 is not

recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the
OPA683 onto the board.

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